CN106887255A - A kind of process plate structure of dual port RAM test equipment - Google Patents
A kind of process plate structure of dual port RAM test equipment Download PDFInfo
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- CN106887255A CN106887255A CN201510936952.9A CN201510936952A CN106887255A CN 106887255 A CN106887255 A CN 106887255A CN 201510936952 A CN201510936952 A CN 201510936952A CN 106887255 A CN106887255 A CN 106887255A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000008569 process Effects 0.000 title claims abstract description 55
- 238000012360 testing method Methods 0.000 title claims abstract description 29
- 230000009977 dual effect Effects 0.000 title claims abstract description 23
- 230000007613 environmental effect Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5604—Display of error information
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Abstract
The invention belongs to field of electric control, and in particular to a kind of process plate structure of dual port RAM test equipment, including housing, display screen and the display screen connection mainboard, process plate and process plate connection the interfaces of SCSI 68；The mainboard is connected with process plate by PCI E interfaces；The process plate includes PCI E bridging chips, FPGA, drive circuit, power module；The PCI E interfaces are connected by PCI E bridging chips with FPGA；The FPGA is electrically connected with drive circuit；By by all test equipment Highgrade integrations, using 10 cun of Flat computer structures, saving space and being easy to carry, environmental suitability strengthens the present invention, and to be adapted to climb carry out operation into low；In addition, the structure of process plate uses RAM signal FPGA gigabit Ethernet PCIE frameworks so that read or write speed is significantly high, saves a large amount of manpowers, improves testing efficiency.
Description
Technical field
The invention belongs to field of electric control, and in particular to a kind of process plate structure of dual port RAM test equipment.
Background technology
In existing practical engineering application, dual port RAM test equipment is not an entirety, its test module is relatively discrete, all use separate devices, equipment volume is big, and existing improving equipment be mostly portable industrial pc structure, it is thicker than notebook computer 2-3 times, weight is in more than 10kg, manual workload in test process is big, particularly operation is carried out in the low environment that climb, efficiency is low, it is poor for applicability, particularly, PCIE special chip frameworks are used in process plate structure in existing dual port RAM test equipment, its read or write speed is slow, so that testing efficiency is low, can not meet testing requirement.Based on the problems present on and defect, it is necessary to related test system is improved and is transformed.
The content of the invention
The purpose of the present invention is the disadvantages mentioned above for overcoming prior art, there is provided a kind of process plate structure of dual port RAM test equipment.
To achieve these goals, the technical solution adopted in the present invention is：A kind of process plate structure of dual port RAM test equipment, including housing, display screen and the display screen connection mainboard, process plate and process plate connection SCSI-68 interfaces；The mainboard is connected with process plate by PCI-E interface；The display screen, mainboard, PCI-E interface, process plate, SCSI-68 interfaces may be contained within enclosure interior；The process plate includes PCI-E bridging chips, FPGA, drive circuit, power module；The PCI-E interface is connected by PCI-E bridging chips with FPGA；The power module is connected with PCI-E bridging chips, FPGA, drive circuit respectively；The FPGA is electrically connected by drive circuit with SCSI-68 interfaces.
A kind of process plate structure of above-mentioned dual port RAM test equipment, the PCI-E bridging chips are RTL8111E.
A kind of process plate structure of above-mentioned dual port RAM test equipment, the power module uses switch power module.
A kind of process plate structure, including drive circuit, the power module that PCI-E bridging chips are connected with PCI-E bridging chips；The power module is connected with PCI-E bridging chips, drive circuit respectively.
A kind of above-mentioned process plate structure, the PCI-E bridging chips are CH368.
A kind of above-mentioned process plate structure, uses dual power supply bus driver chip SN74LVC4245A in the drive circuit.
Beneficial effects of the present invention：By by all test equipment Highgrade integrations, using 10 cun of Flat computer structures, saving space and being easy to carry, environmental suitability strengthens the present invention, and to be adapted to climb carry out operation into low；In addition, the structure of process plate uses RAM signal-FPGA- gigabit Ethernet-PCIE frameworks so that read or write speed is significantly high, saves a large amount of manpowers, improves testing efficiency.
Brief description of the drawings
The present invention is specifically described below by accompanying drawing and in conjunction with the embodiments, advantages of the present invention and implementation will be more obvious, and wherein content is only used for explanation of the present invention shown in accompanying drawing, without constituting to the limitation gone up in all senses of the invention.
Fig. 1 is a kind of structural representation of the process plate structure of dual port RAM test equipment of the invention；
Fig. 2 is a kind for the treatment of plate structure schematic diagram of the process plate constructive embodiment 2 of dual port RAM test equipment of the invention；
Fig. 3 is a kind for the treatment of plate structure schematic diagram of the process plate constructive embodiment 3 of dual port RAM test equipment of the invention；
Description of reference numerals：1st, housing；2nd, display screen；3rd, mainboard；4th, PCI-E interface；5th, process plate；6th, SCSI-68 interfaces；7th, PCI-E bridging chips；8、FPGA；9th, drive circuit；10th, power module.
Specific embodiment
Embodiments of the invention are elaborated below：The present embodiment is implemented under premised on technical solution of the present invention, gives detailed implementation method and specific operating process.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, can also make some variations and modifications, these belong to the scope of the present invention.
Embodiment 1：
As shown in figure 1, a kind of dual port RAM test equipment, including the mainboard 3, process plate 5 and the connection of process plate 5 of housing 1, display screen 2 and the display screen 2 connection SCSI-68 interfaces 6；The mainboard 3 is connected with process plate 5 by PCI-E interface 4；The display screen 2, mainboard 3, PCI-E interface 4, process plate 5, SCSI-68 interfaces 6 may be contained within inside housing 1.
Wherein, dual port RAM data processing plate 5（Hereinafter referred to as process plate 5）It is main complete the conversion of dual port RAM read-write sequence and PCI Bridge connect chip dock, interrupts it is temporary, store and the function such as forward.
The SCSI-68 interfaces 6 are connected by SCSI cables with equipment under test, and cable one end is conveniently docked using the male of SCSI-68 with test equipment；One end is using the air plug of CHCX36T55KP and CHCX33T41KP to be docked with equipment under test.
Embodiment 2：
On the basis of embodiment 1, as shown in Fig. 2 the process plate 5 includes PCI-E bridging chips 7, FPGA 8, drive circuit 9, power module 10；The PCI-E interface 4 is connected by PCI-E bridging chips 7 with FPGA 8；The power module 10 is connected with PCI-E bridging chips 7, FPGA 8, drive circuit 9 respectively；The FPGA 8 is electrically connected by drive circuit 9 with SCSI-68 interfaces 6.
Wherein, PCI-E bridging chips 7 are RTL8111E, and the read or write speed of the program is high, and design of hardware and software is complex.PCI-E is converted to gigabit ethernet interface by RTL8111E, and gigabit ethernet interface is converted to RGMII interfaces by 88E1111, and FPGA completes the conversion between RGMII and dual port RAM；
Four kinds of power supply requirements are had in the scheme in the embodiment 2 to be respectively：
1) 5V power supplys：Power supply is provided to driving chip cable-side, is consistent with IDT7024 level；
2) 3.3V power supplys：Powered to FPGA portion Bank and used；
3) 2.5V power supplys：The module for needing 2.5V to power is more, is respectively VDDO, VDDOX, VDDOH, AVDD of part Bank, 88E1111 of PLL, FPGA of FPGA；
4) 1.2V power supplys：The core voltage of FPGA and the digital power of 88E1111.
It is relatively good mode from switch power module, reason is that module maturity high stability is good and the switch power efficiency battery supply set that is very suitable for high is used.
Upper electricity shutdown power-off of how realizing starting shooting is also to need the emphasis in scheme to consider that, in order to reduce development amount, the power management in scheme using mainboard is managed to process plate.5V power supplys on mainboard only can just be provided when start, and using this feature, 12V (battery voltage) power supply for carrying out control process plate using a small-sized 5V relay in scheme is powered.During start on mainboard 5V power supplys start power supply control relay conducting start to be powered for process plate, during shutdown on mainboard 5V power supplys be cut off relay also therewith disconnection process plate power supply be cut off.
Embodiment 3：
On the basis of embodiment 1, as shown in figure 3, the process plate 5 includes drive circuit 9, the power module 10 that PCI-E bridging chips 7 are connected with PCI-E bridging chips 7；The power module 10 is connected with PCI-E bridging chips 7, drive circuit 9 respectively；Dual power supply bus driver chip SN74LVC4245A is used in the drive circuit 9.
Wherein, PCI-E bridging chips 7 are CH368, and the read or write speed of the program is somewhat low, but cause that circuit design is relatively simple with exploitation the characteristics of due to CH368, and risk is also more relatively low.CH368 is a common interface chip for connection PCI-Express buses, supports I/O port mappings, memory mapping, expansion ROM and interruption.High-speed PCI E general line systems are easy to be easy-to-use similar to 32 of ISA buses or 8 active parallel interfaces by CH368, the computer card based on PCIE buses for making low cost, and original board based on ISA buses or PCI buses is upgraded in PCIE buses.PCIE buses compared with other main flow buses, speed faster, real-time more preferably, controllability more preferably, so CH368 is applied at a high speed I/O control cards, communication interface card, data collecting card etc. in real time.
Four kinds of power supply requirements are had in the scheme in the embodiment 3 to be respectively：
1) numeral 5V power supplys：Power supply is provided to driving chip cable-side, is consistent with IDT7024 level；
2) numeral 3.3V power supplys：Chip side to CH368, EEPROM, driving chip provides power supply；
3) numeral 1.8V power supplys：The core voltage of CH368 is powered；
4) 1.8V power supplys are simulated：CH368 PCI-E differential drive voltages.
Because the power consumption of 5V and 3.3V is smaller, can both be powered using onboard LDO, it is also possible to external power supply module for power supply.Rule of thumb and experiment, be relatively good mode from switch power module, reason is that module maturity high stability is good and the switch power efficiency battery supply set that is very suitable for high is used.
Upper electricity shutdown power-off of how realizing starting shooting is also to need the emphasis in scheme to consider that, in order to reduce development amount, the power management in scheme using mainboard is managed to process plate.5V power supplys on mainboard only can just be provided when start, and using this feature, 12V (battery voltage) power supply for carrying out control process plate using a small-sized 5V relay in scheme is powered.During start on mainboard 5V power supplys start power supply control relay conducting start to be powered for process plate, during shutdown on mainboard 5V power supplys be cut off relay also therewith disconnection process plate power supply be cut off.
The above is preferred exemplary applications of the invention, not limitation of the present invention, and every simple modification made according to technical key point, structure change change are belonged within protection scope of the present invention.
Claims (6)
1. a kind of process plate structure of dual port RAM test equipment, including housing（1）, display screen（2）With the display screen（2）The mainboard of connection（3）, process plate（5）With process plate（5）The SCSI-68 interfaces of connection（6）；The mainboard（3）With process plate（5）By PCI-E interface（4）It is connected；The display screen（2）, mainboard（3）, PCI-E interface（4）, process plate（5）, SCSI-68 interfaces（6）May be contained within housing（1）It is internal；It is characterized in that：
The process plate（5）Including PCI-E bridging chips（7）、FPGA（8）, drive circuit（9）, power module（10）；The PCI-E interface（4）By PCI-E bridging chips（7）With FPGA（8）It is connected；The power module（10）Respectively with PCI-E bridging chips（7）、FPGA（8）, drive circuit（9）Connection；The FPGA（8）By drive circuit（9）With SCSI-68 interfaces（6）Electrically connect.
2. the process plate structure of a kind of dual port RAM test equipment according to claim 1, it is characterised in that：The PCI-E bridging chips（7）It is RTL8111E.
3. the process plate structure of a kind of dual port RAM test equipment according to claim 1, it is characterised in that：The power module（10）Using switch power module.
4. a kind of process plate structure, it is characterised in that：Including PCI-E bridging chips（7）With PCI-E bridging chips（7）Connected drive circuit（9）, power module（10）；The power module（10）Respectively with PCI-E bridging chips（7）, drive circuit（9）It is connected.
5. a kind of process plate structure according to claim 4, it is characterised in that：The PCI-E bridging chips（7）It is CH368.
6. a kind of process plate structure according to claim 4, it is characterised in that：The drive circuit（9）Middle use dual power supply bus driver chip SN74LVC4245A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510936952.9A CN106887255A (en) | 2015-12-15 | 2015-12-15 | A kind of process plate structure of dual port RAM test equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510936952.9A CN106887255A (en) | 2015-12-15 | 2015-12-15 | A kind of process plate structure of dual port RAM test equipment |
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| CN106887255A true CN106887255A (en) | 2017-06-23 |
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| CN201510936952.9A Pending CN106887255A (en) | 2015-12-15 | 2015-12-15 | A kind of process plate structure of dual port RAM test equipment |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638079A (en) * | 2003-12-22 | 2005-07-13 | 株式会社瑞萨科技 | Fabrication method of semiconductor integrated circuit device |
| US20080201515A1 (en) * | 2007-02-20 | 2008-08-21 | Scott Birgin | Method and Systems for Interfacing With PCI-Express in an Advanced Mezannine Card (AMC) Form Factor |
| CN101957806A (en) * | 2010-09-14 | 2011-01-26 | 浙江大学 | Peripheral component interconnection standard acquisition device for synchronous serial interface signal |
| CN203675243U (en) * | 2014-01-14 | 2014-06-25 | 昆山丘钛微电子科技有限公司 | Camera image transmission device based on PCI-E port |
| CN104965469A (en) * | 2015-07-06 | 2015-10-07 | 浙江大学 | CPCI bus standard-based multi-function acquisition control device |
| CN205451778U (en) * | 2015-12-15 | 2016-08-10 | 西安富成防务科技有限公司 | Two port RAM test equipment's processing plate structure |
-
2015
- 2015-12-15 CN CN201510936952.9A patent/CN106887255A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1638079A (en) * | 2003-12-22 | 2005-07-13 | 株式会社瑞萨科技 | Fabrication method of semiconductor integrated circuit device |
| US20080201515A1 (en) * | 2007-02-20 | 2008-08-21 | Scott Birgin | Method and Systems for Interfacing With PCI-Express in an Advanced Mezannine Card (AMC) Form Factor |
| CN101957806A (en) * | 2010-09-14 | 2011-01-26 | 浙江大学 | Peripheral component interconnection standard acquisition device for synchronous serial interface signal |
| CN203675243U (en) * | 2014-01-14 | 2014-06-25 | 昆山丘钛微电子科技有限公司 | Camera image transmission device based on PCI-E port |
| CN104965469A (en) * | 2015-07-06 | 2015-10-07 | 浙江大学 | CPCI bus standard-based multi-function acquisition control device |
| CN205451778U (en) * | 2015-12-15 | 2016-08-10 | 西安富成防务科技有限公司 | Two port RAM test equipment's processing plate structure |
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Application publication date: 20170623 |