CN106856191A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the semiconductor structure includes: providing a semiconductor substrate; forming a mask layer with an opening on the surface of the semiconductor substrate; etching the semiconductor substrate along the opening to form a first groove; form an isolation layer located in the first groove and the opening, the surface of the isolation layer is flush with the surface of the mask layer; remove the mask layer to form a second groove; form a surface lower than The first silicon germanium layer on the surface of the isolation layer; an amorphous silicon germanium layer filling the second groove and covering the isolation layer is formed on the surface of the first silicon germanium layer; a solid phase epitaxial growth process is adopted to make the silicon germanium layer on the surface Part of the amorphous silicon germanium layer is transformed into a third silicon germanium layer; the amorphous silicon germanium layer and the third silicon germanium layer are planarized by using the isolation layer as a stop layer; the isolation layer is etched back to make the surface of the isolation layer lower on the surface of the third silicon germanium layer. The methods described above can improve the performance of semiconductor structures.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate-last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and the fin field effect transistor (Fin FET) as Substitution of conventional devices has received extensive attention. The FinFET usually includes a fin, a gate structure across the fin, and source and drain electrodes located in the fin on both sides of the gate structure.

In order to further improve the performance of semiconductor devices, semiconductor material germanium has also been widely used. Compared with silicon, germanium has higher mobility of electrons and holes, so it can be used in semiconductor devices, especially as a channel region material of transistors, which can effectively improve the performance of semiconductor devices. Using semiconductor materials containing germanium, such as silicon germanium, to form a fin field effect transistor can effectively improve the performance of the transistor.

In the prior art, silicon germanium is used to form the fin portion of the fin field effect transistor, and the concentration of germanium at different positions of the fin portion is the same, which cannot meet the requirements of different transistors, and the performance of the fin field effect transistor needs to be further improved.

Contents of the invention

The problem solved by the present invention is to provide a semiconductor structure and its forming method, improve the performance of the semiconductor structure, so as to improve the performance of the fin field effect transistor formed on the basis of the semiconductor structure.

In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate; forming a mask layer with openings on the surface of the semiconductor substrate to expose part of the surface of the semiconductor substrate; The opening etches the semiconductor substrate, forming a first groove in the semiconductor substrate; forming an isolation layer located in the first groove and the opening, and the surface of the isolation layer is flush with the surface of the mask layer; removing the mask film layer, forming a second groove; forming a first silicon germanium layer in the second groove, the surface of the first silicon germanium layer is lower than the surface of the isolation layer; forming a second groove on the surface of the first silicon germanium layer And cover the amorphous silicon germanium layer of the isolation layer; adopt the solid phase epitaxial growth process to transform part of the amorphous silicon germanium layer on the surface of the first silicon germanium layer into a third silicon germanium layer, the surface of the third silicon germanium layer is higher than The surface of the isolation layer: the amorphous silicon germanium layer and the third silicon germanium layer are planarized using the isolation layer as a stop layer; the isolation layer is etched back to make the surface of the isolation layer lower than the surface of the third silicon germanium layer.

Optionally, the germanium concentration in the first silicon germanium layer is different from that in the third silicon germanium layer.

Optionally, the concentration of germanium in the first silicon germanium layer ranges from 15% to 45%, and the concentration of germanium in the third silicon germanium layer ranges from 25% to 35%.

Optionally, the first silicon germanium layer is formed by using a selective epitaxy process.

Optionally, the height of the first silicon germanium layer is 1/3˜1/2 of the depth of the second groove.

Optionally, the amorphous silicon germanium layer is formed by using a chemical vapor deposition process.

Optionally, the silicon source gas used in the chemical vapor deposition process is SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , the temperature is 400° C.-600° C., and the pressure is 5 Torr-100 Torr.

Optionally, the growth temperature of the solid phase epitaxial growth process is 600°C-800°C.

The technical solution of the present invention also provides a semiconductor structure formed by the above method, including: a semiconductor substrate; a first groove located in the semiconductor substrate; an isolation layer located in the first groove, and the surface of the isolation layer Higher than the surface of the semiconductor substrate; the first silicon germanium layer on the surface of the semiconductor substrate between adjacent isolation layers; the third silicon germanium layer on the surface of the first silicon germanium layer, the surface of the third silicon germanium layer is higher than Isolation layer surface.

The technical solution of the present invention also provides another method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region; forming a first mask with an opening on the surface of the semiconductor substrate; The film layer exposes part of the surface of the first region and the second region of the semiconductor substrate; etching the semiconductor substrate along the opening to form a first groove in the first region and the second region of the semiconductor substrate; forming An isolation layer located in the first groove and the opening, the surface of the isolation layer is flush with the surface of the first mask layer; the first mask layer is removed, the second groove is formed in the first region, and the second groove is formed in the second region. Three grooves; forming a second mask layer covering the first region of the semiconductor substrate; forming a first silicon germanium layer in the third groove, the surface of the first silicon germanium layer being lower than the surface of the isolation layer; removing the second mask layer Finally, forming a third mask layer covering the second region of the semiconductor substrate; forming a second silicon germanium layer in the second groove, the surface of the second silicon germanium layer is lower than the surface of the isolation layer; removing the third mask layer, An amorphous silicon germanium layer is formed on the surface of the first silicon germanium layer and the second silicon germanium layer, and the amorphous silicon germanium layer fills the second groove and the third groove and covers the isolation layer; The solid phase epitaxial growth process transforms part of the amorphous silicon germanium layer on the surface of the first silicon germanium layer and the second silicon germanium layer into a third silicon germanium layer, and the surface of the third silicon germanium layer is higher than the surface of the isolation layer; As a stop layer, the amorphous silicon germanium layer and the third silicon germanium layer are planarized; the isolation layer is etched back so that the surface of the isolation layer is lower than the surface of the third silicon germanium layer.

Optionally, the germanium concentration in the first silicon germanium layer is higher than the germanium concentration in the third silicon germanium layer, and the germanium concentration in the second silicon germanium layer is lower than the germanium concentration in the third silicon germanium layer.

Optionally, the concentration range of germanium in the first silicon germanium layer is 35-45%, the concentration range of germanium in the second silicon germanium layer is 15-25%, and the concentration range of germanium in the third silicon germanium layer is 25%. ~35%.

Optionally, the first silicon germanium layer and the second silicon germanium layer are formed by using a selective epitaxy process.

Optionally, the height of the first silicon germanium layer is 1/3 to 1/2 of the depth of the third groove; the height of the second silicon germanium layer is 1/3 to 1/2 of the depth of the second groove. 2.

Optionally, the amorphous silicon germanium layer is formed by using a chemical vapor deposition process.

Optionally, the silicon source gas used in the chemical vapor deposition process is SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , the temperature is 400° C.-600° C., and the pressure is 5 Torr-100 Torr.

Optionally, the growth temperature of the solid phase epitaxial growth process is 600°C-800°C.

Optionally, the method for forming the second mask layer includes: forming a second mask material layer covering the isolation layer and the semiconductor substrate; forming a patterned photoresist layer on the surface of the second mask material layer; Using the patterned photoresist layer as a mask, etching the second mask material layer, removing the second mask material layer on the second region of the semiconductor substrate, exposing the isolation layer and the second region A second mask layer covering the first region is formed on the semiconductor substrate.

Optionally, the method for forming the third mask layer includes: forming a third mask material layer covering the isolation layer and the semiconductor substrate; forming a patterned photoresist layer on the surface of the third mask material layer; Using the patterned photoresist layer as a mask, etching the third mask material layer, removing the third mask material layer on the first region of the semiconductor substrate, exposing the isolation layer and the first region A semiconductor substrate, forming a third mask layer covering the second region.

The technical solution of the present invention also provides another semiconductor structure formed by the above method, including: a semiconductor substrate, the semiconductor substrate includes a first region and a second region; The first groove in the first groove; the isolation layer located in the first groove, the surface of the isolation layer is higher than the surface of the semiconductor substrate; the second silicon germanium layer on the surface of the first region of the semiconductor substrate between the adjacent isolation layers The first silicon germanium layer on the surface of the second region of the semiconductor substrate between adjacent isolation layers; the third silicon germanium layer on the surface of the first silicon germanium layer and the second silicon germanium layer, the third silicon germanium layer The surface of the silicon layer is higher than the surface of the isolation layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the first silicon germanium layer is formed on the semiconductor substrate, and then an amorphous silicon germanium layer is formed on the surface of the first silicon germanium layer, and then the silicon germanium layer located on the first silicon germanium layer is formed by a solid phase epitaxy process. Part of the amorphous silicon germanium layer on the surface of the layer is transformed into a third silicon germanium layer, and the first silicon germanium layer and the third silicon germanium layer are used as a part of the fin. During the solid phase epitaxial growth process, the atoms located in the amorphous silicon germanium layer will first fill the lattice defect positions on the surface of the first silicon germanium layer, so that the sharp corners on the top of the first silicon germanium layer disappear, forming a flat interface. There are fewer defects, which can increase the carrier mobility in the first silicon germanium layer and the third silicon germanium layer, thereby improving the performance of the semiconductor structure.

Further, the concentration of germanium in the first silicon-germanium layer is different from that in the third silicon-germanium layer. By adjusting the concentration of germanium in the first silicon-germanium layer and the third silicon-germanium layer, the fins can meet the requirements of transistors with different performances. In order to further improve the performance of the fin field effect transistor formed on this basis.

In the technical solution of the present invention, a method for forming a semiconductor structure is also provided, wherein a second silicon germanium layer is formed on the first region of the semiconductor substrate, a first silicon germanium layer is formed on the second region, and then the second silicon germanium layer is formed on the first region. An amorphous silicon germanium layer is formed on the surface of the silicon germanium layer and the second silicon germanium layer, and through a solid phase epitaxy process, part of the amorphous silicon germanium layer on the surface of the first silicon germanium layer and the second silicon germanium layer is transformed into a third silicon germanium layer Floor. The first silicon germanium layer and the third silicon germanium layer on the first region are used as part of the fins on the first region, and the second silicon germanium layer and the third silicon germanium layer on the surface are used as fins on the second region part of the department. During the solid phase epitaxial growth process, the atoms located in the amorphous silicon germanium layer will first fill the lattice defect positions on the surface of the first silicon germanium layer and the second silicon germanium layer, so that the top of the first silicon germanium layer and the second silicon germanium layer The sharp corners disappear, forming a smooth interface, and there are fewer defects on the interface, which can improve the carrier mobility in the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer, and then improve the semiconductor structure. performance.

Further, the third silicon germanium layer and the first silicon germanium layer are used as part of the fin on the first region, both of which have different concentrations of germanium; the third silicon germanium layer and the second silicon germanium layer are used as the part of the fin, the two also have different germanium concentrations. Moreover, the germanium concentration of the third silicon germanium layer is lower than the germanium concentration of the first silicon germanium layer; the germanium concentration of the third silicon germanium layer is greater than the germanium concentration of the second silicon germanium layer; thus making the first region and the second The regions are respectively suitable for forming fin field effect transistors of different performances or types, which can improve the performance of different types of fin field effect transistors.

Description of drawings

1 to 10 are structural schematic diagrams of the formation process of a semiconductor structure according to an embodiment of the present invention;

11 to 22 are structural schematic diagrams of the formation process of the semiconductor structure according to an embodiment of the present invention.

detailed description

As mentioned in the background technology, in the prior art, the concentration of germanium in the fin formed by silicon germanium material is the same at different positions, which cannot meet the needs of different transistors, which will affect the fin field effect formed on this basis. Transistor performance.

In other embodiments of the present invention, forming the fin includes a lower portion and an upper portion, wherein the concentrations of germanium in the upper portion and the lower portion of the fin are different to meet the requirements of different transistors.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 10 are schematic views of the formation process of the semiconductor structure according to the first embodiment of the present invention.

Referring to FIG. 1 , a semiconductor substrate 100 is provided, and a mask material layer 101 is formed on the surface of the semiconductor substrate 100 .

The material of the semiconductor substrate 100 includes semiconductor materials such as silicon, germanium, silicon germanium, and gallium arsenide, and may be a bulk material or a composite structure such as silicon-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 100 according to the semiconductor devices formed on the semiconductor substrate 100 , so the type of the semiconductor substrate 100 should not limit the protection scope of the present invention. In this embodiment, Su Soushu's semiconductor substrate 100 is a single crystal silicon substrate.

The mask material layer 101 may be formed on the surface of the semiconductor substrate 100 by using a chemical vapor deposition process, and the material of the mask material layer 101 may include: silicon nitride, amorphous carbon or silicon carbide, and the like. In this embodiment, the material of the mask material layer 101 is silicon nitride. The mask material layer 101 is subsequently used to form a mask layer on the surface of the semiconductor substrate 100 .

Referring to FIG. 2 , a mask layer 101 a having an opening 110 is formed on the surface of the semiconductor substrate 100 to expose part of the surface of the semiconductor substrate 100 .

The forming method of the mask layer 101a includes: forming a patterned photoresist layer on the surface of the mask material layer 101 (please refer to FIG. 1 ), the patterned photoresist layer exposes part of the mask material layer 101 using the patterned photoresist layer as a mask, etch the mask material layer 101 to the surface of the semiconductor substrate 101 to form a mask layer 101a with an opening 110, and the opening 110 exposes a part of the semiconductor the surface of the substrate 100.

The position and size of the opening 110 define the position and size of the subsequently formed fins.

Referring to FIG. 3 , the semiconductor substrate 100 is etched along the opening 110 to form a first groove 102 in the semiconductor substrate 100 .

The semiconductor substrate 100 may be etched using a dry etching process, and the dry etching process may be a plasma etching process, a reactive ion etching process, or the like. In this embodiment, the semiconductor substrate 100 is etched using a reactive ion etching process. Specifically, the reactive ion etching process uses a mixed gas of HBr and _Cl2 as an etching gas, and _O2 as a buffer gas , wherein the flow rate of HBr is 50sccm～1000sccm, the flow rate of Cl2 is 50sccm～1000sccm, the flow rate of _O2 is _5sccm ～20sccm, the pressure is 5mTorr～50mTorr, the power is 400W～750W, the gas flow rate of _O2 is 5sccm～20sccm, The temperature is 40°C-80°C, and the bias voltage is 100V-250V.

In this embodiment, since the exchange rate of the etching gas at the top of the first groove 102 is faster and the etching rate is higher, the first groove 102 with inclined sidewalls is finally formed.

Referring to FIG. 4 , an isolation layer 103 is formed inside the first groove 102 (please refer to FIG. 3 ) and the opening 110 (please refer to FIG. 3 ), and the surface of the isolation layer 103 is flush with the surface of the mask layer 101a.

The method for forming the isolation layer 103 includes: forming an isolation material layer that fills the first groove 102 and the opening 110 and covers the mask layer 101a; using the mask layer 101a as a stop layer, Layers are planarized to form an isolation layer 103 flush with the surface of the mask layer 101a.

In this embodiment, the material of the isolation material layer is silicon oxide, and in other embodiments of the present invention, the material of the isolation layer may also be an insulating dielectric material such as silicon oxynitride. The isolation material layer can be formed by chemical vapor deposition process, high density plasma deposition process or high aspect ratio deposition process. In other embodiments of the present invention, before forming the isolation layer 103 , a pad oxide layer may be formed on the inner wall surface of the first groove 102 to improve the quality of the formed isolation layer 103 .

Referring to FIG. 5 , the mask layer 101 a (please refer to FIG. 4 ) is removed to form a second groove 104 .

In this embodiment, the mask layer 101a is removed by a wet etching process. In this embodiment, the material of the mask layer 101a is silicon nitride, and a phosphoric acid solution is used as an etching solution to remove the mask layer 101a. In other embodiments of the present invention, a dry etching process with higher etching selectivity to the mask layer 101a may also be used.

After the mask layer 101 a is removed, a second groove 104 is formed between adjacent isolation layers 103 , and the second groove 104 exposes part of the surface of the semiconductor substrate 100 .

Referring to FIG. 6 , a first SiGe layer 105 is formed in the second groove 104 , and the surface of the first SiGe layer 105 is lower than the surface of the isolation layer 103 .

The first silicon germanium layer 105 is formed by a selective epitaxial process, and the first silicon germanium layer 105 grows upward on the surface of the semiconductor substrate 100 at the bottom of the second groove 104, because the first silicon germanium layer 105 has diamond type crystal structure, the surface of the formed first silicon germanium layer 105 has sharp corners.

The reaction gases used in the selective epitaxy process include: germanium source gas, silicon source gas, HCl and H ₂ , wherein the germanium source gas is GeH ₄ , and the silicon source gas includes silicon-containing gases such as SiH ₄ or SiH ₂ Cl ₂ , The gas flow rate of germanium source gas, silicon source gas and HCl is 1sccm-1000sccm, the flow rate of _H2 is 0.1slm-50slm, the temperature of the selective epitaxy process is 300°C-700°C, and the pressure is 1Torr-100Torr.

The first SiGe layer 105 is a part of the finally formed fin, and the sidewall is covered by the isolation layer 103. The height of the first SiGe layer 105 is 1/3˜1/3 of the depth of the second groove 104. 2. For example, after etching back the isolation layer 103 subsequently, the first SiGe layer 105 can still be covered by the isolation layer 103 after etching back. In this embodiment, the height of the first silicon germanium layer 105 is 1/2 of the depth of the second groove 104 . In other embodiments of the present invention, the height of the first silicon germanium layer 105 can be adjusted according to the final height of the fin to be formed.

The germanium concentration in the first silicon germanium layer 105 ranges from 15% to 45%, and the germanium concentration in the first silicon germanium layer 105 can be adjusted by adjusting the flow rates of germanium source gas and silicon source gas during the selective epitaxy process. .

Referring to FIG. 7 , an amorphous SiGe layer 106 filling the second groove 104 (please refer to FIG. 6 ) and covering the isolation layer 103 is formed on the surface of the first SiGe layer 105 .

The amorphous silicon germanium layer is formed by chemical vapor deposition process. The silicon source gas used in the chemical vapor deposition process is silicon-containing gas such as SiH ₄ or SiH ₂ Cl ₂ , the germanium source gas is GeH ₄ , the temperature is 400°C-600°C, and the pressure is 5 Torr-100 Torr.

In the amorphous silicon germanium layer 106, the concentration of germanium is 25-35%.

Please refer to FIG. 8 , a solid phase epitaxial growth process is used to transform part of the amorphous silicon germanium layer 106 on the surface of the first silicon germanium layer 105 into a third silicon germanium layer 107, and the surface of the third silicon germanium layer 107 is higher than the isolation layer. 103 surfaces.

The solid phase epitaxial growth process adopts annealing treatment, and the annealing temperature is lower than the melting point of the amorphous silicon germanium layer 106, so that the germanium atoms and silicon atoms in the amorphous silicon germanium layer 106 obtain enough energy to migrate. Since part of the amorphous silicon-germanium layer 106 is located on the surface of the first silicon-germanium layer 105, and the silicon-germanium atoms on the surface of the first silicon-germanium layer 105 are arranged in a lattice structure, so the parts directly in contact with the first silicon-germanium layer 105 Atoms in part of the amorphous silicon germanium layer 106 grow regularly on the surface of the first silicon germanium layer 105 along the lattice structure of the first silicon germanium layer 105 to form a third germanium layer located on the surface of the first silicon germanium layer 105 Silicon layer 107 . The annealing temperature may be close to 1/2 of the melting point of the amorphous silicon germanium layer 106 , for example, 600° C. to 800° C. In this embodiment, the growth temperature used in the solid phase epitaxial growth process is 700° C.

The concentration of germanium in the third silicon germanium layer 107 is determined by the concentration of germanium in the amorphous silicon germanium layer 106 , and the concentration of germanium in the third silicon germanium layer 107 is different from that in the first silicon germanium layer 105 . In this embodiment, the germanium concentration in the third silicon germanium layer 107 is 25-35%.

During the solid phase epitaxial growth process, since the germanium concentrations of the first silicon germanium layer 105 and the amorphous silicon germanium layer 106 are different, on the interface between the first silicon germanium layer 105 and the amorphous silicon layer 106, germanium atoms will appear. Due to the diffusion phenomenon, the concentration of germanium on the interface between the formed first silicon germanium layer 105 and the third silicon germanium layer 107 is between that of the first silicon germanium layer 105 and the third silicon germanium layer 107 . Moreover, during the solid phase epitaxial growth process, the atoms located in the amorphous silicon germanium layer 106 will first fill the lattice defect positions on the surface of the first silicon germanium layer 105, so that the sharp corners at the top of the first silicon germanium layer 105 disappear, forming a flat surface. The interface has fewer defects, which can improve the carrier mobility in the first silicon germanium layer 106 and the third silicon germanium layer 107 . However, if the third silicon germanium layer is formed directly on the surface of the first silicon germanium layer 105 by epitaxial process, the surface of the first silicon germanium layer 105 is still uneven, resulting in the interface between the first silicon germanium layer 105 and the third silicon germanium layer There are many defects.

Referring to FIG. 9 , the amorphous silicon germanium layer 106 (please refer to FIG. 8 ) and the third silicon germanium layer 107 (please refer to FIG. 8 ) are planarized by using the isolation layer 103 as a stop layer.

Using a chemical polishing process, the amorphous silicon germanium layer 103 and the third silicon germanium layer 107 are planarized, and the remaining amorphous silicon germanium layer 106 and part of the third silicon germanium layer 107 higher than the surface of the isolation layer 103 are removed, Make the surface of the remaining third SiGe layer 107 a flat and flush with the surface of the isolation layer 103 .

Referring to FIG. 10, the isolation layer 103 is etched back so that the surface of the isolation layer 103 is lower than the surface of the third SiGe layer 107a.

The isolation layer 103 may be etched back by using a dry or wet etching process to reduce the height of the isolation layer 103 and expose the sidewall of the third silicon germanium layer 107a.

In this embodiment, the surface of the isolation layer 103 after etching back is flush with the surface of the first SiGe layer 105 , so that the sidewall of the third SiGe layer 107 a is completely exposed. In other embodiments of the present invention, the surface of the isolation layer 103 may be higher or lower than the surface of the first silicon germanium layer 105 .

Subsequently, a gate structure may be formed across the third silicon germanium layer 107a, and then source and drain electrodes may be formed in the third silicon germanium layer 107a on both sides of the gate structure, thereby forming a fin field effect transistor.

In this embodiment, the third SiGe layer 107 a and the first SiGe layer 105 are part of the fin, and both have different germanium concentrations. By adjusting the concentration of germanium in the first silicon germanium layer 105 and the third silicon germanium layer 107a, the fins can meet the requirements of transistors with different performances, and further improve the performance of fin field effect transistors formed on this basis. For example, when the germanium concentration of the third silicon germanium layer 107a is greater than the germanium concentration of the first silicon germanium layer 105, it is suitable to form a P-type fin field effect transistor on this basis, and further improve the performance of the P-type fin field effect transistor; When the germanium concentration of the third silicon germanium layer 107 a is lower than that of the first silicon germanium layer 105 , it is suitable to form an N-type fin field effect transistor on this basis, and further improve the performance of the N-type fin field effect transistor.

An embodiment of the present invention also provides a semiconductor structure formed by the above method.

Please refer to FIG. 10, the semiconductor structure includes: a semiconductor substrate 100; a first groove located in the semiconductor substrate 100; an isolation layer 103 located in the first groove, and the surface of the isolation layer 103 is higher than the semiconductor substrate On the surface of the bottom 100, there is a first silicon germanium layer 105 located on the surface of the semiconductor substrate 100 between adjacent isolation layers 103; a third silicon germanium layer 107a located on the surface of the first silicon germanium layer 105, the third silicon germanium layer 107a The surface is higher than the surface of the isolation layer 103 .

In this embodiment, the surface of the isolation layer 103 is flush with the surface of the first SiGe layer 105, so that the sidewall of the third SiGe layer 107a is completely exposed. In other embodiments of the present invention, the surface of the isolation layer 103 may be higher or lower than the surface of the first silicon germanium layer 105 . The material of the isolation layer 103 is silicon oxide.

The germanium concentration of the third silicon germanium layer 107 a is different from that of the first silicon germanium layer 105 . In this embodiment, the germanium concentration of the third silicon germanium layer 107a is 25-35%, and the germanium concentration of the first silicon germanium layer 105 is 15-45%. By adjusting the concentration of germanium in the first silicon germanium layer 105 and the third silicon germanium layer 107a, the fins can meet the requirements of transistors with different performances, and further improve the performance of fin field effect transistors formed on this basis.

11 to 22 are schematic diagrams of the formation process of the semiconductor structure according to another embodiment of the present invention.

Please refer to FIG. 11 , a semiconductor substrate 200 is provided, and the semiconductor substrate 200 includes a first region I and a second region II; a first mask layer 201 having an opening 210 is formed on the surface of the semiconductor substrate 200 to expose the semiconductor Partial surfaces of the first region I and the second region II of the substrate 100 .

The first region I and the second region II are used to form different transistors.

The method for forming the first mask layer 201 is the same as that of the previous embodiment, and will not be repeated here.

Referring to FIG. 12 , the semiconductor substrate 200 is etched along the opening 210 to form a first groove 202 in the first region I and the second region II of the semiconductor substrate 200 .

The semiconductor substrate 200 may be etched using a dry etching process, and the dry etching process may be a plasma etching process, a reactive ion etching process, or the like. In this embodiment, the method for forming the first groove 202 is the same as that of the previous embodiment, and will not be repeated here.

Referring to FIG. 13 , an isolation layer 203 is formed inside the first groove 202 (please refer to FIG. 12 ) and the opening 210 (please refer to FIG. 12 ), and the surface of the isolation layer 203 is flush with the surface of the first mask layer 201 .

The method for forming the isolation layer 203 includes: forming an isolation material layer that fills the first groove 202 and the opening 210 and covers the first mask layer 201; using the first mask layer 201 as a stop layer, The isolation material layer is planarized to form an isolation layer 203 flush with the surface of the first mask layer 201 .

The material of the isolation layer 203 is silicon oxide, and in other embodiments of the present invention, the material of the isolation layer may also be an insulating dielectric material such as silicon oxynitride.

Referring to FIG. 14 , the first mask layer 201 is removed (please refer to FIG. 13 ), a second groove 204 is formed in the first region I, and a third groove 205 is formed in the second region II.

In this embodiment, the first mask layer 201 is removed by using a wet etching process. In this embodiment, the material of the first mask layer 201 is silicon nitride, and a phosphoric acid solution is used as an etching solution to remove the first mask layer 201 . In other embodiments of the present invention, a dry etching process with higher etching selectivity to the first mask layer 201 may also be used.

Referring to FIG. 15 , a second mask layer 301 covering the first region I of the semiconductor substrate 200 is formed.

The method for forming the second mask layer 301 includes: forming a second mask material layer covering the isolation layer 203 and the semiconductor substrate 200; forming a patterned photoresist layer on the surface of the second mask material layer to The patterned photoresist layer is a mask, and the second mask material layer is etched to remove the second mask material layer on the second region II of the semiconductor substrate 200, exposing the isolation of the second region II layer 203 and the semiconductor substrate 200 to form a second mask layer 301 covering the first region I.

The material of the second mask layer 301 is easy to be removed by etching. Moreover, since the silicon germanium layer needs to be formed in the third groove 205 subsequently by adopting an epitaxial process, and the epitaxial process needs to adopt a relatively high temperature, the second mask layer 301 can withstand high temperature. Specifically, the material of the second mask layer 301 may be silicon nitride, amorphous carbon, or silicon carbide.

In this embodiment, the material of the second mask layer 301 is silicon nitride, and the second mask material layer is etched by a wet etching process to form the second mask layer 301. The wet etching process The etching process uses a phosphoric acid solution as the etching solution, which has a high etching selectivity for the second mask material layer and avoids damage to the isolation layer 203 and the semiconductor substrate 200 .

Referring to FIG. 16 , a first SiGe layer 206 is formed in the third groove 205 , and the surface of the first SiGe layer 206 is lower than the surface of the isolation layer 203 .

The first silicon germanium layer 206 is formed by a selective epitaxial process, and the first silicon germanium layer 206 grows upward on the surface of the semiconductor substrate 200 at the bottom of the third groove 205, because the first silicon germanium layer 206 has diamond type crystal structure, the surface of the formed first silicon germanium layer 206 has sharp corners.

The reaction gases used in the selective epitaxy process include: germanium source gas, silicon source gas, HCl and H ₂ , wherein the germanium source gas is GeH ₄ , and the silicon source gas includes silicon-containing gases such as SiH ₄ or SiH ₂ Cl ₂ , The gas flow rate of germanium source gas, silicon source gas and HCl is 1sccm-1000sccm, the flow rate of _H2 is 0.1slm-50slm, the temperature of the selective epitaxy process is 300°C-700°C, and the pressure is 1Torr-100Torr.

Since the first region I of the semiconductor substrate 200 is covered with the second mask layer 301, the first silicon germanium layer 206 can only be formed on the semiconductor substrate at the bottom of the third groove 205 in the second region II. Bottom 200 surface.

The first silicon germanium layer 206 is a part of the finally formed fin, and the sidewall is covered by the isolation layer 203. The height of the first silicon germanium layer 206 is 1/3˜2/3 of the depth of the third groove 205. 3. For example, after etching back the isolation layer 203 subsequently, the first SiGe layer 206 can still be covered by the isolation layer 203 after etching back. In this embodiment, the height of the first silicon germanium layer 206 is 1/2 of the depth of the third groove 205 . In other embodiments of the present invention, the height of the first silicon germanium layer 206 can be adjusted according to the final height of the fin to be formed.

The germanium concentration in the first silicon germanium layer 206 ranges from 35% to 45%, and the germanium concentration in the first silicon germanium layer 206 can be adjusted by adjusting the flow rates of germanium source gas and silicon source gas during the selective epitaxy process.

Referring to FIG. 17 , after removing the second mask layer 301 (please refer to FIG. 16 ), a third mask layer 302 covering the second region II of the semiconductor substrate 200 is formed.

The method for forming the third mask layer 302 includes: forming a third mask material layer covering the isolation layer 203 and the semiconductor substrate 200; forming a patterned photoresist layer on the surface of the third mask material layer to The patterned photoresist layer is a mask, and the third mask material layer is etched to remove the third mask material layer on the first region I of the semiconductor substrate 200, exposing the isolation of the first region I layer 203 and the semiconductor substrate 200 to form a third mask layer 302 covering the second region II.

Same as the material of the second mask layer 301 , the material of the third mask layer 302 also needs to be easy to be etched and removed and capable of high temperature resistance. Specifically, the material of the third mask layer 302 may be silicon nitride or amorphous carbon. In this embodiment, the material of the third mask layer 302 is silicon nitride, and the third mask material layer is etched by a wet etching process to form the third mask layer 302. The wet etching process The etching process uses a phosphoric acid solution as the etching solution, which has a high etching selectivity for the third mask material layer and avoids damage to the isolation layer 203 and the semiconductor substrate 200 .

Referring to FIG. 18 , a second SiGe layer 207 is formed in the second groove 204 , and the surface of the second SiGe layer 207 is lower than the surface of the isolation layer 203 .

The second silicon germanium layer 207 is formed by the same method as that of the first silicon germanium layer 206 , that is, a selective epitaxial process, and the surface of the second silicon germanium layer 207 also has sharp corners.

The reaction gases used in the selective epitaxy process include: germanium source gas, silicon source gas, HCl and H ₂ , wherein the germanium source gas is GeH ₄ , and the silicon source gas includes silicon-containing gases such as SiH ₄ or SiH ₂ Cl ₂ , The gas flow rate of germanium source gas, silicon source gas and HCl is 1sccm-1000sccm, the flow rate of _H2 is 0.1slm-50slm, the temperature of the selective epitaxy process is 300°C-700°C, and the pressure is 1Torr-100Torr.

Since the second region II of the semiconductor substrate 100 is covered with the third mask layer 302, the second silicon germanium layer 207 can only be formed on the semiconductor substrate at the bottom of the second groove 204 in the first region I. Bottom 200 surface.

The concentration of germanium in the second silicon germanium layer 207 can be adjusted by adjusting the flow rates of germanium source gas and silicon source gas in the selective epitaxy process, so that the germanium concentration of the second silicon germanium layer 207 is the same as that of the first silicon germanium layer 206 The concentration of germanium varies. In this embodiment, the germanium concentration of the second silicon germanium layer 207 is lower than the germanium concentration of the first silicon germanium layer 206 . The germanium concentration of the second silicon germanium layer 207 is 15-25%. In other embodiments of the present invention, the germanium concentration of the second silicon germanium layer 207 may also be greater than the germanium concentration of the first silicon germanium layer 206 .

The height of the second silicon germanium layer 207 is 1/3 to 1/2 of the depth of the second groove 204. In this embodiment, the height of the second silicon germanium layer 207 is the same as the height of the first silicon germanium layer 206. Same, it is 1/2 of the depth of the second groove 204 . In other embodiments of the present invention, the height of the second silicon germanium layer 207 can be adjusted according to the final height of the fin to be formed, and can be different from the height of the first silicon germanium layer 206 .

Please refer to FIG. 19, the third mask layer 302 is removed, and an amorphous silicon germanium layer 208 is formed on the surface of the first silicon germanium layer 206 and the second silicon germanium layer 207, and the amorphous silicon germanium layer 208 is filled with the The second groove 204 and the third groove 205 cover the isolation layer 203 .

The amorphous silicon germanium layer 208 is formed by chemical vapor deposition process, and details are not repeated here.

In the amorphous silicon germanium layer 208, the concentration of germanium is 25-35%.

Please refer to FIG. 20 , the solid phase epitaxial growth process is used to transform part of the amorphous silicon germanium layer 208 on the surface of the first silicon germanium layer 206 and the second silicon germanium layer 207 into a third silicon germanium layer 209, and the third silicon germanium layer 209 The surface of layer 209 is higher than the surface of isolation layer 203 .

The concentration of germanium in the third silicon germanium layer 209 is determined by the concentration of germanium in the amorphous silicon germanium layer 208, and the concentration of germanium in the third silicon germanium layer 209 is the same as that of the first silicon germanium layer 206 and the second silicon germanium layer 207. Concentrations of germanium vary. In this embodiment, the germanium concentration in the first silicon germanium layer 206 is higher than the germanium concentration in the third silicon germanium layer 209, and the germanium concentration in the second silicon germanium layer 207 is lower than that in the third silicon germanium layer 209. germanium concentration. Specifically, the germanium concentration in the third silicon germanium layer 209 ranges from 25% to 35%.

The growth temperature of the solid phase epitaxial growth process is 600° C. to 800° C., and the first silicon germanium layer 206 and the third silicon germanium layer 209 have a flat interface, and the second silicon germanium layer 207 and the third silicon germanium layer 207 The silicon layer 209 also has a flat interface with fewer defects.

Referring to FIG. 21 , the amorphous silicon germanium layer 208 and the third silicon germanium layer 209 are planarized by using the isolation layer 203 as a stop layer.

The amorphous germanium silicon layer 208 and the third germanium silicon layer 209 on the first region I and the second region II are planarized by using a chemical polishing process, and the remaining amorphous germanium silicon layer 208 and the surface higher than the isolation layer 203 are removed part of the third silicon germanium layer 209 , so that the surface of the remaining third silicon germanium layer 209 a is flat and flush with the surface of the isolation layer 203 .

Referring to FIG. 22, the isolation layer 203 is etched back so that the surface of the isolation layer 203 is lower than the surface of the third SiGe layer 209a.

The isolation layer 203 may be etched back by using a dry or wet etching process to reduce the height of the isolation layer 203 and expose the sidewall of the third silicon germanium layer 209a.

In this embodiment, the surface of the isolation layer 203 after etching back is flush with the surfaces of the first SiGe layer 206 and the second SiGe layer 207 , so that the sidewall of the third SiGe layer 209 a is completely exposed. In other embodiments of the present invention, the surface of the isolation layer 203 may be higher or lower than the surface of the first silicon germanium layer 206 and the second silicon germanium layer 207 .

Subsequently, a gate structure can be formed across the third silicon germanium layer 209a, and then source and drain electrodes can be formed in the third silicon germanium layer 209 on both sides of the gate structure, so that the first region I and the second FinFETs are formed on the region II.

In this embodiment, the third silicon germanium layer 209a and the first silicon germanium layer 206 are part of the fin portion on the first region I, and both have different germanium concentrations; the third silicon germanium layer 209a and the second silicon germanium layer 209a The silicon layer 207 acts as a part of the fin on the second region II, both of which also have different germanium concentrations. And, the germanium concentration of the third silicon germanium layer 209a is less than the germanium concentration of the first silicon germanium layer 206; the germanium concentration of the third silicon germanium layer 209a is greater than the germanium concentration of the second silicon germanium layer 207; thus making the first The region I and the second region II are respectively suitable for forming fin field effect transistors of different performances or types. For example, a P-type FinFET is formed on the first region I, and an N-type FinFET is formed on the second region II, so as to effectively improve the performance of different types of FinFETs.

An embodiment of the present invention also provides a semiconductor structure formed by the above method.

Please refer to FIG. 22, the semiconductor structure includes: a semiconductor substrate 200, the semiconductor substrate 200 includes a first region I and a second region II; The first groove; the isolation layer 203 located in the first groove, the surface of the isolation layer 203 is higher than the surface of the semiconductor substrate 200; the first region I surface of the semiconductor substrate 200 between adjacent isolation layers 203 Digermanium silicon layer 207; the first germanium silicon layer 206 on the surface of the second region II of the semiconductor substrate 200 between adjacent isolation layers 203; the first germanium silicon layer 206 and the second germanium silicon layer 207 on the surface The third silicon germanium layer 209 a, the surface of the third silicon germanium layer 209 a is higher than the surface of the isolation layer 203 .

The surface of the isolation layer 203 is flush with the surfaces of the first silicon germanium layer 206 and the second silicon germanium layer 207 , so that the sidewall of the third silicon germanium layer 209 a is completely exposed. In other embodiments of the present invention, the surface of the isolation layer 203 may be higher or lower than the surface of the first silicon germanium layer 206 and the second silicon germanium layer 207 . The material of the isolation layer 203 is silicon oxide.

The third silicon germanium layer 209a and the first silicon germanium layer 206 are part of the fin portion on the first region I, both of which have different concentrations of germanium; the third silicon germanium layer 209a and the second silicon germanium layer 207 are used as the first Parts of the fins on the second region II also have different germanium concentrations. And, the germanium concentration of the third silicon germanium layer 209a is less than the germanium concentration of the first silicon germanium layer 206; the germanium concentration of the third silicon germanium layer 209a is greater than the germanium concentration of the second silicon germanium layer 207; thus making the first The region I and the second region II are respectively suitable for forming fin field effect transistors of different performances or types. For example, the first region I is suitable for forming P-type FinFETs, and the second region II is suitable for forming N-type FinFETs, which can effectively improve the performance of different types of FinFETs.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of forming method of semiconductor structure, it is characterised in that including：

Semiconductor substrate is provided；

The mask layer with opening is formed in half guide bush basal surface, the part surface of Semiconductor substrate is exposed；

Along the opening etch semiconductor substrates, the first groove is formed in Semiconductor substrate；

The separation layer in the first groove and opening is formed, the insulation surface is neat with mask layer surface It is flat；

The mask layer is removed, the second groove is formed；

The first germanium silicon layer is formed in the second groove, the first germanium silicon surface is less than insulation surface；

The amorphous Germanium silicon layer of full second groove of filling and covering separation layer is formed in the first germanium silicon surface；

Using solid-phase epitaxial growth technique, it is changed into the part amorphous germanium silicon layer of the first germanium silicon surface 3rd germanium silicon layer, the 3rd germanium silicon surface is higher than insulation surface；

Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；

The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.

2. the forming method of semiconductor structure according to claim 1, it is characterised in that first germanium Germanium concentration in silicon layer is different from the germanium concentration in the 3rd germanium silicon layer.

3. the forming method of semiconductor structure according to claim 2, it is characterised in that first germanium Range of germanium concentration in silicon layer is 15%~45%, and the range of germanium concentration in the 3rd germanium silicon layer is 25%~35%.

4. the forming method of semiconductor structure according to claim 1, it is characterised in that using selectivity Epitaxy technique forms the first germanium silicon layer.

5. the forming method of semiconductor structure according to claim 1, it is characterised in that first germanium The height of silicon layer is the 1/3~1/2 of the second depth of groove.

6. the forming method of semiconductor structure according to claim 1, it is characterised in that using chemical gas Phase depositing operation forms the amorphous Germanium silicon layer.

7. the forming method of semiconductor structure according to claim 6, it is characterised in that the chemical gas The silicon source gas that phase depositing operation is used is SiH₄Or SiH₂Cl₂, ge source gas is GeH₄, temperature It it is 400 DEG C~600 DEG C, pressure is 5Torr~100Torr.

8. the forming method of semiconductor structure according to claim 1, it is characterised in that outside the solid phase The growth temperature of growth process is 600 DEG C~800 DEG C.

9. the semiconductor structure for being formed using the method described in any claim in claim 1 to 8, its It is characterised by, including：

Semiconductor substrate；

The first groove in Semiconductor substrate；

Separation layer in the first groove, and the insulation surface is higher than semiconductor substrate surface；

First germanium silicon layer of the semiconductor substrate surface between adjacent separation layer；

Positioned at the 3rd germanium silicon layer of the first germanium silicon surface, the 3rd germanium silicon surface is higher than separation layer table Face.

10. a kind of forming method of semiconductor structure, it is characterised in that including：

Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；

The first mask layer with opening is formed in half guide bush basal surface, the first of Semiconductor substrate is exposed Region and the part surface of second area；

Along the opening etch semiconductor substrates, the shape in the first area of Semiconductor substrate and second area Into the first groove；

Form the separation layer in the first groove and opening, the insulation surface and the first mask layer table Face flushes；

The first mask layer is removed, the second groove is formed in first area, the 3rd groove is formed in second area；

Form the second mask layer of covering Semiconductor substrate first area；

The first germanium silicon layer is formed in the 3rd groove, the first germanium silicon surface is less than insulation surface；

After removing the second mask layer, the 3rd mask layer of covering Semiconductor substrate second area is formed；

The second germanium silicon layer is formed in the second groove, the second germanium silicon surface is less than insulation surface；

The 3rd mask layer is removed, amorphous Germanium silicon is formed in the first germanium silicon layer, the second germanium silicon surface Layer, the filling of amorphous Germanium silicon layer full second groove, the 3rd groove, and cover the separation layer；

Using solid-phase epitaxial growth technique, make the first germanium silicon layer, the part amorphous of the second germanium silicon surface Germanium silicon layer is changed into the 3rd germanium silicon layer, and the 3rd germanium silicon surface is higher than insulation surface；

Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；

The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.

The forming method of 11. semiconductor structures according to claim 10, it is characterised in that first germanium Higher than the germanium concentration in the 3rd germanium silicon layer, the germanium concentration in the second germanium silicon layer is less than germanium concentration in silicon layer Germanium concentration in 3rd germanium silicon layer.

The forming method of 12. semiconductor structures according to claim 11, it is characterised in that first germanium Range of germanium concentration in silicon layer is 35~45%, and the range of germanium concentration in the second germanium silicon layer is 15~25%, Range of germanium concentration in 3rd germanium silicon layer is 25~35%.

The forming method of 13. semiconductor structures according to claim 10, it is characterised in that using selectivity Epitaxy technique forms the first germanium silicon layer, the second germanium silicon layer.

The forming method of 14. semiconductor structures according to claim 10, it is characterised in that first germanium The height of silicon layer is the 1/3~1/2 of the 3rd depth of groove；The height of the second germanium silicon layer is the second groove The 1/3~1/2 of depth.

The forming method of 15. semiconductor structures according to claim 10, it is characterised in that using chemical gas Phase depositing operation forms the amorphous Germanium silicon layer.

The forming method of 16. semiconductor structures according to claim 15, it is characterised in that the chemical gas The silicon source gas that phase depositing operation is used is SiH₄Or SiH₂Cl₂, ge source gas is GeH₄, temperature It it is 400 DEG C~600 DEG C, pressure is 5Torr~100Torr.

The forming method of 17. semiconductor structures according to claim 10, it is characterised in that outside the solid phase The growth temperature of growth process is 600 DEG C~800 DEG C.

The forming method of 18. semiconductor structures according to claim 10, it is characterised in that described second covers The forming method of film layer includes：Form the second mask layer of covering separation layer and Semiconductor substrate； Graphical photoresist layer is formed in the second mask material layer surface；With the graphical photoresist layer Be mask, etch second mask layer, removal on Semiconductor substrate second area the Two mask layers, expose the separation layer and Semiconductor substrate of second area, form the firstth area of covering Second mask layer in domain.

The forming method of 19. semiconductor structures according to claim 10, it is characterised in that the described 3rd covers The forming method of film layer includes：Form the 3rd mask layer of covering separation layer and Semiconductor substrate； Graphical photoresist layer is formed in the 3rd mask material layer surface；With the graphical photoresist layer Be mask, etch the 3rd mask layer, removal on Semiconductor substrate first area the Three mask layers, expose the separation layer and Semiconductor substrate of first area, form the secondth area of covering 3rd mask layer in domain.

20. semiconductor structures formed using the method described in any claim in claim 10 to 19, It is characterised in that it includes：

Semiconductor substrate, the Semiconductor substrate includes first area and second area；

The first groove in the first area and second area of Semiconductor substrate；

Separation layer in the first groove, the insulation surface is higher than semiconductor substrate surface；

The second germanium silicon layer on the Semiconductor substrate first area surface between adjacent separation layer；

The first germanium silicon layer on the Semiconductor substrate second area surface between adjacent separation layer；

Positioned at the first germanium silicon layer and the 3rd germanium silicon layer of the second germanium silicon surface, the 3rd germanium silicon layer Surface is higher than insulation surface.