CN106856191A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN106856191A CN106856191A CN201510906938.4A CN201510906938A CN106856191A CN 106856191 A CN106856191 A CN 106856191A CN 201510906938 A CN201510906938 A CN 201510906938A CN 106856191 A CN106856191 A CN 106856191A
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- germanium silicon
- germanium
- silicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 238000000034 method Methods 0.000 title claims abstract description 113
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 352
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 238000000926 separation method Methods 0.000 claims abstract description 98
- 238000009413 insulation Methods 0.000 claims abstract description 26
- 239000007790 solid phase Substances 0.000 claims abstract description 18
- 238000011049 filling Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 554
- 229910052732 germanium Inorganic materials 0.000 claims description 104
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 38
- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 8
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 5
- 239000012071 phase Substances 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 3
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 claims 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 89
- 230000005669 field effect Effects 0.000 description 27
- 238000005530 etching Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000000348 solid-phase epitaxy Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H01L21/823431—
-
- H01L27/0886—
-
- H01L29/165—
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, the forming method of the semiconductor structure includes：Semiconductor substrate is provided；The mask layer with opening is formed in half guide bush basal surface；Along the opening etch semiconductor substrates, the first groove is formed；The separation layer in the first groove and opening is formed, the insulation surface is flushed with mask layer surface；Removal mask layer, forms the second groove；First germanium silicon layer of the surface less than insulation surface is formed in the second groove；The amorphous Germanium silicon layer of full second groove of filling and covering separation layer is formed in the first germanium silicon surface；Using solid-phase epitaxial growth technique, the part amorphous germanium silicon layer of the first germanium silicon surface is set to be changed into the 3rd germanium silicon layer；Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.The above method can improve the performance of semiconductor structure.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With continuing to develop for semiconductor process technique, process node is gradually reduced, rear grid (gate-last)
Technique is widely applied to obtain preferable threshold voltage, improves device performance.But work as device
Characteristic size (CD, Critical Dimension) when further declining, even if using rear grid technique,
The structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, fin field effect
Transistor (Fin FET) has obtained extensive concern as the replacement of conventional device.The fin field effect
Transistor generally includes fin, and the grid structure across fin and the fin positioned at grid structure both sides
Interior source-drain electrode.
In order to further improve the performance of semiconductor devices, semi-conducting material germanium is also widely used.
Compared with silicon, germanium has electronics and hole mobility higher, so that using on the semiconductor device, it is special
It is not the performance that semiconductor devices can be effectively improved as the channel region material of transistor.Using containing
Germanium semiconductor material, such as germanium silicon, forming fin formula field effect transistor can effectively improve the property of transistor
Energy.
The fin of fin formula field effect transistor, fin various location are formed with germanium silicon material in the prior art
Germanium concentration it is all identical, it is impossible to meet the demand of different crystal pipe, the performance of fin formula field effect transistor is also
Need further raising.
The content of the invention
The problem that the present invention is solved is to provide a kind of semiconductor structure and forming method thereof, and raising is described partly to be led
The performance of body structure, to improve the fin formula field effect transistor formed on the basis of the semiconductor structure
Performance.
To solve the above problems, technical scheme provides a kind of forming method of semiconductor structure,
Including：Semiconductor substrate is provided；The mask layer with opening is formed in half guide bush basal surface, half is exposed
The part surface of conductor substrate；Along the opening etch semiconductor substrates, is formed in Semiconductor substrate
One groove；Form the separation layer in the first groove and opening, the insulation surface and mask layer table
Face flushes；The mask layer is removed, the second groove is formed；The first germanium silicon layer is formed in the second groove,
The first germanium silicon surface is less than insulation surface；It is recessed filling full second to be formed in the first germanium silicon surface
The amorphous Germanium silicon layer of groove and covering separation layer；Using solid-phase epitaxial growth technique, make the first germanium silicon layer table
The part amorphous germanium silicon layer in face is changed into the 3rd germanium silicon layer, and the 3rd germanium silicon surface is higher than separation layer
Surface；Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；Return
The separation layer is etched, insulation surface is less than the 3rd germanium silicon surface.
Optionally, the germanium concentration in the first germanium silicon layer is different from the germanium concentration in the 3rd germanium silicon layer.
Optionally, the range of germanium concentration in the first germanium silicon layer is 15%~45%, in the 3rd germanium silicon layer
Range of germanium concentration is 25%~35%.
Optionally, the first germanium silicon layer is formed using selective epitaxial process.
Optionally, the height of the first germanium silicon layer is the 1/3~1/2 of the second depth of groove.
Optionally, the amorphous Germanium silicon layer is formed using chemical vapor deposition method.
Optionally, the silicon source gas that the chemical vapor deposition method is used is SiH4Or SiH2Cl2, germanium
Source gas is GeH4, temperature is 400 DEG C~600 DEG C, and pressure is 5Torr~100Torr.
Optionally, the growth temperature of the solid-phase epitaxial growth technique is 600 DEG C~800 DEG C.
Technical scheme also provides the semiconductor structure that a kind of use above method is formed, including：
Semiconductor substrate；The first groove in Semiconductor substrate；Separation layer in the first groove, and
The insulation surface is higher than semiconductor substrate surface；Semiconductor substrate table between adjacent separation layer
The first germanium silicon layer in face；Positioned at the 3rd germanium silicon layer of the first germanium silicon surface, the 3rd germanium silicon surface
Higher than insulation surface.
Technical scheme also provides the forming method of another semiconductor structure, including：There is provided half
Conductor substrate, the Semiconductor substrate includes first area and second area；Formed in half guide bush basal surface
The first mask layer with opening, exposes the first area of Semiconductor substrate and the part table of second area
Face；Along the opening etch semiconductor substrates, the shape in the first area of Semiconductor substrate and second area
Into the first groove；Form the separation layer in the first groove and opening, the insulation surface and first
Mask layer surface is flushed；The first mask layer is removed, the second groove is formed in first area, in second area
Form the 3rd groove；Form the second mask layer of covering Semiconductor substrate first area；In the 3rd groove
The first germanium silicon layer is formed, the first germanium silicon surface is less than insulation surface；After removing the second mask layer, shape
Into the 3rd mask layer of covering Semiconductor substrate second area；The second germanium silicon layer is formed in the second groove,
Second germanium silicon surface is less than insulation surface；The 3rd mask layer is removed, in the first germanium silicon layer,
Two germanium silicon surfaces formation amorphous Germanium silicon layer, full second groove of amorphous Germanium silicon layer filling,
3rd groove, and cover the separation layer；Using solid-phase epitaxial growth technique, make the first germanium silicon layer,
The part amorphous germanium silicon layer of two germanium silicon surfaces is changed into the 3rd germanium silicon layer, the 3rd germanium silicon surface
Higher than insulation surface；Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are carried out
Planarization；The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.
Optionally, the germanium concentration in the first germanium silicon layer is higher than the germanium concentration in the 3rd germanium silicon layer, second
Germanium concentration in germanium silicon layer is less than the germanium concentration in the 3rd germanium silicon layer.
Optionally, the range of germanium concentration in the first germanium silicon layer is 35~45%, the germanium in the second germanium silicon layer
Concentration range is 15~25%, and the range of germanium concentration in the 3rd germanium silicon layer is 25~35%.
Optionally, the first germanium silicon layer, the second germanium silicon layer are formed using selective epitaxial process.
Optionally, the height of the first germanium silicon layer is the 1/3~1/2 of the 3rd depth of groove；Second germanium
The height of silicon layer is the 1/3~1/2 of the second depth of groove.
Optionally, the amorphous Germanium silicon layer is formed using chemical vapor deposition method.
Optionally, the silicon source gas that the chemical vapor deposition method is used is SiH4Or SiH2Cl2, germanium
Source gas is GeH4, temperature is 400 DEG C~600 DEG C, and pressure is 5Torr~100Torr.
Optionally, the growth temperature of the solid-phase epitaxial growth technique is 600 DEG C~800 DEG C.
Optionally, the forming method of second mask layer includes：Form covering separation layer and semiconductor
Second mask layer of substrate；Graphical photoresist layer is formed in the second mask material layer surface；
With the graphical photoresist layer as mask, second mask layer is etched, removal is located at semiconductor
The second mask layer on substrate second area, exposes the separation layer and Semiconductor substrate of second area,
Form the second mask layer of covering first area.
Optionally, the forming method of the 3rd mask layer includes：Form covering separation layer and semiconductor
3rd mask layer of substrate；Graphical photoresist layer is formed in the 3rd mask material layer surface；
With the graphical photoresist layer as mask, the 3rd mask layer is etched, removal is located at semiconductor
The 3rd mask layer on substrate first area, exposes the separation layer and Semiconductor substrate of first area,
Form the 3rd mask layer of covering second area.
Technical scheme also provides another semiconductor structure formed using the above method, including：
Semiconductor substrate, the Semiconductor substrate includes first area and second area；Positioned at Semiconductor substrate
The first groove in first area and second area；Separation layer in the first groove, the separation layer
Surface is higher than semiconductor substrate surface；Semiconductor substrate first area surface between adjacent separation layer
The second germanium silicon layer；The first germanium silicon on the Semiconductor substrate second area surface between adjacent separation layer
Layer；Positioned at the first germanium silicon layer and the 3rd germanium silicon layer of the second germanium silicon surface, the 3rd germanium silicon layer
Surface is higher than insulation surface.
Compared with prior art, technical scheme has advantages below：
In technical scheme, the first germanium silicon layer is formed on a semiconductor substrate, then described
First germanium silicon surface is formed after amorphous Germanium silicon layer, then makes to be located at the first germanium by process of solid phase epitaxy
The part amorphous germanium silicon layer of silicon surface is changed into the 3rd germanium silicon layer, the first germanium silicon layer and the 3rd germanium
Silicon layer as fin a part.During solid-phase epitaxial growth, the atom in amorphous Germanium silicon layer
The lattice defect position of the first germanium silicon surface can be filled up first so that the wedge angle at the top of the first germanium silicon layer disappears
Lose, form smooth interface, the defect on interface is less, can improve the first germanium silicon layer and the 3rd germanium silicon
Carrier mobility in layer, and then improve the performance of the semiconductor structure.
Further, the first germanium silicon layer is different with the germanium concentration of the 3rd germanium silicon layer, described by adjustment
Germanium concentration in first germanium silicon layer and the 3rd germanium silicon layer, can cause that fin meets different performance transistor
Demand, further improves the performance of the fin formula field effect transistor for being formed on this basis.
In technical scheme, a kind of forming method of semiconductor structure is also provided, in semiconductor lining
The second germanium silicon layer is formed on the first area at bottom, the first germanium silicon layer is formed on second area, then again in institute
State the first germanium silicon layer, the second germanium silicon surface and form amorphous Germanium silicon layer, by process of solid phase epitaxy, make
The part amorphous germanium silicon layer for obtaining the first germanium silicon layer and the second germanium silicon surface is changed into the 3rd germanium silicon layer.Institute
The part of the first germanium silicon layer and the 3rd germanium silicon layer on first area as the fin on first area is stated,
The 3rd germanium silicon layer on the second germanium silicon layer and its surface as the fin on second area a part.Outside solid phase
During epitaxial growth, the atom in amorphous Germanium silicon layer can fill up the first germanium silicon layer, the second germanium first
The lattice defect position of silicon surface so that the wedge angle at the top of the first germanium silicon layer, the second germanium silicon layer disappears,
Form smooth interface, the defect on interface is less, can improve the first germanium silicon layer, the second germanium silicon layer and
Carrier mobility in 3rd germanium silicon layer, and then improve the performance of the semiconductor structure.
Further, the 3rd germanium silicon layer and the first germanium silicon layer as the fin on first area a part,
Both have different germanium concentrations；3rd germanium silicon layer and the second germanium silicon layer are used as the fin on second area
A part, both also have different germanium concentrations.Also, the germanium concentration of the 3rd germanium silicon layer is less than the
The germanium concentration of one germanium silicon layer；Germanium concentration of the germanium concentration of the 3rd germanium silicon layer more than the second germanium silicon layer；So that
Obtain the first area and second area suitably forms the fin field effect crystal of different performance or type respectively
Pipe, can improve the performance of different type fin formula field effect transistor.
Brief description of the drawings
Fig. 1 to Figure 10 is the structural representation of the forming process of the semiconductor structure of one embodiment of the present of invention
Figure；
Figure 11 to Figure 22 is that the structure of the forming process of the semiconductor structure of one embodiment of the present of invention is shown
It is intended to.
Specific embodiment
As described in the background art, in fin of the prior art using germanium silicon material formation, germanium concentration is not
The concentration gone out with position is consistent, it is impossible to meet the demand of different crystal pipe, so as to can influence on this basis
The performance of the fin formula field effect transistor of formation.
In other embodiment of the invention, forming fin includes lower part and upper part, its middle and upper part point and
Germanium concentration in the fin of lower part is differed, to meet the demand of different crystal pipe.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 1 to Figure 10 is the schematic diagram of the forming process of the semiconductor structure of the first embodiment of the present invention.
Refer to Fig. 1, there is provided Semiconductor substrate 100, mask is formed on the surface of the Semiconductor substrate 100
Material layer 101.
The material of the Semiconductor substrate 100 semi-conducting material such as including silicon, germanium, SiGe, GaAs,
Can be that body material can also be composite construction such as silicon-on-insulator.Those skilled in the art can basis
The semiconductor devices formed in Semiconductor substrate 100 selects the type of the Semiconductor substrate 100, therefore
The type of the Semiconductor substrate 100 should not be limited the scope of the invention.In the present embodiment, Soviet Union is searched
Book Semiconductor substrate 100 is monocrystalline substrate.
The mask material can be formed on the surface of the Semiconductor substrate 100 using chemical vapor deposition method
The bed of material 101, the material of the mask layer 101 can include：Silicon nitride, amorphous carbon or carborundum
Deng.In the present embodiment, the material of the mask layer 101 is silicon nitride.The mask layer 101
It is subsequently used for forming the mask layer positioned at the surface of Semiconductor substrate 100.
Fig. 2 is refer to, the mask layer 101a with opening 110, exposure are formed on the surface of half conductive substrate 100
Go out the part surface of Semiconductor substrate 100.
The forming method of the mask layer 101a includes：The mask layer 101 (refer to Fig. 1)
Surface forms graphical photoresist layer, and the graphical photoresist layer exposes part mask layer 101
Surface；With the graphical photoresist layer as mask, the mask layer 101 to semiconductor is etched
The surface of substrate 101, forms the mask layer 101a with opening 110, and the opening 110 exposes part
The surface of Semiconductor substrate 100.
The positions and dimensions of the opening 110, define the positions and dimensions of the fin being subsequently formed.
Fig. 3 is refer to, along 110 etch semiconductor substrates 100 of the opening, in Semiconductor substrate 100
Form the first groove 102.
The Semiconductor substrate 100 can be etched using dry etch process, the dry etch process can be with
It is plasma etch process, reactive ion etching process etc..In the present embodiment, carved using reactive ion
Etching technique is performed etching to the Semiconductor substrate 100, specifically, the reactive ion etching process is adopted
With HBr and Cl2Mixed gas as etching gas, O2As buffer gas, the wherein flow of HBr
It is 50sccm~1000sccm, Cl2Flow be 50sccm~1000sccm, O2Flow be
5sccm~20sccm, pressure is 5mTorr~50mTorr, and power is 400W~750W, O2Gas stream
It is 5sccm~20sccm to measure, and temperature is 40 DEG C~80 DEG C, and bias voltage is 100V~250V.
In the present embodiment, because the etching gas exchange rate at the top of the first groove 102 is very fast, etching
Speed is larger, so ultimately forming the first groove 102 of sidewall slope.
Fig. 4 is refer to, is formed and (be refer to positioned at the first groove 102 (refer to Fig. 3) and opening 110
Separation layer 103 in Fig. 3), the surface of the separation layer 103 flushes with mask layer 101a surfaces.
The forming method of the separation layer 103 includes：Form full first groove 102 of filling, opening
110 and mask film covering layer 101a spacer material layer；Using the mask layer 101a as stop-layer, to institute
State spacer material layer to be planarized, the separation layer 103 that formation is flushed with the mask layer 101a surfaces.
In the present embodiment, the material of the spacer material layer is silica, in other embodiment of the invention
In, the material of the separation layer can also be the insulating dielectric materials such as silicon oxynitride.Can be using chemical gas
Phase depositing operation, high-density plasma deposition process or high-aspect-ratio depositing operation form the isolation material
The bed of material.In other embodiments of the invention, before the separation layer 103 is formed, can be described
The inner wall surface of the first groove 102 forms pad oxide, improves the quality of the separation layer 103 for being formed.
Fig. 5 is refer to, the mask layer 101a (refer to Fig. 4) is removed, the second groove 104 is formed.
In the present embodiment, the mask layer 101a is removed using wet-etching technology.In the present embodiment, institute
The material of mask layer 101a is stated for silicon nitride, the mask layer is removed as etching solution using phosphoric acid solution
101a.In other embodiments of the invention, can also use has etching choosing higher to mask layer 101a
The dry etch process of selecting property.
Remove after the mask layer 101a, the second groove 104 formed between adjacent separation layer 103,
Second groove 104 exposes the surface of part semiconductor substrate 100.
Fig. 6 is refer to, the first germanium silicon layer 105, the first germanium silicon layer 105 are formed in the second groove 104
Surface is less than the surface of separation layer 103.
The first germanium silicon layer 105 is formed using selective epitaxial process, the first germanium silicon layer 105 is
The surface of Semiconductor substrate 100 of the bottom of two groove 104 grows up, due to the first germanium silicon layer 105
With diamond lattice structure, the surface of the first germanium silicon layer 105 of formation has wedge angle.
The reacting gas that the selective epitaxial process is used includes：Ge source gas, silicon source gas, HCl
And H2, wherein, ge source gas is GeH4, silicon source gas include SiH4Or SiH2Cl2Deng silicon-containing gas,
The gas flow of ge source gas, silicon source gas and HCl is 1sccm~1000sccm, H2Flow be
0.1slm~50slm, the temperature of the selective epitaxial process is 300 DEG C~700 DEG C, and pressure is 1Torr
~100Torr.
The first germanium silicon layer 105 as the fin for ultimately forming a part, side wall is isolated layer 103
Covered, the height of the first germanium silicon layer 105 is the 1/3~1/2 of the depth of the second groove 104, for example, make
Obtain after being subsequently etched back to separation layer 103, the first germanium silicon layer 105 can be still etched back to
Separation layer 103 afterwards is covered.In the present embodiment, the height of the first germanium silicon layer 105 is the second groove
The 1/2 of 104 depth.In other embodiments of the invention, the height of the first germanium silicon layer 105 can be with
It is adjusted according to final fin height to be formed.
Range of germanium concentration in the first germanium silicon layer 105 is 15%~45%, by adjusting selective epitaxial
During the flow of ge source gas and silicon source gas can adjust germanium concentration in the first germanium silicon layer 105.
Fig. 7 is refer to, forming full second groove 104 of filling on the surface of the first germanium silicon layer 105 (refer to figure
6) and covering separation layer 103 amorphous Germanium silicon layer 106.
The amorphous Germanium silicon layer is formed using chemical vapor deposition method.The chemical vapor deposition method
The silicon source gas for using is SiH4Or SiH2Cl2Deng silicon-containing gas, ge source gas is GeH4, temperature is 400 DEG C
~600 DEG C, pressure is 5Torr~100Torr.
In the amorphous Germanium silicon layer 106, germanium concentration is 25~35%.
Fig. 8 is refer to, using solid-phase epitaxial growth technique, makes the part on the surface of the first germanium silicon layer 105 without fixed
Shape germanium silicon layer 106 is changed into the 3rd germanium silicon layer 107, and the surface of the 3rd germanium silicon layer 107 is higher than separation layer
103 surfaces.
The solid-phase epitaxial growth technique is less than the amorphous Germanium silicon layer using annealing, annealing temperature
106 fusing point so that germanium atom and silicon atom in the amorphous Germanium silicon layer 106 obtain enough energy
Can be migrated.Because part amorphous germanium silicon layer 106 is positioned at the surface of the first germanium silicon layer 105, and institute
The germanium silicon atom for stating the surface of the first germanium silicon layer 105 is arranged according to lattice structure, so, with the first germanium silicon layer
Atom in the part amorphous germanium silicon layer 106 of 105 directly contacts, on the surface of the first germanium silicon layer 105
Grown along the lattice structure regularization of the first germanium silicon layer 105, formed and be located at the surface of the first germanium silicon layer 105
The 3rd germanium silicon layer 107.The annealing temperature can close to the 1/2 of the fusing point of amorphous Germanium silicon layer 106,
Such as 600 DEG C~800 DEG C, in the present embodiment, the growth temperature that the solid-phase epitaxial growth technique is used for
700℃。
Germanium concentration in the 3rd germanium silicon layer 107 determines by the germanium concentration of amorphous Germanium silicon layer 106, institute
The germanium concentration stated in the 3rd germanium silicon layer 107 is different from the germanium concentration in the first germanium silicon layer 105.The present embodiment
In, the germanium concentration in the 3rd germanium silicon layer 107 is 25~35%.
During solid-phase epitaxial growth is carried out, due to the first germanium silicon layer 105 and amorphous Germanium silicon layer 106
Germanium concentration it is different, on the first interface of the germanium silicon layer 105 with amorphous si-layer 106, it may appear that germanium is former
The diffusion phenomena of son so that the first germanium silicon layer 105 of formation is dense with the germanium on the interface of the 3rd germanium silicon layer 107
Degree is located between the first germanium silicon layer 105 and the germanium concentration of the 3rd germanium silicon layer 107.Also, solid phase epitaxial is given birth to
In growth process, the atom in amorphous Germanium silicon layer 106 can fill up the surface of the first germanium silicon layer 105 first
Lattice defect position so that the wedge angle at the top of the first germanium silicon layer 105 disappears, and forms smooth interface,
Defect on interface is less, can improve the carrier in the first germanium silicon layer 106 and the 3rd germanium silicon layer 107
Mobility.And if directly forming the 3rd germanium silicon layer using epitaxy technique on the surface of the first germanium silicon layer 105,
Then the surface of the first germanium silicon layer 105 remains unchanged out-of-flatness, causes the first germanium silicon layer 105 and the 3rd germanium silicon layer
Boundary defect it is more.
Fig. 9 is refer to, using the separation layer 103 as stop-layer, amorphous Germanium silicon layer 106 (please be joined
Examine Fig. 8) and the 3rd germanium silicon layer 107 (refer to Fig. 8) planarized.
Using chemical grinding technique, the germanium silicon layer 107 of the amorphous Germanium silicon layer 103 and the 3rd is put down
Smoothization, removes remaining amorphous Germanium silicon layer 106 and the germanium of part the 3rd higher than the surface of separation layer 103
Silicon layer 107, makes remaining 3rd germanium silicon layer 107a surfaces flat, and flushed with the surface of separation layer 103.
Figure 10 is refer to, the separation layer 103 is etched back to, the surface of separation layer 103 is less than the 3rd germanium silicon
Layer 107a surfaces.
The separation layer 103 can be etched back using dry or wet etch technique, make it is described every
The height of absciss layer 103 declines, and exposes the side wall of the 3rd germanium silicon layer 107a.
In the present embodiment, the surface of the separation layer 103 after being etched back to flushes with the surface of the first germanium silicon layer 105,
So that the side wall of the 3rd germanium silicon layer 107a is completely exposed.In other embodiments of the invention, the isolation
The surface of layer 103 can be above or less than the surface of the first germanium silicon layer 105.
The grid structure of the 3rd germanium silicon layer 107a can be subsequently developed across, then in the grid knot
Source-drain electrode is formed in 3rd germanium silicon layer 107a of structure both sides, so as to form fin formula field effect transistor.
In the present embodiment, the 3rd germanium silicon layer 107a and the first germanium silicon layer 105 are used as one of fin
Point, both have different germanium concentrations.By adjusting the first germanium silicon layer 105 and the 3rd germanium silicon layer 107a
Interior germanium concentration, can cause that fin meets the demand of different performance transistor, further improve in this base
The performance of the fin formula field effect transistor formed on plinth.For example, when the germanium concentration of the 3rd germanium silicon layer 107a is big
When the germanium concentration of the first germanium silicon layer 105, it is adapted to form p-type fin formula field effect transistor on this basis,
Further improve the performance of p-type fin formula field effect transistor；When the germanium concentration of the 3rd germanium silicon layer 107a is less than
During the germanium concentration of the first germanium silicon layer 105, it is adapted to form N-type fin formula field effect transistor on this basis,
Further improve the performance of N-type fin formula field effect transistor.
Embodiments of the invention also provide the semiconductor structure that a kind of use above method is formed.
Figure 10 is refer to, the semiconductor structure includes：Semiconductor substrate 100；Positioned at Semiconductor substrate
The first groove in 100；Separation layer 103 in the first groove, and the surface of the separation layer 103 is high
Have in the surface of Semiconductor substrate 100, between adjacent separation layer 103 and be located at the surface of Semiconductor substrate 100
The first germanium silicon layer 105；Positioned at the 3rd germanium silicon layer 107a on the surface of the first germanium silicon layer 105, the described 3rd
Germanium silicon layer 107a surfaces are higher than the surface of separation layer 103.
In the present embodiment, the surface of the separation layer 103 flushes with the surface of the first germanium silicon layer 105 so that
The side wall of the 3rd germanium silicon layer 107a is completely exposed.In other embodiments of the invention, the separation layer 103
Surface can be above or less than the surface of the first germanium silicon layer 105.The material of the separation layer 103
It is silica.
The germanium concentration of the 3rd germanium silicon layer 107a is different from the germanium concentration of the first germanium silicon layer 105.This implementation
In example, the germanium concentration of the 3rd germanium silicon layer 107a is 25~35%, the germanium concentration of the first germanium silicon layer 105
It is 15~45%.By adjusting the germanium concentration in the first germanium silicon layer 105 and the 3rd germanium silicon layer 107a,
Can cause that fin meets the demand of different performance transistor, further improve the fin for being formed on this basis
The performance of formula field-effect transistor.
Figure 11 to Figure 22 is the forming process schematic diagram of the semiconductor structure of another embodiment of the present invention.
Refer to Figure 11, there is provided Semiconductor substrate 200, the Semiconductor substrate 200 includes first area I
With second area II；The first mask layer 201 with opening 210 is formed on the surface of half conductive substrate 200, cruelly
Expose the part surface of the first area I and second area II of Semiconductor substrate 100.
The first area I and second area II is used to form different transistors.
The forming method of first mask layer 201 is identical with previous embodiment, and therefore not to repeat here.
Figure 12 is refer to, along 210 etch semiconductor substrates 200 of the opening, in Semiconductor substrate 200
First area I and second area II in formed the first groove 202.
The Semiconductor substrate 200 can be etched using dry etch process, the dry etch process can be with
It is plasma etch process, reactive ion etching process etc..In the present embodiment, described first is formed recessed
The method of groove 202 is identical with previous embodiment, and therefore not to repeat here.
Figure 13 is refer to, formed (please join positioned at the first groove 202 (refer to Figure 12) and opening 210
Examine Figure 12) in separation layer 203, the surface of the separation layer 203 flushes with the surface of the first mask layer 201.
The forming method of the separation layer 203 includes：Form full first groove 202 of filling, opening
210 and covering the first mask layer 201 spacer material layer；Using first mask layer 201 as stop-layer,
The spacer material layer is planarized, is formed and isolating that the surface of the first mask layer 201 flushes
Layer 203.
The material of the separation layer 203 is silica, in other embodiments of the invention, the isolation
The material of layer can also be the insulating dielectric materials such as silicon oxynitride.
Refer to Figure 14, remove the first mask layer 201 (refer to Figure 13), I forms the in first area
Two grooves 204, the 3rd groove 205 is formed in second area II.
In the present embodiment, first mask layer 201 is removed using wet-etching technology.In the present embodiment,
The material of first mask layer 201 is silicon nitride, described as etching solution removal using phosphoric acid solution
First mask layer 201.In other embodiments of the invention, can also use and have to the first mask layer 201
There is the dry etch process compared with high etch selectivity.
Figure 15 is refer to, second mask layer 301 of covering Semiconductor substrate 200 first area I is formed.
The forming method of second mask layer 301 includes：Form covering separation layer 203 and semiconductor
Second mask layer of substrate 200；Graphical photoresist is formed in the second mask material layer surface
Layer, with the graphical photoresist layer as mask, etches second mask layer, and removal is located at half
The second mask layer on the second area II of conductor substrate 200, exposes the separation layer of second area II
203 and Semiconductor substrate 200, form second mask layer 301 of covering first area I.
The material of second mask layer 301 is easy to etching removal.It is additionally, since follow-up in the 3rd groove
Need to form germanium silicon layer using epitaxy technique in 205, and the epitaxy technique needs to use temperature higher,
So, second mask layer 301 being capable of high temperature resistant.Specifically, the material of second mask layer 301
Material can be silicon nitride, amorphous carbon or carborundum etc..
In the present embodiment, the material of second mask layer 301 is silicon nitride, using wet-etching technology
Second mask layer is etched, the second mask layer 301 is formed, the wet-etching technology uses phosphoric acid
Solution has Etch selectivity higher as etching solution to the second mask layer, it is to avoid to isolation
Layer 203 and Semiconductor substrate 200 cause to damage.
Figure 16 is refer to, the first germanium silicon layer 206, the first germanium silicon layer 206 are formed in the 3rd groove 205
Surface is less than the surface of separation layer 203.
The first germanium silicon layer 206 is formed using selective epitaxial process, the first germanium silicon layer 206 is
The surface of Semiconductor substrate 200 of the bottom of three groove 205 grows up, due to the first germanium silicon layer 206
With diamond lattice structure, the surface of the first germanium silicon layer 206 of formation has wedge angle.
The reacting gas that the selective epitaxial process is used includes：Ge source gas, silicon source gas, HCl
And H2, wherein, ge source gas is GeH4, silicon source gas include SiH4Or SiH2Cl2Deng silicon-containing gas,
The gas flow of ge source gas, silicon source gas and HCl is 1sccm~1000sccm, H2Flow be
0.1slm~50slm, the temperature of the selective epitaxial process is 300 DEG C~700 DEG C, and pressure is 1Torr
~100Torr.
Due to being coated with the second mask layer 301 on the first area I of the Semiconductor substrate 200, so,
The first germanium silicon layer 206 is only capable of being formed in the semiconductor lining of the bottom of the 3rd groove 205 of second area II
The surface of bottom 200.
The first germanium silicon layer 206 as the fin for ultimately forming a part, side wall is isolated layer 203
Covered, the height of the first germanium silicon layer 206 is the 1/3~2/3 of the depth of the 3rd groove 205, for example, make
Obtain after being subsequently etched back to separation layer 203, the first germanium silicon layer 206 can be still etched back to
Separation layer 203 afterwards is covered.In the present embodiment, the height of the first germanium silicon layer 206 is the 3rd groove
The 1/2 of 205 depth.In other embodiments of the invention, the height of the first germanium silicon layer 206 can be with
It is adjusted according to final fin height to be formed.
Range of germanium concentration in the first germanium silicon layer 206 is 35~45%, by adjusting selective epitaxial mistake
The flow of ge source gas and silicon source gas can adjust the germanium concentration in the first germanium silicon layer 206 in journey.
Figure 17 is refer to, after the second mask layer 301 (refer to Figure 16) of removal, covering semiconductor is formed
3rd mask layer 302 of the second area II of substrate 200.
The forming method of the 3rd mask layer 302 includes：Form covering separation layer 203 and semiconductor
3rd mask layer of substrate 200；Graphical photoresist is formed in the 3rd mask material layer surface
Layer, with the graphical photoresist layer as mask, etches the 3rd mask layer, and removal is located at half
The 3rd mask layer on the first area I of conductor substrate 200, exposes the separation layer of first area I
203 and Semiconductor substrate 200, form the 3rd mask layer 302 of covering second area II.
Material with the second mask layer 301 is identical, and the material of the 3rd mask layer 302 is needed also exist for easily
In etching removal and being capable of high temperature resistant.Specifically, the material of the 3rd mask layer 302 can be nitridation
Silicon or amorphous carbon etc..In the present embodiment, the material of the 3rd mask layer 302 is silicon nitride, is used
Wet-etching technology etches the 3rd mask layer, forms the 3rd mask layer 302, the wet etching
Technique, as etching solution, has Etch selectivity higher using phosphoric acid solution to the 3rd mask layer,
Avoid that separation layer 203 and Semiconductor substrate 200 are caused to damage.
Figure 18 is refer to, the second germanium silicon layer 207, the second germanium silicon layer 207 are formed in the second groove 204
Surface is less than the surface of separation layer 203.
Using with form the identical method of the first germanium silicon layer 206, i.e. selective epitaxial process and form described the
Two germanium silicon layers 207, the surface of the second germanium silicon layer 207 of formation also has wedge angle.
The reacting gas that the selective epitaxial process is used includes：Ge source gas, silicon source gas, HCl
And H2, wherein, ge source gas is GeH4, silicon source gas include SiH4Or SiH2Cl2Deng silicon-containing gas,
The gas flow of ge source gas, silicon source gas and HCl is 1sccm~1000sccm, H2Flow be
0.1slm~50slm, the temperature of the selective epitaxial process is 300 DEG C~700 DEG C, and pressure is 1Torr
~100Torr.
Due to being coated with the 3rd mask layer 302 on the second area II of the Semiconductor substrate 100, so,
The second germanium silicon layer 207 is only capable of being formed in the Semiconductor substrate of the bottom of the second groove 204 of first area I
200 surfaces.
Described can be adjusted by the flow for adjusting ge source gas and silicon source gas during selective epitaxial
Germanium concentration in two germanium silicon layers 207 so that the germanium concentration and the first germanium silicon layer of the second germanium silicon layer 207
206 germanium concentration is different.In the present embodiment, the germanium concentration of the second germanium silicon layer 207 is less than the first germanium silicon
The germanium concentration of layer 206.The germanium concentration of the second germanium silicon layer 207 is 15~25%.It is of the invention other
In embodiment, the germanium concentration of the second germanium silicon layer 207 can also be more than the first germanium silicon layer 206
Germanium concentration.
The height of the second germanium silicon layer 207 is the 1/3~1/2 of the depth of the second groove 204, in the present embodiment,
The height of the second germanium silicon layer 207 is highly identical with the first germanium silicon layer 206, is the second groove 204
The 1/2 of depth.In other embodiments of the invention, the height of the second germanium silicon layer 207 can basis
Final fin height to be formed is adjusted, can be different from the height of the first germanium silicon layer 206.
Figure 19 is refer to, the 3rd mask layer 302 is removed, in the first germanium silicon layer 206, the second germanium silicon layer
207 surfaces form amorphous Germanium silicon layer 208, full second groove of the filling of amorphous Germanium silicon layer 208
204th, the 3rd groove 205, and cover the separation layer 203.
The amorphous Germanium silicon layer 208 is formed using chemical vapor deposition method, is specifically repeated no more.
In the amorphous Germanium silicon layer 208, germanium concentration is 25~35%.
Figure 20 is refer to, using solid-phase epitaxial growth technique, makes the first germanium silicon layer 206, the second germanium silicon layer
The part amorphous germanium silicon layer 208 on 207 surfaces is changed into the 3rd germanium silicon layer 209, the 3rd germanium silicon layer 209
Surface is higher than the surface of separation layer 203.
Germanium concentration in the 3rd germanium silicon layer 209 determines by the germanium concentration of amorphous Germanium silicon layer 208, institute
State the germanium concentration and the first germanium silicon layer 206 in the 3rd germanium silicon layer 209, the germanium concentration in the second germanium silicon layer 207
It is different.In the present embodiment, the germanium concentration in the first germanium silicon layer 206 is higher than in the 3rd germanium silicon layer 209
Germanium concentration, germanium concentration in the second germanium silicon layer 207 is less than the germanium concentration in the 3rd germanium silicon layer 209.Tool
Range of germanium concentration in the 3rd germanium silicon layer 209 of body is 25~35%.
The growth temperature of the solid-phase epitaxial growth technique is 600 DEG C~800 DEG C, and the first germanium silicon layer
206 and the 3rd germanium silicon layer 209 there is smooth interface, the second germanium silicon layer 207 and the 3rd germanium silicon layer
209 also have smooth interface, and defect is less.
Figure 21 is refer to, using separation layer 203 as stop-layer, to the germanium of amorphous Germanium silicon layer 208 and the 3rd
Silicon layer 209 is planarized.
Using chemical grinding technique, to the amorphous Germanium silicon layer 208 on first area I and second area II
Planarized with the 3rd germanium silicon layer 209, removed remaining amorphous Germanium silicon layer 208 and higher than isolation
The germanium silicon layer 209 of part the 3rd on 203 surface of layer, makes remaining 3rd germanium silicon layer 209a surfaces flat, and
Flushed with the surface of separation layer 203.
Figure 22 is refer to, the separation layer 203 is etched back to, the surface of separation layer 203 is less than the 3rd germanium silicon
Layer 209a surfaces.
The separation layer 203 can be etched back using dry or wet etch technique, make it is described every
The height of absciss layer 203 declines, and exposes the side wall of the 3rd germanium silicon layer 209a.
In the present embodiment, the surface of the separation layer 203 after being etched back to and the first germanium silicon layer 206, the second germanium silicon
207 surface of layer flush so that the side wall of the 3rd germanium silicon layer 209a is completely exposed.In other realities of the invention
Apply in example, the surface of the separation layer 203 can be above or less than the first germanium silicon layer 206, second
The surface of germanium silicon layer 207.
The grid structure of the 3rd germanium silicon layer 209a can be subsequently developed across, then in the grid knot
Source-drain electrode is formed in 3rd germanium silicon layer 209 of structure both sides, so that respectively in first area I and second area
Fin formula field effect transistor is formed on II.
In the present embodiment, the 3rd germanium silicon layer 209a and the first germanium silicon layer 206 are used as on the I of first area
Fin a part, both have different germanium concentrations；3rd germanium silicon layer 209a and the second germanium silicon layer 207
Used as a part for the fin on second area II, both also have different germanium concentrations.Also, it is described
Germanium concentration of the germanium concentration of the 3rd germanium silicon layer 209a less than the first germanium silicon layer 206；3rd germanium silicon layer 209a
Germanium concentration more than the second germanium silicon layer 207 germanium concentration；So that the first area I and second area
II suitably forms the fin formula field effect transistor of different performance or type respectively.For example, in first area I
Upper formation p-type fin formula field effect transistor, forms N-type fin formula field effect transistor on second area II,
Effectively improve the performance of different types of fin formula field effect transistor.
Embodiments of the invention also provide the semiconductor structure that a kind of use above method is formed.
Figure 22 is refer to, the semiconductor structure includes：Semiconductor substrate 200, the Semiconductor substrate
200 include first area I and second area II；Positioned at the first area I of Semiconductor substrate 200 and second
The first groove in the II of region；Separation layer 203 in the first groove, the surface of the separation layer 203
Higher than the surface of Semiconductor substrate 200；Semiconductor substrate 200 first between adjacent separation layer 203
The second germanium silicon layer 207 on region I surfaces；Semiconductor substrate 200 between adjacent separation layer 203
The first germanium silicon layer 206 in two regions II surfaces；Positioned at the first germanium silicon layer 206 and the second germanium silicon layer 207
The 3rd germanium silicon layer 209a on surface, the 3rd germanium silicon layer 209a surfaces are higher than the surface of separation layer 203.
The surface of the separation layer 203 flushes with the first germanium silicon layer 206, the surface of the second germanium silicon layer 207, makes
The side wall for obtaining the 3rd germanium silicon layer 209a is completely exposed.In other embodiments of the invention, the separation layer
203 surface can be above or less than the first germanium silicon layer 206, the surface of the second germanium silicon layer 207.Institute
The material for stating separation layer 203 is silica.
The 3rd germanium silicon layer 209a and the first germanium silicon layer 206 are used as one of the fin on the I of first area
Point, both have different germanium concentrations；3rd germanium silicon layer 209a and the second germanium silicon layer 207 are used as the secondth area
A part for fin on the II of domain, both also have different germanium concentrations.Also, the 3rd germanium silicon layer
Germanium concentration of the germanium concentration of 209a less than the first germanium silicon layer 206；The germanium concentration of the 3rd germanium silicon layer 209a is more than
The germanium concentration of the second germanium silicon layer 207；So that the first area I and second area II are adapted to respectively
Form the fin formula field effect transistor of different performance or type.For example, suitably forming P on the I of first area
Type fin formula field effect transistor, suitably forms N-type fin formula field effect transistor on second area II, can
To effectively improve the performance of different types of fin formula field effect transistor.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Semiconductor substrate is provided；
The mask layer with opening is formed in half guide bush basal surface, the part surface of Semiconductor substrate is exposed；
Along the opening etch semiconductor substrates, the first groove is formed in Semiconductor substrate；
The separation layer in the first groove and opening is formed, the insulation surface is neat with mask layer surface
It is flat；
The mask layer is removed, the second groove is formed；
The first germanium silicon layer is formed in the second groove, the first germanium silicon surface is less than insulation surface；
The amorphous Germanium silicon layer of full second groove of filling and covering separation layer is formed in the first germanium silicon surface；
Using solid-phase epitaxial growth technique, it is changed into the part amorphous germanium silicon layer of the first germanium silicon surface
3rd germanium silicon layer, the 3rd germanium silicon surface is higher than insulation surface；
Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；
The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.
2. the forming method of semiconductor structure according to claim 1, it is characterised in that first germanium
Germanium concentration in silicon layer is different from the germanium concentration in the 3rd germanium silicon layer.
3. the forming method of semiconductor structure according to claim 2, it is characterised in that first germanium
Range of germanium concentration in silicon layer is 15%~45%, and the range of germanium concentration in the 3rd germanium silicon layer is
25%~35%.
4. the forming method of semiconductor structure according to claim 1, it is characterised in that using selectivity
Epitaxy technique forms the first germanium silicon layer.
5. the forming method of semiconductor structure according to claim 1, it is characterised in that first germanium
The height of silicon layer is the 1/3~1/2 of the second depth of groove.
6. the forming method of semiconductor structure according to claim 1, it is characterised in that using chemical gas
Phase depositing operation forms the amorphous Germanium silicon layer.
7. the forming method of semiconductor structure according to claim 6, it is characterised in that the chemical gas
The silicon source gas that phase depositing operation is used is SiH4Or SiH2Cl2, ge source gas is GeH4, temperature
It it is 400 DEG C~600 DEG C, pressure is 5Torr~100Torr.
8. the forming method of semiconductor structure according to claim 1, it is characterised in that outside the solid phase
The growth temperature of growth process is 600 DEG C~800 DEG C.
9. the semiconductor structure for being formed using the method described in any claim in claim 1 to 8, its
It is characterised by, including：
Semiconductor substrate；
The first groove in Semiconductor substrate；
Separation layer in the first groove, and the insulation surface is higher than semiconductor substrate surface；
First germanium silicon layer of the semiconductor substrate surface between adjacent separation layer；
Positioned at the 3rd germanium silicon layer of the first germanium silicon surface, the 3rd germanium silicon surface is higher than separation layer table
Face.
10. a kind of forming method of semiconductor structure, it is characterised in that including：
Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；
The first mask layer with opening is formed in half guide bush basal surface, the first of Semiconductor substrate is exposed
Region and the part surface of second area；
Along the opening etch semiconductor substrates, the shape in the first area of Semiconductor substrate and second area
Into the first groove；
Form the separation layer in the first groove and opening, the insulation surface and the first mask layer table
Face flushes；
The first mask layer is removed, the second groove is formed in first area, the 3rd groove is formed in second area；
Form the second mask layer of covering Semiconductor substrate first area；
The first germanium silicon layer is formed in the 3rd groove, the first germanium silicon surface is less than insulation surface；
After removing the second mask layer, the 3rd mask layer of covering Semiconductor substrate second area is formed；
The second germanium silicon layer is formed in the second groove, the second germanium silicon surface is less than insulation surface；
The 3rd mask layer is removed, amorphous Germanium silicon is formed in the first germanium silicon layer, the second germanium silicon surface
Layer, the filling of amorphous Germanium silicon layer full second groove, the 3rd groove, and cover the separation layer；
Using solid-phase epitaxial growth technique, make the first germanium silicon layer, the part amorphous of the second germanium silicon surface
Germanium silicon layer is changed into the 3rd germanium silicon layer, and the 3rd germanium silicon surface is higher than insulation surface；
Using separation layer as stop-layer, amorphous Germanium silicon layer and the 3rd germanium silicon layer are planarized；
The separation layer is etched back to, insulation surface is less than the 3rd germanium silicon surface.
The forming method of 11. semiconductor structures according to claim 10, it is characterised in that first germanium
Higher than the germanium concentration in the 3rd germanium silicon layer, the germanium concentration in the second germanium silicon layer is less than germanium concentration in silicon layer
Germanium concentration in 3rd germanium silicon layer.
The forming method of 12. semiconductor structures according to claim 11, it is characterised in that first germanium
Range of germanium concentration in silicon layer is 35~45%, and the range of germanium concentration in the second germanium silicon layer is 15~25%,
Range of germanium concentration in 3rd germanium silicon layer is 25~35%.
The forming method of 13. semiconductor structures according to claim 10, it is characterised in that using selectivity
Epitaxy technique forms the first germanium silicon layer, the second germanium silicon layer.
The forming method of 14. semiconductor structures according to claim 10, it is characterised in that first germanium
The height of silicon layer is the 1/3~1/2 of the 3rd depth of groove；The height of the second germanium silicon layer is the second groove
The 1/3~1/2 of depth.
The forming method of 15. semiconductor structures according to claim 10, it is characterised in that using chemical gas
Phase depositing operation forms the amorphous Germanium silicon layer.
The forming method of 16. semiconductor structures according to claim 15, it is characterised in that the chemical gas
The silicon source gas that phase depositing operation is used is SiH4Or SiH2Cl2, ge source gas is GeH4, temperature
It it is 400 DEG C~600 DEG C, pressure is 5Torr~100Torr.
The forming method of 17. semiconductor structures according to claim 10, it is characterised in that outside the solid phase
The growth temperature of growth process is 600 DEG C~800 DEG C.
The forming method of 18. semiconductor structures according to claim 10, it is characterised in that described second covers
The forming method of film layer includes：Form the second mask layer of covering separation layer and Semiconductor substrate；
Graphical photoresist layer is formed in the second mask material layer surface；With the graphical photoresist layer
Be mask, etch second mask layer, removal on Semiconductor substrate second area the
Two mask layers, expose the separation layer and Semiconductor substrate of second area, form the firstth area of covering
Second mask layer in domain.
The forming method of 19. semiconductor structures according to claim 10, it is characterised in that the described 3rd covers
The forming method of film layer includes：Form the 3rd mask layer of covering separation layer and Semiconductor substrate；
Graphical photoresist layer is formed in the 3rd mask material layer surface；With the graphical photoresist layer
Be mask, etch the 3rd mask layer, removal on Semiconductor substrate first area the
Three mask layers, expose the separation layer and Semiconductor substrate of first area, form the secondth area of covering
3rd mask layer in domain.
20. semiconductor structures formed using the method described in any claim in claim 10 to 19,
It is characterised in that it includes：
Semiconductor substrate, the Semiconductor substrate includes first area and second area；
The first groove in the first area and second area of Semiconductor substrate；
Separation layer in the first groove, the insulation surface is higher than semiconductor substrate surface；
The second germanium silicon layer on the Semiconductor substrate first area surface between adjacent separation layer；
The first germanium silicon layer on the Semiconductor substrate second area surface between adjacent separation layer；
Positioned at the first germanium silicon layer and the 3rd germanium silicon layer of the second germanium silicon surface, the 3rd germanium silicon layer
Surface is higher than insulation surface.
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| CN109786330A (en) * | 2017-11-15 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Integrated circuit device fin, integrated circuit and forming method thereof |
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| EP2717316A1 (en) * | 2012-10-05 | 2014-04-09 | Imec | Method for producing strained germanium fin structures |
| CN103811325A (en) * | 2012-11-13 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor forming method |
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