CN111128676B - Nanowire and manufacturing method thereof - Google Patents

Nanowire and manufacturing method thereof Download PDF

Info

Publication number
CN111128676B
CN111128676B CN201911271622.7A CN201911271622A CN111128676B CN 111128676 B CN111128676 B CN 111128676B CN 201911271622 A CN201911271622 A CN 201911271622A CN 111128676 B CN111128676 B CN 111128676B
Authority
CN
China
Prior art keywords
thin film
nanowire
etching
fin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911271622.7A
Other languages
Chinese (zh)
Other versions
CN111128676A (en
Inventor
王桂磊
亨利·H·阿达姆松
孔真真
李俊峰
殷华湘
王文武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201911271622.7A priority Critical patent/CN111128676B/en
Publication of CN111128676A publication Critical patent/CN111128676A/en
Application granted granted Critical
Publication of CN111128676B publication Critical patent/CN111128676B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention relates to the technical field of semiconductors, and discloses a method for manufacturing a nanowire, which comprises the following steps: forming a plurality of grooves on a substrate along a first direction; selectively epitaxially growing a heterogeneous thin film in each trench; depositing a dielectric layer to cover the heterogeneous thin film; carrying out oxidation cycle annealing treatment on the heterogeneous thin film to form a high-quality high-mobility thin film; a number of nanowires are formed on a substrate. The invention also provides the nanowire manufactured by the method. By adopting the technical scheme of the invention, the generation of the defects of the heterogeneous thin film can be reduced, and the nanowire with high mobility can be manufactured.

Description

Nanowire and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a nanowire and a manufacturing method thereof.
Background
The current fin field effect transistor (FinFET) can finally reach a limit point due to the self-structure problem, namely, the FinFET can not be continuously reduced along with the reduction of process nodes, particularly after 5nm. The problem can be solved by adopting a new Gate-All-Around (GAA) structure. The GAA structure allows the size of the transistor to be adjusted to ensure that the gate is not only on the top and both sides, but also below the channel.
In the conventional silicon material, it is very difficult to further improve the carrier mobility, and it is necessary to introduce a high mobility material, such as silicon germanium with high germanium composition. However, how to manufacture the high mobility nanowires by using the high mobility material with high efficiency is a difficult problem in research.
Disclosure of Invention
The invention provides a nanowire and a manufacturing method thereof, aiming at solving the problem of how to efficiently utilize a high-mobility material to manufacture a high-mobility nanowire in the prior art.
The invention provides a method for manufacturing a nanowire, which comprises the following steps: forming a plurality of grooves on the substrate along a first direction; selectively epitaxially growing a heterogeneous thin film in each trench; depositing a dielectric layer to cover the heterogeneous thin film; carrying out oxidation cycle annealing treatment on the heterogeneous thin film to form a high-mobility thin film; a number of nanowires are formed on a substrate.
By adopting the technical scheme, on one hand, the groove on the substrate is utilized to grow the heterogeneous thin film, and the heterogeneous thin film is directly grown on the non-substrate, so that the side limitation is provided for the growth of the crystal lattice of the heterogeneous thin film, the generation of excessive crystal lattice defects can be inhibited, the high-quality heterogeneous thin film is obtained, the quality and the carrier mobility of the manufactured nanowire are improved, and the performance of a semiconductor device is improved. On the other hand, when the heterogeneous thin film is subjected to oxidation cycle annealing treatment, a low-mobility material (e.g., silicon) in the heterogeneous thin film is consumed, thereby increasing the occupation ratio of a high-mobility material (e.g., germanium) therein; meanwhile, under the obstruction of the dielectric layer, the outward diffusion of high-mobility material atoms in the heterogeneous film in the oxidation cycle annealing treatment process can be avoided, so that the carrier mobility of the manufactured nanowire is greatly improved.
Further, the forming of the trench includes the steps of:
forming a fin structure on a substrate;
depositing a shallow trench isolation, and performing first planarization treatment on the shallow trench isolation to expose the top of the fin-shaped structure;
and etching the fin-shaped structure to form a groove, wherein a single crystal seed layer is left at the bottom of the groove.
The side wall of the groove generated by adopting the technical scheme is in shallow groove isolation, and the shallow groove isolation is combined with the dielectric layer at the top of the heterogeneous thin film, so that the diffusion of high-mobility material atoms in the heterogeneous thin film in the oxidation cycle annealing treatment process can be more effectively inhibited.
Furthermore, the fin-shaped structure is etched by adopting a dry etching process, a CVD thermal etching process or a chemical liquid etching process to form a groove.
By adopting the technical scheme, high-quality grooves can be obtained, wherein the dry etching process is adopted, so that the free control of the etching depth is facilitated; the CVD thermal etching process and the chemical liquid etching process are adopted, the single crystal seed layer at the bottom of the groove is provided with the inclined plane attached to the side wall of the groove, the structure has the advantages of being beneficial to forming of heterogeneous films and controlling of defects, and the combination of the groove structure is beneficial to annihilation of lateral defects during selective epitaxial growth of the heterogeneous films, so that growth of large lattice mismatch materials on the substrate can be realized.
Further, the thickness of the single crystal seed layer is greater than 1nm.
By adopting the technical scheme, when the thickness of the single crystal seed layer is more than 1nm, the growth of a high-quality heterogeneous film is facilitated.
Further, the formation of the nanowire comprises the following steps: a second planarization process to expose the top of the high mobility film; depositing a material layer, etching the material layer, and forming a plurality of fin parts along a second direction; anisotropically etching the shallow trench isolation to expose the high mobility film with the whole height except the covering part of the fin part; and selectively etching to remove the fin part and isotropically etching to expose the nanowire.
By adopting the technical scheme, the part of the fin part covered by the shallow trench isolation is used as a support structure to support the formed nanowire, so that the stability of the structure is further improved, and the performance of the device is improved.
Further, the material layer is Si 3 N 4 Or Si y O z N k The thickness of the material layer is 10-200 nm; wherein y =0.41, z =0.04, k =0.55.
By adopting the technical scheme, si 3 N 4 And SiO y N z And common dielectric layer SiO 2 The etching selection ratio is high, and the etching of the material layer is more favorable.
Further, the heterogeneous thin film is Si 1-x Ge x Wherein X is more than or equal to 0.1 and less than or equal to 0.3.
By adopting the technical scheme, when the atomic proportion of Ge in the heterogeneous thin film is between 0.1 and 0.3, the preparation of the nanowire with high mobility is facilitated.
Further, in an oxygen atmosphere, high-temperature annealing is carried out on the heterogeneous film, so that oxidation cycle annealing treatment is carried out on the heterogeneous film.
Furthermore, the annealing temperature of the high-temperature annealing is 700-900 ℃, the oxygen flow is 20-200 sccm, and the annealing time is 2-16 h.
Furthermore, the annealing temperature of the high-temperature annealing is 900-1050 ℃, the oxygen flow is 20-200 sccm, and the annealing time is 2-16 h.
By adopting the high-temperature annealing mode, the germanium-silicon nanowire with the germanium component of more than 70 percent can be obtained, and the mobility of the manufactured nanowire is further improved.
Further, the substrate is a silicon substrate or an SOI substrate.
The substrate can be used for manufacturing the nanowire with high mobility, and particularly when the SOI substrate is used, due to the fact that the substrate is provided with the oxide layer, the heterogeneous film oxidation cycle annealing treatment is carried out on the upper portion of the oxide layer, diffusion of high-mobility material atoms such as Ge in the heterogeneous film is further avoided, the effect of the oxidation cycle annealing treatment is better, and the efficiency of the oxidation cycle annealing treatment is higher.
The invention also provides a nanowire which is manufactured and formed by any one of the methods.
By adopting the technical scheme, the generation of the defects of the heterogeneous thin film is controlled through the groove, and the effective utilization rate of the high-mobility material is improved by carrying out oxidation cycle annealing treatment under the isolation and the blocking of the dielectric layer and the shallow groove, so that the nanowire with high mobility is manufactured.
Compared with the prior art, the invention has the following beneficial effects:
1. on one hand, the invention utilizes the groove on the substrate to grow the heterogeneous thin film, but not directly grow on the substrate, provides the limit of the side surface for the growth of the crystal lattice of the heterogeneous thin film, and can inhibit the generation of excessive crystal lattice defects, thereby growing the high-quality heterogeneous thin film, improving the mobility of the manufactured nanowire and improving the performance of a semiconductor device. On the other hand, when the heterogeneous thin film is subjected to oxidation cycle annealing treatment, the low-mobility material in the heterogeneous thin film is consumed, so that the proportion of the high-mobility material in the heterogeneous thin film is increased; meanwhile, under the obstruction of the dielectric layer, the outward diffusion of high-mobility material atoms in the heterogeneous thin film in the oxidation cycle annealing treatment process can be effectively avoided, so that the reduction of mobility caused by the diffusion of atoms in the oxidation process is effectively avoided, and the mobility of the manufactured nanowire is greatly improved.
2. The side wall of the groove generated by the invention is shallow groove isolation, and the shallow groove isolation is combined with the dielectric layer on the top of the heterogeneous thin film, so that the diffusion of atoms of the heterogeneous Bao Mochong high-mobility material in the oxidation process can be more effectively inhibited.
Drawings
FIG. 1 is a flow chart of a method of fabricating nanowires according to the present invention;
fig. 2 to 20 are structural diagrams corresponding to each step of the method for manufacturing a nanowire according to the present invention.
The structure comprises a substrate 1, a fin-shaped structure 2, a shallow groove isolation 3, a groove 4, a single crystal seed layer 5, a heterogeneous film 6, a dielectric layer 7, a high mobility film 8, a nanowire 9, a material layer 10, a fin part 11 and a support structure 12.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
The invention provides a nanowire and a manufacturing method thereof, wherein the nanowire is manufactured by selectively epitaxially growing a heterogeneous film in a groove, performing oxidation cycle annealing treatment on the heterogeneous film under the obstruction of the groove and a dielectric layer to manufacture a high-mobility film, and etching to form the nanowire, so that the mobility of the nanowire is greatly improved, and the performance of a device is improved.
The manufacturing method provided by the invention is particularly suitable for manufacturing the high-mobility channel nanowire.
One embodiment of the present invention relates to a method for manufacturing a nanowire, as shown in fig. 1, including the following steps:
s1, forming a plurality of grooves 4 on the substrate 1 along a first direction.
It should be further noted that the first direction can be set according to specific production and manufacturing conditions, and the present invention is not limited in particular. The number of trenches 4 is set according to the specific device requirements. The cross-sectional shape of the groove 4 may be rectangular or elliptical. The sidewall of the trench 4 is preferably made of an insulating material such as silicon dioxide.
Specifically, in the present invention, the cross-sectional shape of the groove 4 is rectangular.
As a preferred embodiment of this step, the substrate 1 is a silicon substrate or an SOI substrate.
In particular, the present invention preferably uses an SOI substrate for the fabrication of the nanowires 9, with the top silicon being 55nm.
As a preferred embodiment of this step, the formation of the trench 4 comprises the steps of:
s11, forming a fin-shaped structure 2 on a substrate 1; as shown in fig. 2-3.
Specifically, as shown in fig. 2, the width of the nanowire 9 is defined on the substrate 1 by lithography, and any method satisfying the process requirements in the prior art can be used for lithography.
As shown in fig. 3, the fin structure 2 is dry etched according to the width defined in fig. 1. Of course, besides the dry etching shown in the present invention, a CVD thermal etching process may also be adopted, and other processes such as chemical liquid etching may also be adopted to form the fin structure 2 by etching.
S12, depositing the shallow trench isolation 3, and performing first planarization treatment on the shallow trench isolation 3 to expose the top of the fin-shaped structure 2; as shown in fig. 4-5.
Specifically, as shown in fig. 4, after the photoresist on the top of the fin-shaped structure 2 is removed, the shallow trench isolation 3 is deposited on the formed structure; the shallow trench isolation 3 may be made of silicon dioxide, silicon nitride, or other materials meeting the working requirement, and the deposited height should be sufficient to embed the protruding fin structures 2.
As shown in fig. 5, a first planarization process is performed on the shallow trench isolation 3 to expose the top of the fin structure 2, wherein the planarization process may be performed by CMP or the like and stops on the top surface of the fin structure 2.
And S13, etching the fin-shaped structure 2 to form a groove 4, wherein a single crystal seed layer 5 is left at the bottom of the groove 4.
It should be noted that different etching processes can be selected according to the set shape of the trench 4. The single crystal seed layer 5 is mainly used as a basis for the lattice growth of the heterogeneous thin film 6, and its shape is formed according to the specifically adopted etching process.
As a preferred embodiment of this step, the fin-shaped structure 2 is etched by a dry etching process, a CVD thermal etching process, or a chemical liquid etching process to form the trench 4.
Specifically, the dry etching process is taken as an example in the present invention, as shown in fig. 6. The dry etching process can select methods such as plasma etching, atomic layer etching and the like, the etching depth of the dry etching process can be freely controlled, and the formed single crystal seed layer 5 at the bottom of the groove 4 is regular and rectangular.
In addition, as shown in fig. 19 and 20, the trenches 4 formed by the CVD thermal etching process or the chemical liquid etching process are respectively shown, and the single crystal seed layer 5 formed by these two methods has an inclined surface attached to the sidewall (shallow trench isolation 3), so that the single crystal seed layer 5 is more favorable for controlling defects caused by the selective epitaxial formation of the hetero film 6, and is more favorable for the formation of the hetero film 6.
Specifically, the fin structure 2 may be CVD thermally etched using HCl gas, or the fin structure 2 may be chemically etched using an alkaline solution to form the trench 4.
As a preferred embodiment of this step, the thickness of the single crystal seed layer 5 is greater than 1nm.
S2, selectively epitaxially growing a hetero film 6 in each trench 4, as shown in fig. 7.
It should be noted that the heterogeneous thin film 6 may be grown not to exceed the depth of the trench 4, or may be grown to the outside of the trench 4 beyond the trench 4, and when the heterogeneous thin film 6 is grown beyond the trench 4, the lattice defects are larger than those of the heterogeneous thin film 6 in the trench 4 due to the irregular growth thereof, and it is necessary to planarize the heterogeneous thin film 6 grown outside the trench 4.
Preferably, in this step, the selective epitaxial growth of the heterogeneous thin film 6 does not extend beyond the depth of the trench 4, i.e. within the trench 4, on the single crystal seed layer 5.
As an originalIn a preferred embodiment of the step, the heterogeneous thin film 6 is Si 1-x Ge x Wherein X is more than or equal to 0.1 and less than or equal to 0.3.
Note that the hetero thin film 6 may be made of other high mobility material such as GaAs (gallium arsenide), inAs (indium arsenide), or InSb (indium antimonide).
S3, depositing a dielectric layer 7 to cover the heterogeneous thin film 6, as shown in FIG. 8.
It should be noted that the dielectric layer 7 may be deposited by any method known in the art, and the planarization process is not required in this step. The dielectric layer 7 may be made of an insulating material such as silicon dioxide or silicon nitride, and the thickness of the dielectric layer 7 is preferably such that the heterogeneous thin film 6 can be completely covered.
And S4, carrying out oxidation cycle annealing treatment on the heterogeneous thin film 6 to form a high mobility thin film 8, as shown in figure 9.
As a preferred embodiment of the present step, in an oxygen atmosphere, the heterogeneous thin film 6 is subjected to high-temperature annealing to realize oxidation cycle annealing treatment of the heterogeneous thin film 6;
wherein, when the heterogeneous film 6 is a germanium-silicon film and the concentration of germanium atoms in the nanowire 9 which is required to be finally manufactured is 70-95%, the annealing temperature corresponding to the high-temperature annealing operation is 700-900 ℃, the oxygen flow is 20-200 sccm, and the annealing time is 2-16 h;
when the heterogeneous thin film 6 is a germanium-silicon thin film, and when the concentration of germanium atoms in the nanowire 9 which is required to be finally manufactured is more than 95%, the annealing temperature of high-temperature annealing is 900-1050 ℃, the oxygen flow is 20-200 sccm, and the annealing time is 2-16 h.
It should be noted that, when the high-temperature annealing is performed, the temperature in the high-temperature annealing reaction chamber should be gradually decreased with the increase of the Ge atom ratio in the heterogeneous thin film 6, and specifically, the annealing temperature, the oxygen flow rate and the annealing time may be set according to practical situations, and are not limited specifically herein.
And S5, forming a plurality of nanowires 9 on the substrate 1.
Note that the width and the shape of the formed nanowire 9 are the width and the shape defined in step S1.
As a preferred embodiment of this step, the formation of the nanowires 9 comprises the following steps:
s51, second planarization treatment to expose the top of the high mobility thin film 8, as shown in fig. 10.
Specifically, if the height of the grown heterogeneous thin film 6 is smaller than the depth of the trench 4, the second planarization treatment can be performed on the dielectric layer 7 and the shallow trench isolation 3 by using processes such as CMP and the like to expose the top of the high mobility thin film 8;
if the height of the grown heterogeneous thin film 6 is equal to the depth of the trench 4, a second planarization process may be performed on the dielectric layer 7 by using a process such as CMP to expose the top of the high mobility thin film 8.
S52, depositing the material layer 10, and etching the material layer 10 (as shown in fig. 11), and forming a plurality of fins 11 along the second direction, as shown in fig. 12.
The second direction is different from the first direction, and preferably, the second direction is perpendicular to the first direction. The fin 11 defines a support structure 12 for the nanowire 9, which support structure 12 is a structure below the fin 11.
Further, the material layer 10 is Si 3 N 4 Or Si y O z N k The thickness of the material layer 10 is 10-200 nm; wherein y =0.41, z =0.04, k =0.55.
It should be noted that other materials with high etching selectivity to the material of the shallow trench isolation 3 in the prior art may also be selected.
S53, anisotropically etching the shallow trench isolation 3 to expose the high-mobility film 8 with the whole height except the part covered by the fin part 11; as shown in fig. 13-15, fig. 13 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A ', fig. 14 isbase:Sub>A sectional view taken along line B-B ', and fig. 15 isbase:Sub>A sectional view taken along line C-C '.
When the shallow trench isolation 3 is etched, the portion other than the portion covered by the fin 11 is etched.
S54, selectively etching to remove the fin portion 11, and isotropically etching to expose the nanowire 9, as shown in fig. 16-18, where fig. 16 isbase:Sub>A cross-sectional viewbase:Sub>A-base:Sub>A ', fig. 17 isbase:Sub>A cross-sectional view B-B ', and fig. 18 isbase:Sub>A cross-sectional view C-C '.
It should be noted that, the isotropic etching is to etch the oxide and the oxide layer or the oxide under the etched region and the high mobility thin film 8 in step S53, so as to expose the nanowire 9; wherein, the oxide is a structure formed by oxidizing the single crystal seed layer 5 after the oxidation cycle annealing treatment; the oxide layer is an intermediate oxide layer when the substrate 1 is an SOI substrate.
The invention also provides a nanowire, the nanowire 9 being manufactured by any one of the above-mentioned methods.
The invention also provides a specific embodiment of the method for manufacturing the nanowire, which comprises the following steps:
s1, forming a plurality of grooves 4 on the substrate 1 along a first direction. The substrate 1 is an SOI substrate, and specifically, the SOI substrate includes a silicon layer, an oxide layer, and a silicon substrate from top to bottom. The cross-sectional shape of the groove 4 is rectangular. The formation of the trench 4 includes the steps of:
s11, forming a fin-shaped structure 2 on a substrate 1; as shown in fig. 2-3.
S12, depositing a shallow trench isolation 3, and performing first planarization treatment on the shallow trench isolation 3 to expose the top of the fin-shaped structure 2; as shown in fig. 4-5.
And S13, etching the fin-shaped structure 2 by adopting a dry etching process to form a groove 4, and leaving a single crystal seed layer 5 at the bottom of the groove 4 as shown in FIG. 6. The thickness of the single crystal seed layer 5 was 1.5nm.
S2, selectively epitaxially growing a hetero film 6 in each trench 4, as shown in fig. 7. Specifically, the heterogeneous thin film 6 is Si 1-x Ge x Wherein X =0.2.
S3, depositing a dielectric layer 7 to cover the heterogeneous thin film 6, as shown in figure 8.
And S4, carrying out oxidation cycle annealing treatment on the heterogeneous thin film 6 to form a high mobility thin film 8, as shown in figure 9. Specifically, the heterogeneous thin film 6 is annealed at a high temperature in an oxygen atmosphere to perform an oxidation cycle annealing treatment on the heterogeneous thin film 6, and it should be noted that after the oxidation cycle annealing treatment, the single crystal seed layer 5 correspondingly forms an oxide. Specifically, in order to make the germanium atom concentration in the finally manufactured nanowire 9 more than 95%, the annealing temperature of the high-temperature annealing is 900 to 1050 ℃, the oxygen flow is 20 to 200sccm, and the annealing time is 2 to 16 hours.
And S5, forming a plurality of nanowires 9 on the substrate 1. The formation of the nanowires 9 comprises the following steps:
s51, a second planarization process is performed on the dielectric layer 7 and the shallow trench isolation 3 to expose the top of the high mobility film 8, as shown in fig. 10.
S52, depositing the material layer 10, and etching the material layer 10 (as shown in fig. 11), and forming a plurality of fins 11 along the second direction, as shown in fig. 12. The material layer 10 is Si 3 N 4 Or Si y O z N k The layer thickness of the material layer 10 is 100nm; wherein y =0.41, z =0.04, k =0.55.
S53, anisotropically etching the shallow trench isolation 3 to expose the high mobility film 8 with the whole height except the part covered by the fin part 11; as shown in fig. 13-15.
S54, selectively etching to remove the fin portion 11, and isotropically etching the oxide and the oxide layer to expose the nanowire 9, as shown in fig. 16-18.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention and do not limit the spirit and scope of the present invention. Various modifications and improvements of the technical solutions of the present invention may be made by those skilled in the art without departing from the design concept of the present invention, and the technical contents of the present invention are all described in the claims.

Claims (10)

1. A method for fabricating a nanowire, comprising the steps of:
forming a plurality of grooves on the substrate along a first direction;
selectively epitaxially growing a hetero-film in each of the trenches;
depositing a dielectric layer to cover the heterogeneous thin film;
carrying out oxidation cycle annealing treatment on the heterogeneous thin film to form a high-mobility thin film;
forming a plurality of nanowires on the substrate;
the dielectric layer is made of an insulating material and comprises silicon dioxide or silicon nitride;
the forming of the trench includes the steps of:
forming a fin structure on a substrate;
depositing shallow trench isolation, and performing first planarization treatment on the shallow trench isolation to expose the top of the fin-shaped structure;
etching the fin-shaped structure to form the groove, wherein a single crystal seed layer is left at the bottom of the groove;
the formation of the nanowires comprises the steps of:
a second planarization process to expose a top portion of the high mobility thin film;
depositing a material layer, etching the material layer, and forming a plurality of fin parts along a second direction;
anisotropically etching the shallow trench isolation to expose the high mobility film with the full height except the covering part of the fin part;
selectively etching to remove the fin part, and isotropically etching to expose the nanowire;
the material layer is Si 3 N 4 Or Si y O z N k Wherein y =0.41, z =0.04, k =0.55.
2. The method of claim 1, wherein the trench is formed by etching the fin structure using a dry etching process, a CVD thermal etching process, or a chemical liquid etching process.
3. The method of claim 2, wherein the single crystal seed layer has a thickness greater than 1nm.
4. The method of claim 1, wherein the layer thickness of the material layer is 10 to 200nm5.
5. The method of claim 1, wherein the heterogeneous thin film is Si 1-x Ge x Wherein x is more than or equal to 0.1 and less than or equal to 0.3.
6. The method of claim 5, wherein the heterogeneous thin film is annealed at a high temperature in an oxygen atmosphere to perform the oxidation cycle annealing treatment on the heterogeneous thin film.
7. The method for manufacturing the nanowire according to claim 6, wherein the annealing temperature of the high temperature annealing is 700 to 900 ℃, the oxygen flow is 20 to 200sccm, and the annealing time is 2 to 169h.
8. The method for manufacturing the nanowire according to claim 6, wherein the annealing temperature of the high-temperature annealing is 900 to 1050 ℃, the oxygen flow is 20 to 200sccm, and the annealing time is 2 to 169h.
9. The method of claim 1, wherein the substrate is a silicon substrate or an SOI substrate.
10. A nanowire made by the method of any one of claims 1~9.
CN201911271622.7A 2019-12-12 2019-12-12 Nanowire and manufacturing method thereof Active CN111128676B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911271622.7A CN111128676B (en) 2019-12-12 2019-12-12 Nanowire and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911271622.7A CN111128676B (en) 2019-12-12 2019-12-12 Nanowire and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN111128676A CN111128676A (en) 2020-05-08
CN111128676B true CN111128676B (en) 2023-02-03

Family

ID=70499396

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911271622.7A Active CN111128676B (en) 2019-12-12 2019-12-12 Nanowire and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111128676B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112117375A (en) * 2020-09-24 2020-12-22 中国科学院微电子研究所 Superconducting nanowire structure and preparation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206293A (en) * 2015-02-03 2016-12-07 联华电子股份有限公司 Form method and this semiconductor structure of the semiconductor structure with nano wire
CN106898643A (en) * 2017-03-16 2017-06-27 北京大学 A kind of mobility channel double nano field of line effect transistor and preparation method thereof
CN108155101A (en) * 2017-12-22 2018-06-12 中国科学院微电子研究所 Stacked nanowire and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006270000A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206293A (en) * 2015-02-03 2016-12-07 联华电子股份有限公司 Form method and this semiconductor structure of the semiconductor structure with nano wire
CN106898643A (en) * 2017-03-16 2017-06-27 北京大学 A kind of mobility channel double nano field of line effect transistor and preparation method thereof
CN108155101A (en) * 2017-12-22 2018-06-12 中国科学院微电子研究所 Stacked nanowire and manufacturing method thereof

Also Published As

Publication number Publication date
CN111128676A (en) 2020-05-08

Similar Documents

Publication Publication Date Title
US11437517B2 (en) Semiconductor structures and methods with high mobility and high energy bandgap materials
TWI539499B (en) Facilitating fabricating gate-all-around nanowire field-effect transistors
TWI731421B (en) Method for forming semiconductor device and semiconductor structure
US8927405B2 (en) Accurate control of distance between suspended semiconductor nanowires and substrate surface
US9608115B2 (en) FinFET having buffer layer between channel and substrate
CN104241361B (en) Semiconductor device with strain technique
CN103972059B (en) Method for forming semiconductor region in the trench
US9620360B1 (en) Fabrication of semiconductor junctions
US20240087961A1 (en) Fin Loss Prevention
CN111128676B (en) Nanowire and manufacturing method thereof
US20230378271A1 (en) Ultra-thin fin structure and method of fabricating the same
CN106549054A (en) Fet and manufacturing method thereof
US20230420565A1 (en) Method for forming dual silicide in manufacturing process of semiconductor structure
KR20190098715A (en) Methods for bottom up fin structure formation
JP2009094156A (en) Semiconductor substrate and semiconductor device
US20200381540A1 (en) Semiconductor device, manufacturing method thereof, and electronic device including the device
CN106409770A (en) Method for forming semiconductor structure
CN106558552B (en) CMOS manufacturing method
CN106653602A (en) Fin field-effect transistor and method for forming fin FET
CN113496882A (en) Manufacturing method for improving mobility of silicon carbide gate oxide layer
JP2013254982A (en) Semiconductor substrate and semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant