CN106856172A - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
- Publication number
- CN106856172A CN106856172A CN201510906921.9A CN201510906921A CN106856172A CN 106856172 A CN106856172 A CN 106856172A CN 201510906921 A CN201510906921 A CN 201510906921A CN 106856172 A CN106856172 A CN 106856172A
- Authority
- CN
- China
- Prior art keywords
- fin
- dielectric layer
- oxygen
- ion
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 230000005669 field effect Effects 0.000 title claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims abstract description 78
- -1 oxonium ion Chemical class 0.000 claims abstract description 64
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 60
- 239000001301 oxygen Substances 0.000 claims description 48
- 229910052760 oxygen Inorganic materials 0.000 claims description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 25
- 229910052735 hafnium Inorganic materials 0.000 claims description 20
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000011435 rock Substances 0.000 claims description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910015801 BaSrTiO Inorganic materials 0.000 claims description 3
- 229910003865 HfCl4 Inorganic materials 0.000 claims description 3
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 3
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical compound Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010408 film Substances 0.000 description 23
- 238000005530 etching Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 210000002381 plasma Anatomy 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, fin is formed with the Semiconductor substrate, the material of the fin is Ge, SiGe or III-V element；It is developed across the pseudo- grid of part fin side wall and top surface；The dielectric layer of the covering Semiconductor substrate, fin and pseudo- grid is formed, the surface of the dielectric layer flushes with the top surface of pseudo- grid；The pseudo- grid are removed, groove is formed；The high-K dielectric layer of oxygen-carrying ion is formed in the side wall and lower surface of the groove；High-K dielectric layer to the oxygen-carrying ion is annealed so that the oxonium ion in the high-K dielectric layer of oxygen-carrying ion is diffused in the fin of bottom portion of groove, and oxonium ion reacts to form boundary layer with fin material；After annealing, the metal gates of filling groove are formed in the high-K dielectric layer.The method of the present invention improves the interfacial characteristics between the high-K dielectric layer of fin formula field effect transistor and fin.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of formation side of fin formula field effect transistor
Method.
Background technology
Continuing to develop with semiconductor process technique of the invention, process node is gradually reduced, rear grid
(gate-last) technique is widely applied, and to obtain preferable threshold voltage, improves device performance.
But when the characteristic size (CD, Critical Dimension) of device further declines, even if using
Grid technique afterwards, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance,
Fin formula field effect transistor (Fin FET) has obtained extensive concern as the replacement of conventional device.
A kind of fin formula field effect transistor of prior art includes：Semiconductor substrate, the Semiconductor substrate
On be formed with the fin of protrusion, fin after semiconductor substrate etching generally by obtaining；Separation layer,
Cover a part for the surface of the Semiconductor substrate and the side wall of fin；Grid structure, across in institute
State on fin, cover top and the side wall of the fin, grid structure includes gate dielectric layer and is situated between positioned at grid
Gate electrode on matter layer.
The material of the gate dielectric layer is silica, and the material of gate electrode is polysilicon.As fin is imitated
Answer the characteristic size of transistor also less and less, in order to reduce the parasitic capacitance of fin formula field effect transistor with
And the leakage current of reduction device, device speed is improved, high-K gate dielectric layer is folded with the grid of metal gate electrode
Rotating fields are introduced in fin formula field effect transistor.In order to avoid the metal material of metal gates is to crystal
The influence of pipe other structures, the metal gates are generally used with the gate stack structure of high-K gate dielectric layer
" grid (gate last) afterwards " technique makes.
The forming process of the metal gates of existing fin formula field effect transistor is：Semiconductor substrate, institute are provided
State and be formed with Semiconductor substrate some fins；Pseudo- grid are formed on the side wall of the fin and surface；Shape
Into the dielectric layer for covering the pseudo- grid, fin and semiconductor substrate surface, the surface of the dielectric layer is higher than
The top surface of pseudo- grid；The dielectric layer is planarized using chemical mechanical milling tech, until exposing puppet
The top surface of grid；The pseudo- grid are removed, groove is formed, the groove exposes the partial sidewall of fin
And top surface；In the middle formation high-K gate dielectric layer and metal gate electrode of the groove.
In order to further improve the performance of the fin formula field effect transistor of formation, such as improve fin field effect
The mobility of transistor channel region carrier, the fin that prior art is formed uses Ge, SiGe or III-V
Element.
The fin formula field effect transistor performance of existing formation still has to be hoisted.
The content of the invention
The problem that the present invention is solved be how to improve the high-K dielectric layer of fin formula field effect transistor and fin it
Between interface performance.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including：
Semiconductor substrate is provided, fin is formed with the Semiconductor substrate, the material of the fin is Ge,
SiGe or III-V element；It is developed across the pseudo- grid of part fin side wall and top surface；Form covering described
The dielectric layer of Semiconductor substrate, fin and pseudo- grid, the surface of the dielectric layer is neat with the top surface of pseudo- grid
It is flat；The pseudo- grid are removed, groove is formed；Oxygen-carrying ion is formed in the side wall and lower surface of the groove
High-K dielectric layer；High-K dielectric layer to the oxygen-carrying ion is annealed so that the height of oxygen-carrying ion
Oxonium ion in K dielectric layer is diffused in the fin of bottom portion of groove, and oxonium ion reacts to be formed with fin material
Boundary layer；After annealing, the metal gates of filling groove are formed in the high-K dielectric layer.
Optionally, the high-K dielectric layer of the oxygen-carrying ion is formed using auto-dope depositing operation.
Optionally, the formation process of the high-K dielectric layer of the oxygen-carrying ion is the ald of auto-dope
Technique.
Optionally, the material of the high-K dielectric layer is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、
ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.
Optionally, the high-K dielectric layer material HfO2, the atom layer deposition process of auto-dope forms oxygen-containing
The process of the high-K dielectric layer of ion includes：Step S21, to being passed through hafnium source gas in deposition chambers；Step
Rapid S22, the first oxygen source gas are passed through to deposition chambers；Step S23, applies radio-frequency power, by hafnium source gas
Body, the first oxygen source gas are dissociated into plasma；The plasma-deposited formation high K dielectrics of step S24 are thin
Film layer；Step S25, after circulation carries out step S21-S24 at least 1-4 times, carries out being passed through the second oxygen source gas
Body, and dissociate the second oxygen source gas, to high K dielectric film layer adulterate oxonium ion the step of；Step S26,
Repeat step S21-S25, the high K dielectric film layer of some oxygen-carrying ions constitutes the K high of oxygen-carrying ion
Dielectric layer.
Optionally, hafnium source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm,
First oxygen source gas are H2O, the flow of the first oxygen source gas is 20~300sccm, and the second oxygen source gas are
O2Or O3, the flow of the second oxygen source gas is 30~200sccm, and deposition chambers pressure is 0.1 support to 8
Support, deposition chambers radio-frequency power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400 degrees Celsius.
Optionally, the concentration of oxonium ion is in the high-K dielectric layer of the oxygen-carrying ion
1E12atom/cm3~1E16atom/cm3, the thickness of the high-K dielectric layer of oxygen-carrying ion is 5~30 angstroms.
Optionally, 600~1200 degrees Celsius when being annealed, annealing time is 30 seconds~60 minutes, is moved back
Fiery atmosphere is atmosphere of inert gases 60 minutes, and annealing atmosphere is atmosphere of inert gases, and annealing atmosphere is inertia.
Optionally, source region and drain region are also formed with the fin of the pseudo- grid both sides.
Optionally, also include：Before the anneal, lid is formed on the high-K dielectric layer surface of oxygen-carrying ion
Layer.
Optionally, the cap rock is metal nitride.
Optionally, the metal nitride is TiN or TaN.
Optionally, the thickness of the cap rock is 10~50 angstroms.
Compared with prior art, technical scheme has advantages below：
The forming method of fin formula field effect transistor of the present invention, is forming the high-K dielectric layer of the oxygen-carrying ion
When, auto-dope technique uniform doping oxonium ion in the high-K dielectric layer for being formed can be used, subsequently may be used
Uniformly it is diffused into the fin of bottom portion of groove with the oxonium ion in the high-K dielectric layer for causing oxygen-carrying ion,
Oxonium ion and fin material react to form boundary layer, in high-K dielectric layer are to be uniformly distributed due to oxonium ion
, thus during annealing, oxonium ion is uniformly diffused into from high-K dielectric layer with the contact surface diverse location of fin
In fin, the diffusion oxygen ion concentration of diverse location is identical on contact surface, thus oxonium ion from it is different
The thickness evenness that position fin material reacts the boundary layer to be formed is higher, and by controlling high K dielectric
The content of oxonium ion, can control the thickness of the boundary layer to be formed in layer, so that the method for the present invention can be with
Thinner thickness and boundary layer in uniform thickness are formed, is improved interface characteristics between high-K dielectric layer and fin
Energy；And when being annealed, the boundary layer of formation is located between high-K dielectric layer and fin, and K high is situated between
Matter layer prevents newly formed boundary layer and air contact, so as to improve the stability of the boundary layer to be formed,
Further improve the interface performance between high-K dielectric layer and fin.Further, using the original of auto-dope
When sublayer depositing operation forms the high-K dielectric layer of oxygen-carrying ion, one layer of high K dielectric of oxygen-carrying ion is formed
The corresponding auto-dope oxonium ion of film layer, oxonium ion is in each layer of high K dielectric film layer of oxygen-carrying ion
Can be uniformly distributed, if the high K dielectric film layer of dried layer oxygen-carrying ion stacks the K high to form oxygen-carrying ion
Dielectric layer, thus the high-K dielectric layer thickness evenness of oxygen-carrying ion is higher, and oxygen-carrying ion K high
Oxonium ion is uniformly distributed in dielectric layer.
Further, during auto-dope atom layer deposition process, step S26 is carried out, repeats step S21-S25,
The high K dielectric film layer of some oxygen-carrying ions constitutes the high-K dielectric layer of oxygen-carrying ion, carries out step S26
Purpose be mainly to formed high K dielectric film layer carry out oxonium ion doping, prevent as foreign ion
Oxonium ion participates in high K dielectric film layer (HfO2) reaction so that oxonium ion is free in Hf-O keys
In space, to cause to be formed the doping concentration of the oxonium ion for keeping certain in high-K dielectric layer, it is easy to follow-up
Diffusion during annealing, and the step can also take the chlorine element remained in high K dielectric film layer out of.
Brief description of the drawings
Fig. 1~Fig. 5 is the structural representation of the forming process of one embodiment of the invention fin formula field effect transistor
Figure.
Specific embodiment
As background technology is sayed, the fin formula field effect transistor performance of existing formation still has to be hoisted, such as
The high-K gate dielectric layer of the fin formula field effect transistor that prior art is formed and the interface performance in fin interface face
It is excessively poor, and in order to improve interface performance, it is necessary in the fin before high-K gate dielectric layer is formed
Surface forms boundary layer.
Research finds that existing boundary layer is typically formed by oxidation technology or deposition, the material of boundary layer
It is GeO2But, the GeO that prior art is formed2Boundary layer is highly unstable, is very soluble in water,
Particularly expose and easily reacted with the steam in air when in atmosphere；And due to the structure of fin
Compare especially, forming the more difficult control of interfacial layer thickness, the uniformity of thickness also is difficult to ensure, and very
Hardly possible forms the GeO of lower thickness2Boundary layer.
Therefore, the invention provides a kind of forming method of fin formula field effect transistor, being formed, this is oxygen-containing
During the high-K dielectric layer of ion, can uniformly be mixed in the high-K dielectric layer for being formed using auto-dope technique
Miscellaneous oxonium ion, can subsequently cause that the oxonium ion in the high-K dielectric layer of oxygen-carrying ion is uniformly diffused into recessed
In the fin of trench bottom, oxonium ion reacts to form boundary layer with fin material, because oxonium ion is situated between in K high
Equally distributed in matter layer, thus during annealing, oxonium ion from the contact surface of high-K dielectric layer and fin not
Uniformly it is diffused into fin with position, the diffusion oxygen ion concentration of diverse location is identical on contact surface,
Thus oxonium ion is higher with the thickness evenness that diverse location fin material reacts the boundary layer to be formed, and
By controlling the content of oxonium ion in high-K dielectric layer, the thickness of the boundary layer to be formed can be controlled, so that
The method of the present invention can form thinner thickness and boundary layer in uniform thickness；And when being annealed,
The boundary layer of formation is located between high-K dielectric layer and fin, and high-K dielectric layer prevents newly formed boundary layer
With air contact, so as to improve the stability of the boundary layer to be formed.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only,
Schematic diagram can disobey general ratio and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of the invention.Additionally, the three of length, width and depth should be included in actual fabrication
Dimension space size.
The structural representation of the forming process of Fig. 1~Fig. 5 one embodiment of the invention fin formula field effect transistors.
With reference to Fig. 1, there is provided Semiconductor substrate 200, fin 201 is formed with the Semiconductor substrate 200,
The material of the fin is Ge, SiGe or III-V element；It is developed across the side wall of part fin 201 and top
The pseudo- grid 204 on portion surface；Form the dielectric layer 203 of the covering Semiconductor substrate, fin and pseudo- grid, institute
The surface for stating dielectric layer 203 flushes with the top surface of pseudo- grid 204.
The Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), the Semiconductor substrate
200 can also be germanium, germanium silicon, GaAs or germanium on insulator or other suitable materials, in this implementation
The material of the Semiconductor substrate 200 is silicon.
The surface of the Semiconductor substrate 200 is formed with the fin 201 of some projections, and the material of the fin is
Ge, SiGe or III-V element, to improve the fin formula field effect transistor channel region carrier being subsequently formed
Mobility, in one embodiment, when the material of Semiconductor substrate 200 is Ge, SiGe or III-V element
When, the fin 201 of material identical with Semiconductor substrate by etch semiconductor substrates, can be formed.At this
In the other embodiment of invention, the fin 201 is formed also by epitaxy technique.In the fin 201
Can be different doped with different types of foreign ion according to the type of the fin formula field effect transistor for being formed,
In the present embodiment, when fin formula field effect transistor to be formed is p-type fin formula field effect transistor, fin
Can be with doped N-type foreign ion in portion 201；When fin formula field effect transistor to be formed is N-type fin
During field-effect transistor, can be with doped p-type foreign ion in fin 201.Fin described in the present embodiment
Material be Ge.
The material of the pseudo- grid 204 is polysilicon, amorphous carbon.The pseudo- grid 204 are subsequently removed to be formed
Groove, forms metal gates in a groove.
In one embodiment, the forming process of the pseudo- grid 204 is：Form the covering Semiconductor substrate
200 and the pseudo- gate material layer of fin 201, the top surface of the surface higher than fin 201 of pseudo- gate material layer；
Planarize the surface of the pseudo- gate material layer；The part surface of pseudo- gate material layer after planarization is formed and covered
Film layer；Pseudo- gate material layer after being planarized described in the mask layer as mask etching, is developed across fin
Partial sidewall and top surface pseudo- grid 204.
In one embodiment, separation layer 202, the separation layer are also formed with the Semiconductor substrate 200
Less than the top surface of fin 201, the separation layer 202 is for the adjacent fin of electric isolation on 202 surface
Portion 201 and adjacent grid structure, the material of the separation layer 202 is silica, silicon nitride or nitrogen oxygen
SiClx, the material of separation layer 202 described in the present embodiment is silica.It is specific that separation layer 202 is formed
Process is：It is initially formed the spacer material layer of the covering Semiconductor substrate 200 and fin 201；Then
The spacer material layer is planarized using chemical mechanical milling tech, the top surface with fin 201 is to stop
Only layer；Then it is etched back to remove the part spacer material layer, forms separation layer 202, the separation layer
Top surface of 202 surface less than fin 201.
In one embodiment, it is also formed with side wall 205 in the both sides sidewall surfaces of the pseudo- grid 204.It is described
Side wall 205 can be single or multiple lift (>=2 layers) stacked structure.The material of the side wall 205 can be oxygen
SiClx, silicon nitride or silicon oxynitride.
After side wall 205 is formed, can also distinguish in the fin 201 of pseudo- grid 204 and the both sides of side wall 205
Form source region and drain region 206.
In the present embodiment, the source region and drain region 206 are stress source-drain area, the shape of the stress source-drain area
It is into process：With the fin that the pseudo- grid 204 and side wall 205 are mask etching puppet grid 204 both sides, shape
Into etching groove；Stress material layer is filled in etching groove, stress source-drain area is formed.
In one embodiment, the etching groove can be the etching groove of sigma shapes, be filled in etching groove
Stress material is SiGe.In another embodiment, the etching groove can be rectangular channel, be filled out in etching groove
The stress material for filling is carborundum.
In other embodiments of the invention, the source region and drain region 206 can be by ion implantation technologies
Formed, its forming process is：With the pseudo- grid 204 and side wall 205 as mask, using ion implanting work
Skill to pseudo- grid 204 and the fin impurity ion of the both sides of side wall 205, in pseudo- grid 204 and side wall 205
Source region and drain region 206 are formed in the fin 201 of both sides.
The foreign ion of the ion implanting injection is p type impurity ion or N-type impurity ion, the P
Type foreign ion is one or more in boron ion, gallium ion or indium ion；The N-type impurity ion
It is one or more in phosphonium ion, arsenic ion or antimony ion.
The material of the dielectric layer 203 is silica, silicon nitride or low-K dielectric material.
With reference to Fig. 2, the pseudo- grid 204 (with reference to figure) are removed, form groove 211；In the groove 211
Side wall and lower surface formed oxygen-carrying ion high-K dielectric layer 210.
The oxygen that the high-K dielectric layer 210 of the oxygen-carrying ion spreads for the follow-up fin to the bottom of groove 211
Ion provides oxygen source.The high-K dielectric layer 210 of the oxygen-carrying ion that this implementation is formed is film layer, using heavy
When product technique forms the high-K dielectric layer 210 of oxygen-carrying ion, can be using auto-dope technique in the height for being formed
Uniform doping oxonium ion in K dielectric layer, in can subsequently causing the high-K dielectric layer 210 of oxygen-carrying ion
Oxonium ion be uniformly diffused into the fin 201 of the bottom of groove 211, and react to be formed with fin material
Boundary layer, forms boundary layer, because oxonium ion is in high-K dielectric layer compared to oxidation technology or depositing operation
It is equally distributed in 210, thus follow-up when being annealed, oxonium ion is from high-K dielectric layer 210 and fin
The contact surface diverse location in portion 201 is uniformly diffused into fin 201, the diffusion of diverse location on contact surface
Oxygen ion concentration is identical, thus oxonium ion reacts the boundary layer to be formed with diverse location fin material
Thickness evenness is higher, and by controlling the content of oxonium ion in high-K dielectric layer, can control to be formed
Boundary layer thickness so that the method for the present invention can form thinner thickness and boundary layer in uniform thickness；
And in follow-up annealing, the boundary layer of formation is located between high-K dielectric layer 210 and fin 201,
High-K dielectric layer 210 prevents newly formed boundary layer and air contact, so as to improve the boundary layer to be formed
Stability.
The high-K dielectric layer 210 of the oxygen-carrying ion is formed using auto-dope depositing operation.The K high is situated between
The material of matter layer 210 is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、
SrTiO3Or BaSrTiO.In the present embodiment, the material of the high-K dielectric layer 210 is HfO2。
In the present embodiment, the formation process of the high-K dielectric layer 210 of the oxygen-carrying ion is the original of auto-dope
Sublayer depositing operation, the atom layer deposition process of auto-dope forms the process of the high-K dielectric layer of oxygen-carrying ion
Including (to form the HfO of oxygen-carrying ion2As a example by high-K dielectric layer 210)：Step S21, to deposit cavity
Hafnium source gas is passed through in room；Step S22, the first oxygen source gas are passed through to deposition chambers；Step S23, applies
Plus radio-frequency power, hafnium source gas, the first oxygen source gas are dissociated into plasma；Step S24 plasmas
Body deposits to form high K dielectric film layer；Step S25, after circulation carries out step S21-S24 at least 1-4 times,
Be passed through the second oxygen source gas, and second oxygen source gas that dissociate, to high K dielectric film layer doping oxygen from
The step of son；Step S26, repeats step S21-S25, the high K dielectric film of some oxygen-carrying ions
Layer constitutes the high-K dielectric layer of oxygen-carrying ion.In the above method, the purpose for carrying out step S26 is mainly right
Forming high K dielectric film layer carries out oxonium ion doping, prevents from participating in K high as the oxonium ion of foreign ion
Dielectric thin film layer (HfO2) reaction so that oxonium ion is free in the space of Hf-O keys, is easy to follow-up
Diffusion during annealing, and the step can also take the chlorine element remained in high K dielectric film layer out of.
It should be noted that when the high-K dielectric layer of other materials is formed, auto-dope ald work
The process of skill and formation HfO2High-K dielectric layer process is similar to, such as form Al2O3It is, in said process
Hafnium source gas replace with aluminum source gas accordingly, other step all sames.In brief, can be by K high
Other elements in dielectric layer material outside oxygen element are defined as the first element, carry out auto-dope atomic layer deposition
During product technique, above-mentioned hafnium source gas is replaced with into the source gas with the first element, such as high K dielectric
Layer material is Al2O3When, the first element be aluminium element, by above-mentioned hafnium source gas replace with aluminium unit
The source gas of element；For another example, high-K dielectric layer material is TiO2, the first element is titanium elements, will be above-mentioned
Hafnium source gas replace with the source gas with titanium elements；Such as, high-K dielectric layer material is HfZrO,
First element is hafnium element and zr element, and above-mentioned hafnium source gas is replaced with hafnium element and zr element
Source gas.Detailed process includes：Step S21, to being passed through the source gas with the first element in deposition chambers
Body；Step S22, the first oxygen source gas are passed through to deposition chambers；Step S23, applies radio-frequency power, will
Source gas, the first oxygen source gas with the first element are dissociated into plasma；Step S24 plasmas
Deposition forms high K dielectric film layer；Step S25, after circulation carries out step S21-S24 at least 1-4 times,
Be passed through the second oxygen source gas, and second oxygen source gas that dissociate, to high K dielectric film layer doping oxygen from
The step of son；Step S26, repeats step S21-S25, the high K dielectric film of some oxygen-carrying ions
Layer constitutes the high-K dielectric layer of oxygen-carrying ion.
In one embodiment, the atom layer deposition process of the auto-dope forms oxygen containing HfO2High K dielectric
During layer 210, hafnium source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm,
First oxygen source gas are H2O, the flow of the first oxygen source gas is 20~300sccm, and the second oxygen source gas are
O2Or O3, the flow of the second oxygen source gas is 30~200sccm, and deposition chambers pressure is 0.1 support to 8
Support, deposition chambers radio-frequency power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400 degrees Celsius,
Raising forms the uniformity of the thickness evenness of high-K dielectric layer 210 and the oxonium ion distribution of oxygen-carrying ion.
It should be noted that when forming the high-K dielectric layer 210 of the oxygen-carrying ion of other materials, technique ginseng
Number and the HfO for forming oxygen-carrying ion2The technological parameter of high-K dielectric layer 210 is similar to, only need to be by said process
In hafnium source gas replace with the source gas with the first element.Specially：It is described that there is first element
The flow of source gas is 60sccm to 500sccm, and the first oxygen source gas are H2O, the first oxygen source gas
Flow is 20~300sccm, and the second oxygen source gas are O2Or O3, the flow of the second oxygen source gas is 30~200
Sccm, deposition chambers pressure is 0.1 support to 8 supports, and deposition chambers radio-frequency power is 300 watts to 3000 watts,
Deposition chambers temperature is 250~400 degrees Celsius.
When forming the high-K dielectric layer 210 of oxygen-carrying ion using the atom layer deposition process of auto-dope, formed
The corresponding auto-dope oxonium ion of high K dielectric film layer of one layer of oxygen-carrying ion, oxonium ion is oxygen-containing in each layer
It is uniformly distributed in the high K dielectric film layer of ion, and oxonium ion is in free in high K dielectric film layer
State, if the high K dielectric film layer of dried layer oxygen-carrying ion stacks the high-K dielectric layer 210 to form oxygen-carrying ion,
Thus oxygen-carrying ion the thickness evenness of high-K dielectric layer 210 it is higher, and oxygen-carrying ion high K dielectric
Oxonium ion is uniformly distributed in layer 210 so that the oxygen of diverse location in the high-K dielectric layer 210 of oxygen-carrying ion
Ion concentration distribution is uniform, when thickness is annealed so that oxygen in the high-K dielectric layer 210 of oxygen-carrying ion from
Son can be diffused to uniformly in the fin 201 of bottom portion of groove.
The thickness of high-K dielectric layer 210 of the oxygen-carrying ion that the above method is formed is 5~30 angstroms, and research finds high
The thickness of boundary layer of the content of K dielectric layer 210 on being subsequently formed has directly influence, implements one
In example, the concentration of oxonium ion is in the high-K dielectric layer 210 of oxygen-carrying ion
1E12atom/cm3~1E16atom/cm3。
With reference to Fig. 3, cap rock 207 is formed on the surface of high-K dielectric layer 210 of the oxygen-carrying ion.
The material of the cap rock 207 is metal nitride.In one embodiment, the metal nitride
It is TiN or TaN, the one side of the cap rock 207 can be as a part for the metal gates being subsequently formed；
Another convenience, when being annealed, the TiN can also prevent in high-K dielectric layer 210 oxonium ion to
The direction diffusion on the surface of high-K dielectric layer 210.
The thickness of the cap rock 207 is 10~50 angstroms
In other examples, it is also possible to do not form cap rock 207, it is situated between in the K high for forming oxygen-carrying ion
Follow-up annealing steps are directly carried out after matter layer 210.
With reference to Fig. 4, the high-K dielectric layer 210 to the oxygen-carrying ion is annealed so that oxygen-carrying ion
High-K dielectric layer 210 in oxonium ion diffuse to the fin 201 of bottom portion of groove, and with fin material
Reaction forms boundary layer 209.
When being annealed, the oxonium ion in the high-K dielectric layer 210 of oxygen-carrying ion can spread and carry out groove
In the fin 201 of bottom, and react to form boundary layer 209 with fin material, due to the height of oxygen-carrying ion
The oxonium ion of K dielectric layer 210 is to be uniformly distributed, thus the oxygen in the high-K dielectric layer 210 of oxygen-carrying ion
Ion is uniformly diffused into the fin of the bottom of groove 211 from each position, and is reacted with fin material,
The uniformity that boundary layer 209 is thus formed between high-K dielectric layer 210 and fin 201 is higher.
In one embodiment, the temperature of the annealing process is 600~1200 degrees Celsius, can be taken the photograph for 600
Family name's degree, 700 degrees Celsius, 800 degrees Celsius, 900 degrees Celsius, 1000 degrees Celsius, 1100 degrees Celsius, 1200
Degree Celsius, annealing time is 30 seconds~60 minutes, and annealing atmosphere is atmosphere of inert gases, can be 30
Second, 1 minute, 5 minutes, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 55 points
Clock, 60 minutes, annealing atmosphere be atmosphere of inert gases, with cause oxygen-carrying ion high-K dielectric layer 210
Middle oxonium ion uniformly diffuses to the fin of bottom portion of groove from the contact surface of high-K dielectric layer 210 and fin 201
In portion, and reacted with fin material, form boundary layer in uniform thickness；And cause the K high of oxygen-carrying ion
The oxonium ion of dielectric layer 210 is wholly or largely diffused into fin 201, in reduction high-K dielectric layer 210
The residual of oxonium ion so that the property retention of high-K dielectric layer 210 is constant.
Oxonium ion in the high-K dielectric layer 210 of oxygen-carrying ion is diffused into after fin 201, remaining height
K dielectric layer 210 is still as the gate dielectric layer of metal gates.
In the present embodiment, the material of the fin 201 is Ge, and the material of the corresponding boundary layer for being formed is
GeO2, in other embodiments, when the fin 201 is other semi-conducting materials, the boundary layer of formation
Material be corresponding semi-conducting material oxide.
With reference to Fig. 5, after annealing, the metal gates 208 of filling groove are formed on the cap rock 207.
The material of the metal gates 208 is W, Al or Cu.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (13)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate is provided, fin is formed with the Semiconductor substrate, the material of the fin is Ge,
SiGe or III-V element；
It is developed across the pseudo- grid of part fin side wall and top surface；
Form the dielectric layer of the covering Semiconductor substrate, fin and pseudo- grid, surface and the puppet of the dielectric layer
The top surface of grid is flushed；
The pseudo- grid are removed, groove is formed；
The high-K dielectric layer of oxygen-carrying ion is formed in the side wall and lower surface of the groove；
High-K dielectric layer to the oxygen-carrying ion is annealed so that in the high-K dielectric layer of oxygen-carrying ion
Oxonium ion is diffused in the fin of bottom portion of groove, and oxonium ion reacts to form boundary layer with fin material；
After annealing, the metal gates of filling groove are formed in the high-K dielectric layer.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that using from
Doping depositing operation forms the high-K dielectric layer of the oxygen-carrying ion.
3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that described to contain
The formation process of the high-K dielectric layer of oxonium ion is the atom layer deposition process of auto-dope.
4. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the height
The material of K dielectric layer is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、
Al2O3、SrTiO3Or BaSrTiO.
5. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the height
K dielectric layer material HfO2, the high-K dielectric layer of the atom layer deposition process formation oxygen-carrying ion of auto-dope
Process include：Step S21, to being passed through hafnium source gas in deposition chambers；Step S22, to deposit cavity
Room is passed through the first oxygen source gas；Step S23, applies radio-frequency power, by hafnium source gas, the first oxygen source
Gas is dissociated into plasma；Step S24 is plasma-deposited to form high K dielectric film layer；Step
S25, after circulation carries out step S21-S24 at least 1-4 times, carries out being passed through the second oxygen source gas, and solve
From the second oxygen source gas, to high K dielectric film layer adulterate oxonium ion the step of；Step S26, repeats
Step S21-S25 is carried out, the high K dielectric film layer of some oxygen-carrying ions constitutes the K high of oxygen-carrying ion
Dielectric layer.
6. the forming method of fin formula field effect transistor as claimed in claim 5, it is characterised in that the hafnium
Source gas is HfCl4, the flow of hafnium source gas is 60sccm to 500sccm, and the first oxygen source gas are
H2O, the flow of the first oxygen source gas is 20~300sccm, and the second oxygen source gas are O2Or O3, the
The flow of two oxygen source gas is 30~200sccm, and deposition chambers pressure is 0.1 support to 8 supports, deposit cavity
Room radio-frequency power is 300 watts to 3000 watts, and deposition chambers temperature is 250~400 degrees Celsius.
7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described to contain
The concentration of oxonium ion is 1E12atom/cm in the high-K dielectric layer of oxonium ion3~1E16atom/cm3, contain
The thickness of the high-K dielectric layer of oxonium ion is 5~30 angstroms.
8. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that moved back
600~1200 degrees Celsius when fiery, annealing time is 30 seconds~60 minutes, and annealing atmosphere is indifferent gas
Body atmosphere 60 minutes, annealing atmosphere is atmosphere of inert gases, and annealing atmosphere is inertia.
9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the puppet
Source region and drain region are also formed with the fin of grid both sides.
10. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include：
Before the anneal, cap rock is formed on the high-K dielectric layer surface of oxygen-carrying ion.
The forming method of 11. fin formula field effect transistors as claimed in claim 10, it is characterised in that the lid
Layer is metal nitride.
The forming method of 12. fin formula field effect transistors as claimed in claim 11, it is characterised in that the gold
Category nitride is TiN or TaN.
The forming method of 13. fin formula field effect transistors as claimed in claim 11, it is characterised in that the lid
The thickness of layer is 10~50 angstroms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906921.9A CN106856172B (en) | 2015-12-09 | 2015-12-09 | Method for forming fin field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906921.9A CN106856172B (en) | 2015-12-09 | 2015-12-09 | Method for forming fin field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106856172A true CN106856172A (en) | 2017-06-16 |
| CN106856172B CN106856172B (en) | 2019-12-31 |
Family
ID=59132493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510906921.9A Active CN106856172B (en) | 2015-12-09 | 2015-12-09 | Method for forming fin field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106856172B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300790A (en) * | 2017-07-24 | 2019-02-01 | 格芯公司 | With the contact etch stop layer for sacrificing polysilicon layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378156A (en) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Multi-gate devices with replaced-channels and methods for forming the same |
| CN104103509A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interfacial layer and formation method of metal gate transistor |
| CN104835743A (en) * | 2014-02-10 | 2015-08-12 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
-
2015
- 2015-12-09 CN CN201510906921.9A patent/CN106856172B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378156A (en) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Multi-gate devices with replaced-channels and methods for forming the same |
| CN104103509A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interfacial layer and formation method of metal gate transistor |
| CN104835743A (en) * | 2014-02-10 | 2015-08-12 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109300790A (en) * | 2017-07-24 | 2019-02-01 | 格芯公司 | With the contact etch stop layer for sacrificing polysilicon layer |
| CN109300790B (en) * | 2017-07-24 | 2021-11-02 | 格芯(美国)集成电路科技有限公司 | Contact etch stop layer with sacrificial polysilicon layer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106856172B (en) | 2019-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103311247B (en) | Semiconductor device and method for manufacturing the same | |
| CN106684144B (en) | The manufacturing method of semiconductor structure | |
| JP6218384B2 (en) | Manufacturing method of semiconductor device having tungsten gate electrode | |
| KR101282343B1 (en) | Semiconductor device with metal gate and method for manufacturing the same | |
| CN105225937B (en) | The forming method of semiconductor devices | |
| JP5535706B2 (en) | Manufacturing method of semiconductor device | |
| CN108807380A (en) | Semiconductor structure and the method for forming integrated circuit structure | |
| CN107591362B (en) | Semiconductor structure and forming method thereof | |
| US20150132938A1 (en) | Methods and Systems for Forming Reliable Gate Stack on Semiconductors | |
| US11387149B2 (en) | Semiconductor device and method for forming gate structure thereof | |
| CN106653844A (en) | Fin field effect transistor and forming method thereof | |
| TWI749798B (en) | Semiconductor devices and methods for forming the same | |
| CN107346783A (en) | Semiconductor structure and its manufacture method | |
| CN104103509A (en) | Formation method of interfacial layer and formation method of metal gate transistor | |
| CN108122742A (en) | The manufacturing method of semiconductor device structure | |
| US20230378310A1 (en) | Negative-Capacitance and Ferroelectric Field-Effect Transistor (NCFET and FE-FET) Devices | |
| CN107481932B (en) | Method for manufacturing semiconductor structure | |
| CN102157553B (en) | Structure of asymmetric semiconductor and forming method thereof | |
| CN106847695A (en) | The forming method of fin field effect pipe | |
| CN106783742B (en) | The forming method of fin formula field effect transistor | |
| CN106856172A (en) | The forming method of fin formula field effect transistor | |
| CN107591367A (en) | The manufacture method of semiconductor structure | |
| CN107293489A (en) | Improve the method for fin field effect pipe performance | |
| CN107919323A (en) | Semiconductor structure and forming method thereof | |
| CN109979820A (en) | The forming method of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |