CN106849647A - Synchronous buck type DC-DC converter and its method - Google Patents
Synchronous buck type DC-DC converter and its method Download PDFInfo
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- CN106849647A CN106849647A CN201510887884.1A CN201510887884A CN106849647A CN 106849647 A CN106849647 A CN 106849647A CN 201510887884 A CN201510887884 A CN 201510887884A CN 106849647 A CN106849647 A CN 106849647A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/1555—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only for the generation of a regulated current to a load whose impedance is substantially inductive
Abstract
A kind of synchronous buck type DC-DC converter and its method, the synchronous buck DC-DC converter include a signal output part, an output-stage circuit, a first comparator, a latch unit, a control logic circuit, one drive circuit and an ON time control circuit.Output-stage circuit connects signal output part, and provides output voltage to signal output part according to input voltage.First comparator receives the feedback voltage signal and reference voltage signal and output control voltage signal for being relevant to output voltage.Latch unit receives control voltage signal and timing signal and exports conducting and enables signal.Control logic circuit receives conducting and enables signal and export conductivity control signal.Discharge and recharge time of the drive circuit according to conductivity control signal controlled output level circuit.ON time control circuit receives conductivity control signal and input voltage and exports timing signal.Wherein, timing signal is relevant to the dutycycle of output-stage circuit.The invention also discloses its conversion method.
Description
Technical field
The present invention relates to a kind of direct current to direct current (DC-DC) converter, particularly a kind of synchronous buck type is straight
Stream is to direct current transducer and its method.
Background technology
In field of power management, synchronous buck type direct current has various control mould to direct current (DC-DC) converter
Formula.When using constant on-time control model, DC-DC converter can be directly by output voltage
Ripple control, it is not necessary to special pulse width modulation (Pulse Width Modulation, PWM)
Signal generating circuit, it is not required that loop compensation networks, greatly simplifies using dc-dc
The structure of power-supply system, improves transient state of the power-supply system in the case of the load of wide scope and output capacitance and returns
Should, while also improving the reliability of power-supply system.
In the canonical topology of the synchronous buck type dc-dc of traditional constant on-time control model
In structure, generally output voltage is compared to produce as threshold voltage and timer electric capacity both end voltage
Timing signal, then controls the ON time of power transistor according to timing signal and control voltage signal, from
And regulated output voltage.
In existing constant on-time control technology, due to the influence of power transistor itself conducting resistance, work(
The switch periods of rate transistor also with load current change, have impact on dc-dc working condition and
Performance, limits the application of dc-dc.
The content of the invention
The technical problems to be solved by the invention are directed to the drawbacks described above of prior art, there is provided a kind of synchronous drop
Die mould direct current is to direct current (DC-DC) converter and its method.
To achieve these goals, the invention provides a kind of synchronous buck DC-DC converter, its bag
Include a signal output part, an output-stage circuit, a first comparator, a latch unit, a control logic circuit,
One drive circuit and ON time control circuit.Output-stage circuit connects signal output part, and according to defeated
Enter voltage and output voltage to signal output part is provided.First comparator receives the feedback electricity for being relevant to output voltage
Pressure signal and reference voltage signal and output control voltage signal.Latch unit receives control voltage signal and timing
Signal simultaneously exports conducting enable signal.Control logic circuit receives conducting and enables signal and export conducting control letter
Number.Discharge and recharge time of the drive circuit according to conductivity control signal controlled output level circuit.ON time is controlled
Circuit receives conductivity control signal and input voltage and exports timing signal.Wherein, timing signal is relevant to defeated
Go out the dutycycle of grade circuit.
In order to above-mentioned purpose is better achieved, direct current is changed present invention also offers a kind of synchronous buck direct current
Method, it includes：Inductance is carried out discharge and recharge to provide output based on input voltage using first switch circuit
Voltage, the switch of first switch circuit is controlled according to conductivity control signal, is compared and is relevant to the anti-of output voltage
Feedthrough voltage signal and reference voltage signal control control voltage signal with terms of to produce control voltage signal, breech lock
When signal with export conducting enable signal, logical process conducting enable signal with export conductivity control signal, with
And timing signal is produced according to conductivity control signal and input voltage.Wherein, timing signal is relevant to first and opens
The dutycycle on powered-down road.
The technical effects of the invention are that：
Synchronous buck type dc-dc of the invention and its method can make switch periods not with load
Curent change, and then improve the performance of converter and expand the range of application of converter.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as to of the invention
Limit.
Brief description of the drawings
Fig. 1 is the synchronous buck type direct current of constant on-time control model to direct current (DC-DC) converter
Structural representation；
Fig. 2 is the structural representation of the synchronous buck type dc-dc of one embodiment of the invention；
Fig. 3 is the circuit diagram of an embodiment of the threshold voltage generation circuit in Fig. 2；
Fig. 4 is the circuit diagram of another embodiment of the threshold voltage generation circuit in Fig. 2；
Fig. 5 is the circuit diagram of an embodiment of the timer circuit in Fig. 2；
Fig. 6 is the timing diagram of coherent signal in Fig. 2,3 and 5.
Wherein, reference
1 timer circuit
2 first comparators
3 latch units
4 control logic circuits
5 drive circuits
6 output-stage circuits
601 first switch circuits
7 feedback circuits
1 ' ON time controls circuit
101 timer circuits
102 threshold voltage generation circuits
VIN/R charging current signals
Vout output voltages
Tout timing signals
VREF reference voltage signals
VFB feedback voltage signals
PUMP control voltage signals
S sets end
R resets end
Q output ends
TON turns on enable signal
HSON conductivity control signals
LSON conductivity control signals
DRVH grid control signals
DRVL grid control signals
VIN input voltages
GND ground terminals
MP1 p-type MOS transistors
MN1 N-type MOS transistors
SW contacts
L inductance
CL electric capacity
RL load resistances
The feedback resistances of RF1 first
The feedback resistances of RF2 second
D*VIN*k threshold voltage signals
R11 charging circuits
F12 low pass filters
R12 resistance
R14 resistance
R16 resistance
C12 electric capacity
INV12 not gates
OR12 OR gates
MP12 PMOS transistors
MN12 nmos pass transistors
MN14 nmos pass transistors
SVIN contacts
The comparators of P11 second
C11 electric capacity
K11 switch elements
VA terminal voltages
VIN/R charging current signals
Specific embodiment
Structural principle of the invention and operation principle are described in detail below in conjunction with the accompanying drawings：
Fig. 1 is the synchronous buck type direct current of constant on-time control model to direct current (DC-DC) converter
Structural representation.The synchronous buck type dc-dc of constant on-time control model includes：Meter
When device circuit 1, first comparator 2, latch unit 3, control logic circuit 4, drive circuit 5, output stage
Circuit 6 and feedback circuit 7.
The first input end of timer circuit 1 connects power end (it is used to provide input voltage VIN), and
And the second input of timer circuit 1 connects signal output part (it is used to provide output voltage Vout).
The output end of timer circuit 1 connects the replacement end R of latch unit 3.The positive input terminal of first comparator 2 is defeated
Enter reference voltage signal VREF, and the negative input end of first comparator 2 connects the feedback of feedback circuit 7
End.The output end of first comparator 2 connects the setting end S of latch unit.The output end Q connections of latch unit 3
The input of control logic circuit 4.The of the first output end connection drive circuit 5 of control logic circuit 4
One input, and control logic circuit 4 the second output end connect drive circuit 5 the second input.
First output end of drive circuit 5 connects the first control end of output-stage circuit 6, and drive circuit 5
The second output end connect output-stage circuit 6 the second control end.The input connection electricity of output-stage circuit 6
Source, and the output end of output-stage circuit 6 connection signal output part.Feedback circuit 7 is connected to signal output
Between end and ground terminal GND.
Wherein, output-stage circuit 6 include on-off circuit (hereinafter referred to as first switch circuit 601) and
Inductance L.Input (that is, the input of output-stage circuit 6) the connection power supply of first switch circuit 601
End, and the output end connection inductance L of first switch circuit 601 first end.Second end of inductance L
It is the output end of output-stage circuit 6, and its connection signal output part.First control of first switch circuit 601
End (that is, the first control end of output-stage circuit 6) processed receives the grid control signal for carrying out driving circuit 5
DRVH, and second control end (that is, the second control end of output-stage circuit 6) of first switch circuit 601
Receive the grid control signal DRVL for carrying out driving circuit 5.First switch circuit 601 is according to grid control
The discharge and recharge time of signal DRVH and grid control signal DRVL control electric currents (inductance L), and then
The output end of output-stage circuit 6 can export a VD Vout for stabilization.
Timer circuit 1 exports periodic timing signal according to input voltage VIN and output voltage Vout
Tout.The output control voltage signal PUMP of first comparator 2, and this control voltage signal PUMP
It is the digital signal produced more afterwards between feedback voltage signal VFB and reference voltage signal VREF.Door bolt
The lock breech lock control voltage signal PUMP of device 3 and timing signal Tout, and first switch circuit is exported according to this
Conducting enable signal TON.Control logic circuit 4 receives the conducting enable signal of the output of latch unit 3
TON, exports the conductivity control signal HSON and conducting control letter of first switch circuit after logical process
Number LSON.The first input end of drive circuit 5 receives conductivity control signal HSON, and drive circuit
5 the second input receives conductivity control signal LSON.Drive circuit 5 is according to conductivity control signal HSON
Grid control signal DRVH corresponding with conductivity control signal LSON generations and grid control signal
DRVL.The first output end output grid control signal DRVH of drive circuit 5, and drive circuit 5
Second output end output grid control signal DRVL.
In certain embodiments, output-stage circuit 6 also includes electric capacity CL.Second end of inductance L is also connected with
The first end of electric capacity CL, and second end of electric capacity CL then connects ground terminal GND.In this, inductance L
It is the output end of output-stage circuit 6 with the connection end of electric capacity CL, and its connection signal output part.Inductance L
LC smoothing circuits are constituted with electric capacity CL, to provide the output voltage Vout of advection.
In certain embodiments, first switch circuit 601 includes PMOS (P-channel Metal Oxide
Semiconductor, p-type gold oxygen half) transistor MP1 and NMOS (N-channel Metal Oxide
Semiconductor, N-type gold oxygen half) transistor MN1.The grid (first of PMOS transistor MP1
First control end of on-off circuit 601) connection drive circuit 5 the first output end, and PMOS crystal
Source electrode (input of first switch circuit 601) the connection power end of pipe MP1.Nmos pass transistor
Second output of grid (the second control end of first switch circuit 601) the connection drive circuit 5 of MN1
End, and the source electrode of nmos pass transistor MN1 connection ground terminal GND.The drain electrode of PMOS transistor MP1,
The drain electrode of nmos pass transistor MN1 is commonly connected to contact SW (first switches with the first end of inductance L
The output end of circuit 601).In other words, PMOS transistor MP1 be connected to power end and inductance L it
Between, and it is used for providing a charging current path.Nmos pass transistor MN1 be connected to ground terminal GND and
Between inductance L, and it is used for providing a discharge current path.
In this, control logic circuit 4 receives the conducting enable signal TON of the output of latch unit 3, through logic
The conductivity control signal HSON and nmos pass transistor MN1 of PMOS transistor MP1 are exported after treatment
Conductivity control signal LSON.Drive circuit 5 is according to conductivity control signal HSON and conductivity control signal
LSON produces corresponding grid control signal DRVH and grid control signal DRVL respectively.PMOS
Transistor MP1 grid input grid control signal DRVH, and nmos pass transistor MN1 grid
Pole is input into grid control signal DRVL.Input voltage VIN is connected to section by PMOS transistor MP1
Point SW, and nmos pass transistor MN1 is connected between node SW and ground terminal GND.Inductance L
It is connected between node SW and output voltage Vout.
When PMOS transistor MP1 opens (ON), input voltage VIN passes through PMOS transistor
MP1 is connected to the first end of inductance L, so that input voltage VIN passes through PMOS transistor MP to electricity
Sense L is charged.When nmos pass transistor MN1 is opened, inductance L is via nmos pass transistor
MN1 is conducted to ground terminal GMND, so that inductance L is discharged.Therefore, through regulation PMOS crystal
When the ON time of pipe MP1 and nmos pass transistor MN1 carrys out the discharge and recharge of control electric current (inductance L)
Between, and then output-stage circuit 6 can export a VD Vout for stabilization.
During implementing, above-mentioned synchronous buck type dc-dc is defeated by timer circuit 1
Go out periodic timing signal Tout, and carry out controlling switch electricity with control voltage signal PUMP collective effects
The switch (ON/OFF turns on and disconnect) on road.For the input voltage VIN and output voltage that give
Vout, the time of conducting enable signal TON is constant (that is, ON time is constant).Due to PMOS
The influence of the conduction impedance of transistor MP1 and nmos pass transistor MN1, under different load currents,
Maintaining the dutycycle of constant output voltage Vout, on-off circuit 601 can change.Therefore, electricity is switched
The switch periods Tsw on road 601 changes with the load current of signal output part.Generally load is bigger,
Required dutycycle is higher, but ON time is constant, so switch periods Tsw can reduce, switching frequency
Can improve.
In other words, in above-mentioned synchronous buck type dc-dc, due to input voltage VIN and defeated
It is changeless to go out voltage Vout, therefore (that is, is loaded when the amount of load or its required magnitude of current change
Electric current changes) when, backfeed loop (feedback loop) can adjust dutycycle D and meet negative providing
Carry the new dutycycle D ' of curent change.However, Ton time-count cycle of timing signal Tout is to immobilize
But dutycycle has changed into D ', therefore the switch periods Tsw of switching signal then needs to change a little to meet this
Change, reaches new steady s tate (1/Tsw=Ton*D ') whereby.The switch periods Tsw of switching signal
Change with the load current of signal output part, therefore PMOS transistor MP1 and nmos pass transistor
The frequency (switching frequency) of MN1 conductings also changes therewith.
In certain embodiments, feedback circuit 7 can realize that it is used to carry out output voltage with bleeder circuit
Voltage division processing produces feedback voltage signal VFB.In this, feedback circuit 7 includes the first feedback resistance RF1
With the second feedback resistance RF2.One end of first feedback resistance RF1 and one end of the second feedback resistance RF2
Series connection.The output end and signal output part of the other end connection output-stage circuit 6 of the first feedback resistance RF1,
And the other end connection ground terminal GND of the second feedback resistance RF2.The feedbacks of first feedback resistance RF1 and second
The connection end (dividing point) of resistance RF2 is the feedback end of feedback circuit 7, and its connection first comparator 2
Negative input end.
In certain embodiments, feedback circuit 7 can also feed back cabling realization (schema is not shown).Feedback is walked
The output end and signal output part of one end connection output-stage circuit 6 of line.It is feedback to feed back the other end of cabling
The feedback end of circuit 7, and it connects the negative input end of first comparator 2.
Fig. 2 is the structural representation of the synchronous buck type dc-dc of one embodiment of the invention.Reference
Fig. 2, this synchronous buck type dc-dc can provide constant switch periods Tsw.In this embodiment
In, synchronous buck type synchronous buck type dc-dc includes：ON time control circuit 1 ', first
Comparator 2, latch unit 3, control logic circuit 4, drive circuit 5, output-stage circuit 6 and feedback electricity
Road 7.In this, first comparator 2, latch unit 3, control logic circuit 4, drive circuit 5, output stage
The structure of circuit 6 and feedback circuit 7 is generally same as previous embodiment with running.
Wherein, the first output end of control logic circuit 4 is also connected with the first defeated of ON time control circuit 1 '
Enter end, and the second output end of control logic circuit 4 is also connected with the second defeated of ON time control circuit 1 '
Enter end.ON time control circuit 1 ' receives conductivity control signal HSON, LSON, and is controlled according to conducting
Signal HSON, LSON processed and input voltage VIN produce timing signal Tout.In this, timing signal
The time delay of Tout changes and respective change with the load current of signal output part.
In certain embodiments, ON time control circuit 1 ' is produced including timer circuit 101 and threshold voltage
Raw circuit 102.The first of the first input end connection control logic circuit 4 of threshold voltage generation circuit 102
Output end, and the second input input control logic circuit 4 of threshold voltage generation circuit 102 second
Output end.Second input of the output end connection timer circuit 101 of threshold voltage generation circuit 102.
The first input end connection input voltage VIN of timer circuit 101, and the output end of timer circuit 101
Connect the replacement end R of latch unit 3.
Second input of timer circuit 101 receives the threshold value as produced by threshold voltage generation circuit 102
(that is, threshold voltage signal D*VIN*k is dutycycle D and input voltage VIN to voltage signal D*VIN*k
K times of product).In this, threshold voltage generation circuit 102 receives conductivity control signal HSON, LSON,
And switching signal (the grid with first switch circuit 601 are produced according to conductivity control signal HSON, LSON
Pole control signal DRVH, DRVL) the threshold voltage signal D*VIN*k that are directly proportional of dutycycle D.
Timer circuit 101 is according to input voltage VIN and threshold voltage signal D*VIN*k outputs periodically meter
When signal Tout, and timing signal Tout can also be directly proportional to dutycycle D.In other words, when signal is defeated
When the load current for going out end changes, dutycycle D changes therewith, and threshold voltage signal D*VIN*k is also therewith
Change, and then Ton time-count cycle of timing signal Tout is also directly proportional to dutycycle D.
Ton time-count cycle of timing signal Tout can be obtained by simple operation：
VIN/R*Ton=C*D*VIN*k, i.e. Ton=C*R*D*k.Wherein, R is in timer circuit 101
The resistance value of charging circuit, and C is the capacitance of electric capacity C11.In this, it is assumed that proportionality factor is K,
Time-count cycle, the relational expression of Ton and dutycycle D was Ton=K*D, due to switch periods Tsw and timing
The relation of cycle T on is Tsw=Ton/D, it may thus be appreciated that switch periods Tsw is constantly equal to K.In other words,
The switch periods Tsw of synchronous buck type dc-dc is unrelated with dutycycle D, i.e., not with load current
And change, realize the constant of switch periods Tsw.The synchronous buck type DC-DC of constant switch periods Tsw
Converter increases on the architecture basics of the synchronous buck type dc-dc of constant on-time control model
Plus threshold voltage generation circuit 102, and produced by threshold voltage generation circuit 102 with dutycycle D into
The threshold voltage signal D*VIN*k of direct ratio, to cause when load current changes, makes switch periods Tsw
It is constant.
In this, load current change refers to change in the loading range of dc-dc.Furtherly,
In the case where constant pressure (output voltage Vout) is exported, if load resistance RL is smaller, load current
(Vout/RL) then than larger；, whereas if load resistance RL is than larger, load current Vout/RL
It is then smaller；Also, herein load current change be within the specific limits for.
In this, k is changeless value, and it can be designed in response to actual demand.
Fig. 3 is the circuit diagram of an embodiment of the threshold voltage generation circuit 102 in Fig. 2.At some
In embodiment, reference picture 3, threshold voltage generation circuit 102 includes on-off circuit (hereinafter referred to as second switch
Circuit), low pass filter F12 and not gate INV12.Wherein, second switch circuit includes PMOS
Transistor MP12 and nmos pass transistor MN12.
The input of not gate INV12 connects the first output end of control logic circuit 4.PMOS transistor
The grid of MP12 connects the output end of not gate INV12, and the source electrode of PMOS transistor MP12 connects
Connect power end.The drain electrode of the drain electrode connection nmos pass transistor MN12 of PMOS transistor MP12, and
And the drain electrode of PMOS transistor MP12 is also connected with the input of low pass filter F12.NMOS crystal
The grid of pipe MN12 connects the second output end of control logic circuit 4, and nmos pass transistor MN12
Source electrode connection ground terminal GND.The drain electrode of PMOS transistor MP12 and nmos pass transistor MN12
Drain electrode be connected contact SVIN jointly with the input of low pass filter F12.Low pass filter F12's is defeated
Go out to hold the second input of connection timer circuit 101.
The input of not gate INV12 receives the conductivity control signal HSON of PMOS transistor MP1.
The grid of nmos pass transistor MN12 receives the conductivity control signal LSON of nmos pass transistor MN1.
In other words, in threshold voltage generation circuit 102, the grid of PMOS transistor MP12 receives PMOS
The inversion signal of the conductivity control signal HSON of transistor MP1, the grid of nmos pass transistor MN12
The conductivity control signal LSON of nmos pass transistor MN1 is received, thus makes PMOS transistor MP12
Turned on nmos pass transistor MN12 property performance period and disconnected.
For example, when it is 0 that conductivity control signal HSON is 1 and conductivity control signal LSON,
PMOS transistor MP12 is turned on and nmos pass transistor MN12 disconnects；Now, input voltage VIN
Output end (the timer circuit 101 of threshold voltage generation circuit 102 is connected to by low pass filter F12
The second input).Conversely, when conductivity control signal HSON is 0 and conductivity control signal LSON
For 1 when, PMOS transistor MP12 disconnect and nmos pass transistor MN12 turn on；Now, low pass
The input of wave filter F12 is connected to ground terminal GND.In each switch periods Tsw, PMOS crystal
The ON time of pipe MP12 is Ton, and the ON time of nmos pass transistor MN12 is Toff.It is false
If D is dutycycle, i.e. D=Ton/Tsw.In other words, PMOS transistor MP12 and NMOS is brilliant
Body pipe MN12 is sampled with dutycycle D to input voltage VIN, and is taken via contact SVIN outputs
Input voltage after sample gives low pass filter F12.Low pass filter F12 is by the input voltage VIN after sampling
In the zero-decrement output end for being delivered to threshold voltage generation circuit 102 of DC component, and in threshold voltage
The output end of circuit 102 is produced to obtain direct current threshold voltage signal D*VIN*k.In this embodiment, k=1,
That is threshold voltage signal D*VIN*k is the product of dutycycle D and input voltage VIN.
In certain embodiments, low pass filter F12 includes resistance R12 and electric capacity C12.Resistance R12
First end connection PMOS transistor MP12 drain electrode, and be also connected to nmos pass transistor MN12
Drain electrode.That is, the first end connection contact SVIN of resistance R12.The second end connection electric capacity of resistance R12
The first end of C12, and it is also connected to the second input of timer circuit 101.Second end of electric capacity C12
Connection ground terminal GND.
Fig. 4 is the circuit diagram of another embodiment of the threshold voltage generation circuit 102 in Fig. 2.Another
In some embodiments, reference picture 4, threshold voltage generation circuit 102 includes on-off circuit (hereinafter referred to as second
On-off circuit), ratio circuit, low pass filter F12 and not gate INV12.Wherein, second switch electricity
Road includes PMOS transistor MP12 and nmos pass transistor MN12.Ratio circuit includes two resistance
R14, R16, nmos pass transistor MN14 and OR gate OR12.
The input of not gate INV12 connects the first output end of control logic circuit 4.PMOS transistor
The grid of MP12 connects the output end of not gate INV12, and the source electrode of PMOS transistor MP12 connects
Connect power end.The drain electrode of the drain electrode connection nmos pass transistor MN12 of PMOS transistor MP12, and
And the drain electrode of PMOS transistor MP12 is also connected with the input of low pass filter F12.NMOS crystal
The grid of pipe MN12 connects the second output end of control logic circuit 4, and nmos pass transistor MN12
Source electrode connection ground terminal GND.The drain electrode of PMOS transistor MP12 and nmos pass transistor MN12
Drain electrode be connected contact SVIN jointly with the first end of resistance R14.The second end connection resistance of resistance R14
The first end of R16 and the input of low pass filter F12.The output end connection timing of low pass filter F12
Second input of device circuit 101.Second end of resistance R16 connects the leakage of nmos pass transistor MN14
Pole.The source electrode connection ground terminal GND of nmos pass transistor MN14.The two inputs difference of OR gate OR12
Connect first output end and the second output end of logic circuit 4.The output end connection NMOS of OR gate OR12
The grid of transistor MN14.
The input of not gate INV12 receives the conductivity control signal HSON of PMOS transistor MP1.
The grid of nmos pass transistor MN12 receives the conductivity control signal LSON of nmos pass transistor MN1.
In other words, in threshold voltage generation circuit 102, the grid of PMOS transistor MP12 receives PMOS
The inversion signal of the conductivity control signal HSON of transistor MP1, the grid of nmos pass transistor MN12
The conductivity control signal LSON of nmos pass transistor MN1 is received, thus makes PMOS transistor MP12
Turned on nmos pass transistor MN12 property performance period and disconnected, input voltage VIN is taken whereby
Sample.
In each switch periods Tsw, the ON time of PMOS transistor MP12 is Ton, and NMOS
The ON time of transistor MN12 is Toff.Assuming that D is dutycycle, i.e. D=Ton/Tsw.In other words,
PMOS transistor MP12 is carried out with dutycycle D with nmos pass transistor MN12 to input voltage VIN
Sample and provide the input voltage VIN after sampling via contact SVIN.Ratio circuit is by the input after sampling
Voltage VIN carries out ratio adjustment with scale factor k.The low pass of resistor R12 and capacitor C12 compositions
Wave filter F12 ratio is adjusted after input voltage VIN * k in DC component be delivered to threshold undampedly
Threshold voltage produces the output end of circuit 102, and the output end in threshold voltage generation circuit 102 obtains direct current
Threshold voltage signal D*VIN*k.In this embodiment, k=R14/ (R14+R16).
Fig. 5 is the circuit diagram of an embodiment of the timer circuit 101 in Fig. 2.In some embodiments
In, reference picture 5, timer circuit 101 includes the second comparator P11, charging circuit R11, electric capacity C11
And switch element K11.
Negative input end connection threshold voltage generation circuit 102 (the low pass filter F12 of the second comparator P11
Output end).The output end of the second comparator P11 connects the replacement end R of latch unit 3, and is also connected with
To the control end of switch element K11.The positive input terminal of the second comparator P11, the first end of electric capacity C11,
The first end of switch element K11 is connected contact A jointly with the output end of charging circuit R11.Charging circuit
The output end connection power end of R11.Second end of electric capacity C11 is connected with second end of switch element K11
Ground terminal GND.In other words, switch element K11 is in parallel with electric capacity C11.
In timer circuit 101, charging circuit R11 receives input voltage VIN and by input voltage VIN
Charging current signal VIN/R is converted into, electric capacity C11 is charged with charging current signal VIN/R then.
Second comparator P11 believes the terminal voltage (VA) (voltage of contact A) of electric capacity C11 and threshold voltage
Number D*VIN*k is compared to export timing signal Tout, and using this timing signal Tout as feedback
Signal carrys out the switch of controlling switch element K11, and then produces periodic timing signal Tout.Wherein,
Ton time-count cycle of this timing signal Tout can be represented with following formula 1.
Formula 1
Furtherly, in initial period, the terminal voltage VA of electric capacity C11 is zero, now timing signal Tout
For low level and turn off switch element K11, and charging current signal VIN/R is then to electric capacity C11
Charge, to cause terminal voltage VA to gradually rise.When the terminal voltage VA of electric capacity C11 believes more than threshold voltage
During number D*VIN*k, the timing signal Tout of the second comparator P11 outputs is high levels, and this high levels
Timing signal Tout close switch element K11, and electric capacity C11 discharged, to cause end electricity
Pressure VA is reduced to 0.When terminal voltage VA is changed into 0, the timing signal Tout of the second comparator P11 outputs
Then it is changed into low level again, and charging current signal VIN/R charges to electric capacity C11 again.Through such
Loop, the second comparator P11 is exportable periodic timing signal Tout, and time-count cycle
Ton=D*R*C.Wherein, R is the resistance value of charging circuit R11, and C is the electric capacity of electric capacity C11
Value.
When synchronous buck type dc-dc normal work, load current allows to become within the specific limits
Change, in the ideal case, ignore the conducting resistance of transistor (on-off circuit), and dutycycle D can be with
Following formula 2 is represented.
D=Vout/VIN formulas 2
Following formula 3 can obtain by formula 1 to formula 2.
Formula 3
Also, switch periods Tsw such as following formulas 4 can be derived from by formula 3.
Formula 4
From formula 4, switch periods Tsw is steady state value (k*R*C).
But in practice, due to transistor (on-off circuit) conducting resistance presence, thus cause actual
Dutycycle D changes with load current.Assuming that the conducting resistance of PMOS transistor MP1 is Rhs, NMOS
The conducting resistance of transistor MN1 is Rls and load current is Io, then actual dutycycle D such as following formulas 5.
Formula 5
In the synchronous buck type dc-dc of constant on-time control model, timer circuit 1
Ton time-count cycle of the timing signal Tout of output can be represented with following formula 6.
Formula 6
Ton time-count cycle of actual dutycycle D (formula 5) and formula 6 is substituted into the fortune of switch periods Tsw
In formula, following formula 7 can be obtained.
Formula 7
From equation 7 above, in practice, switch periods Tsw is changed with load current Io.
For the unstable problems of switch periods Tsw, in ON time control circuit 1 ', with threshold value electricity
Press signal D*VIN*k to replace output voltage Vout of the prior art, and then obtain Ton time-count cycle
Such as following formula 8.
Formula 8
Arithmetic expression further according to switch periods Tsw can obtain following formula 9.
Formula 9
From equation 9 above, switch periods Tsw is constant (kRC).
For example, Ton time-count cycle is changed, i.e. Ton=D*t as dutycycle D changes, its
Middle time t is pre-set and changeless.Now, switch periods Tsw=D/Ton=1/t.When negative
When the amount of load or its required magnitude of current change (that is, load current changes), backfeed loop (feedback
Loop dutycycle D) can be adjusted with provide meet load current change new dutycycle D '.Due to dutycycle
D ' is changed into by D, time-count cycle, Ton can also change over new Ton ' time-count cycle=D ' * t, and now
Switch periods can be represented with following formula：Tsw '=D '/Ton '=1/t.Therefore, no matter how dutycycle D changes,
Switch periods Tsw keeps constant.No matter that is, how the amount or its required magnitude of current of load change
Become, switch periods Tsw can keep constant.
Fig. 6 is the timing diagram of coherent signal in Fig. 2,3 and 5.Control voltage signal PUMP, terminal voltage
VA, timing signal Tout, conducting enable signal TON, conductivity control signal HSON, LSON and
The sequential relationship of grid control signal DRVH, DRVL is as shown in Figure 5.
In sum, synchronous buck type dc-dc of the invention and its method can make switch week
Phase does not change with load current, and then improves the performance of converter and expand the range of application of converter.
Certainly, the present invention can also have other various embodiments, in the feelings without departing substantially from spirit of the invention and its essence
Under condition, those of ordinary skill in the art work as can make various corresponding changes and deformation according to the present invention, but
These corresponding changes and deformation should all belong to the protection domain of appended claims of the invention.
Claims (17)
1. a kind of synchronous buck type DC-DC converter, it is characterised in that including：
One signal output part, exports an output voltage；
One output-stage circuit, connects the signal output part, and the output voltage is provided according to an input voltage；
One first comparator, receives a feedback voltage signal and a reference voltage signal and exports a control voltage
Signal, the wherein feedback voltage signal are relevant to the output voltage；
One latch unit, receives the control voltage signal with a timing signal and the conducting enable signal of output one；
One control logic circuit, receives the conducting and enables signal and export a conductivity control signal；
One drive circuit, the discharge and recharge time of the output-stage circuit is controlled according to the conductivity control signal；And
One ON time controls circuit, receives the conductivity control signal and the input voltage and exports timing letter
Number, wherein the timing signal is relevant to a dutycycle of the output-stage circuit.
2. synchronous buck type DC-DC converter as claimed in claim 1, it is characterised in that should
The time-count cycle of timing signal is proportional to the dutycycle.
3. synchronous buck type DC-DC converter as claimed in claim 1, it is characterised in that should
ON time control circuit includes：
One threshold voltage generation circuit, receives the conductivity control signal and exports a threshold voltage signal, wherein
The threshold voltage signal is proportional to the dutycycle；And
One timer circuit, receives the threshold voltage signal and the input voltage and exports the timing signal.
4. synchronous buck type DC-DC converter as claimed in claim 3, it is characterised in that should
Threshold voltage generation circuit includes：
One on-off circuit, is controlled by the conductivity control signal；And
One low pass filter, connects the input voltage and exports the threshold voltage signal via the on-off circuit.
5. synchronous buck type DC-DC converter as claimed in claim 3, it is characterised in that should
Threshold voltage generation circuit includes：
One on-off circuit, is controlled by the conductivity control signal；
One ratio circuit, couples the on-off circuit, is controlled by the conductivity control signal, via the on-off circuit
Connect the input voltage and a scale factor is provided；And
One low pass filter, couples the ratio circuit, and being somebody's turn to do with the scale factor is received from the ratio circuit
Input voltage simultaneously exports the threshold voltage signal.
6. synchronous buck type DC-DC converter as claimed in claim 3, it is characterised in that should
Timer circuit includes：
One resistance, receives the input voltage and provides a charging current signal according to the input voltage；
One electric capacity, the capacitance connection receives the charging current signal between the resistance and ground terminal；
One switch element, it is in parallel with the electric capacity；And
One second comparator, receives terminal voltage and threshold voltage signal of the first end of the electric capacity and exports
The timing signal.
7. synchronous buck type DC-DC converter as claimed in claim 3, it is characterised in that should
Threshold voltage signal is directly proportional to the dutycycle.
8. synchronous buck type DC-DC converter as claimed in claim 1, it is characterised in that should
Output-stage circuit includes：
One inductance；And
One on-off circuit, provides the first end in the input voltage and the inductance under the control of the drive circuit
Between a charge path and the discharge path between the first end and ground terminal of the inductance, the wherein inductance
The second end connect the signal output part.
9. synchronous buck type DC-DC converter as claimed in claim 7, it is characterised in that should
Output-stage circuit also includes：
One electric capacity, is connected between the signal output part and the ground terminal.
10. the synchronous buck type DC-DC converter as described in any one of claim 1 to 9,
Characterized in that, also including：
One feedback circuit, is connected between the signal output part and the first comparator.
A kind of 11. synchronous buck type direct currents are to direct current conversion method, it is characterised in that including：
Carry out discharge and recharge to an inductance to provide an output based on an input voltage using a first switch circuit
Voltage；
The switch of the first switch circuit is controlled according to a conductivity control signal；
Compare a feedback voltage signal and a reference voltage signal to produce a control voltage signal, wherein this is anti-
Feedthrough voltage signal is relevant to the output voltage；
Breech lock controls the control voltage signal to enable signal to export a conducting with the timing signal；
The logical process conducting enables signal to export the conductivity control signal；And
The timing signal is produced according to the conductivity control signal and the input voltage, wherein the timing signal is related
In a dutycycle of the first switch circuit.
12. synchronous buck type direct currents as claimed in claim 11 are to direct current conversion method, it is characterised in that
The time-count cycle of the timing signal is proportional to the dutycycle.
13. synchronous buck type direct currents as claimed in claim 11 are to direct current conversion method, it is characterised in that
The generation step of the timing signal includes：
The input voltage a to low pass filter is provided via a second switch circuit；
A threshold voltage signal, the wherein threshold voltage signal and the dutycycle are exported using the low pass filter
It is proportional；
The switch of the second switch circuit is controlled according to the conductivity control signal；
A charging current signal is provided based on the input voltage；And
The timing signal is produced according to the threshold voltage signal and the charging current signal.
14. synchronous buck type direct currents as claimed in claim 13 are to direct current conversion method, it is characterised in that
The threshold voltage signal is directly proportional to the dutycycle.
15. synchronous buck type direct currents as claimed in claim 11 are to direct current conversion method, it is characterised in that
The generation step of the timing signal includes：
The input voltage is provided via a second switch circuit；
The input voltage with a scale factor is produced according to the conductivity control signal；
A threshold voltage is exported using the low pass filter according to the input voltage with the scale factor to believe
Number, wherein the threshold voltage signal is proportional to the dutycycle；
The switch of the second switch circuit is controlled according to the conductivity control signal；
A charging current signal is provided based on the input voltage；And
The timing signal is produced according to the threshold voltage signal and the charging current signal.
16. synchronous buck type direct currents as claimed in claim 15 are to direct current conversion method, it is characterised in that
The threshold voltage signal is directly proportional to the dutycycle.
The 17. synchronous buck type direct current as described in any one of claim 11 to 16 is to direct current conversion side
Method, it is characterised in that also include：
Voltage division processing is carried out to the output voltage to produce the feedback voltage signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109784097A (en) * | 2017-11-13 | 2019-05-21 | 意法半导体(鲁塞)公司 | For modifying the method and relevant device of the consumption distribution of logic circuit at random |
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| US8242764B2 (en) * | 2008-09-12 | 2012-08-14 | Ricoh Company, Ltd. | DC-DC converter having VFM mode in which inductor current increases and switching frequency decreases |
| CN102801313A (en) * | 2011-05-27 | 2012-11-28 | 株式会社理光 | Switching regulator and electronic device incorporating same |
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| US8242764B2 (en) * | 2008-09-12 | 2012-08-14 | Ricoh Company, Ltd. | DC-DC converter having VFM mode in which inductor current increases and switching frequency decreases |
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| CN109784097A (en) * | 2017-11-13 | 2019-05-21 | 意法半导体(鲁塞)公司 | For modifying the method and relevant device of the consumption distribution of logic circuit at random |
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Application publication date: 20170613 |