CN106786451A - A kind of analog power domain esd protection circuit - Google Patents

Abstract

The present invention relates to the integrated circuit (IC in microelectronics：Integrated Circuit) static discharge (ESD：Electro Static Discharge) design protection technical field; disclose a kind of analog power domain esd protection circuit; it is applied to the ESD circuit design of multi-power domain digital-analog mix-mode chip; it is particularly suited for the ESD circuit design in analog power domain; by across power domain triggering technique; the ESD protections to analog power domain kernel circuitry are realized, the low-power consumption of chip, antimierophonic requirement is also met, while solving the problems, such as esd discharge circuit false triggering during chip normal work.

Description

A kind of analog power domain esd protection circuit

Technical field

The present invention relates to a kind of analog power domain esd protection circuit, it is adaptable to which the ESD of multi-power domain digital-analog mix-mode chip is protected Shield design, is particularly suited for the ESD design protections that ESD is easier the analog power domain of failure.

Background technology

CMOS (Complementary Metal-Oxide-Semiconductor) technique, i.e. CMOS half Semiconductor process, grows up on PMOS and NMOS Process ba- sis, will nmos device and PMOS device be produced on simultaneously On same silicon substrate, CMOS integrated circuits are made.CMOS integrated circuits have fast low in energy consumption, speed, strong antijamming capability, integrated Spend high many merits.CMOS technology has turned into the prevailing technology technology of current large scale integrated circuit, overwhelming majority collection at present All it is to be manufactured with CMOS technology into circuit.

IC chip from producing to encapsulating, test, transport, applying, whole life cycle can all face various being difficult to The electrostatic environment of precognition, electrostatic damage is caused to integrated circuit.So integrated circuit will not only disclosure satisfy that the function of design will Ask, while also to have the antistatic capacity of certain level.

Chip-scale is increasing, and power domain is more and more, and chip port increasingly enriches, and internal structure is more and more multiple Miscellaneous, integrated module is more and more, and including digital module, analog module, radio-frequency module etc., chip application environment is also more and more multiple Miscellaneous, this all brings increasingly stern challenge to the ESD reliability designs of chip.However, the ESD design protections of chip do not have Unified method for designing, per chips all because its processing technology and circuit structure feature are needed using the ESD design sides for customizing Method, could finally realize successful ESD designs.

IO (the Input/Output that usual electrostatic passes through integrated circuit:Input and output) pin enters IC interior, The ESD failures on IO inside or IO peripheries may be directly contributed, it is also possible to be connected serially between power supply and ground by IO, this will likely The ESD in whole power domain is caused to fail.So the ESD design protections of integrated circuit, will not only carry out the ESD protections of I/O port Design, it is often more important that carry out the ESD design protections of whole power domain.

Nowadays many IC chips are all complicated numeral, simulation hybrid chip, and are different from patrolling for comparison rule Architecture digital circuit core design is collected, the different connections of substantial amounts of different conditions may be then directly connected to inside simulation kernel circuitry The irregular large scale cmos device of structure, these special constructions can all become more sensitive fragility under ESD condition of high voltage, Relative to digital power domain, analog power domain is easier ESD damage, and ESD designs are more challenged.

Due to the particular design of analog power domain kernel circuitry, the ESD failure breakdown voltages in analog power domain are than common number Word power domain is lower, so the existing grounded-grid NMOS structure esd protection circuits such as Fig. 2 tend not to effectively protection simulation Power domain kernel circuitry, especially the analog power domain kernel circuitry of the chip of advanced technologies processing.To solve the problem, propose Grid such as Fig. 3 couples NMOS structure esd protection circuits, due to the coupling of RC (capacitance resistance) 303-304 of grid, The cut-in voltage of ESD device can be reduced, therefore analog power domain especially advanced technologies chip core circuit ESD can be solved The relatively low problem of failure voltage.

But the working condition of analog circuit be also it is very various, than if any the analog circuit low-down work(of requirement Consumption, the noise of some analog powers is very big, then the grid coupling NMOS structure esd protection circuits such as Fig. 3 often cause Very big electricity leakage power dissipation, causes the power consumption of whole chip very big, and this is very badly suited for low power dissipation design and is especially to rely on Battery powered mobile device chip design.Therefore the low drain electric grid coupling NMOS structures ESD protection electricity such as Fig. 4 is proposed Road, electricity leakage power dissipation can be substantially reduced by two-stage trigger architecture, but still there is RC trigger architectures, and electric leakage is not completely eliminated Power consumption, the low power dissipation design very harsh in the industry for nowadays integrated circuit row is still inapplicable.

As the grid coupling NMOS structures esd protection circuit of Fig. 3 and the low drain electric grid coupling NMOS structures ESD of Fig. 4 are protected Protection circuit depends on the transient response frequency of ESD to trigger, and the appropriate noise of same frequency can similarly trigger ESD device and open The risk that ESD device is opened by power supply noise false triggering when opening, therefore there is chip normal work, then will cause the chip can not The serious consequence of normal work.

The content of the invention

In order to solve the above problems, a kind of analog power domain esd protection circuit disclosed by the invention, you can effectively to protect Kernel circuitry fails from ESD, while having noise resisting ability very high, the ESD devices caused by power supply noise is avoided completely Part is opened by mistake and opened, and the electricity leakage power dissipation that ESD device is relevant is avoided completely, is conducive to chip low power dissipation design and High Reliability Design.

A kind of analog power domain esd protection circuit, it is quicker mainly for the protection of ESD in multi-power domain digital-analog mix-mode chip The analog power domain kernel circuitry of sense, but triggering technique is opened different from existing ESD device, the present invention is touched using isolated from power Hair technology, the ESD device triggered by digital power signal in simulation power domain opens electric discharge.

Such as Fig. 1, in digital power domain, digital power signal directly controls ESD in analog power domain by current-limiting resistance The open and close of the PMOS of discharge circuit, when ESD is tested, DVDD is low level, and PMOS can be opened, will export high level to The grid of ESD device NMOS, so that ESD device opens electric discharge, and during chip normal work, DVDD is high level, and PMOS can be closed Close, because the grid of ESD device NMOS is pulled to low level by pull down resistor R2, ESD device is closed.

By the method for the present invention, when chip receives ESD to be tested, ESD device can be opened and discharged, protection simulation electricity Source domain kernel circuitry, and when chip normal work, ESD device is fully closed, and thoroughly avoids the ESD caused by power supply noise Device is opened by mistake and opens the electricity leakage power dissipation relevant with ESD device.

Brief description of the drawings

Below in conjunction with the accompanying drawings, the present invention will be described in detail

Fig. 1 esd protection circuit structure charts in analog power domain of the invention；

The existing grounded-grid NMOS structures esd protection circuit structure charts of Fig. 2；

The existing grid coupling NMOS structure esd protection circuit structure charts of Fig. 3；

The existing low drain electric grid coupling NMOS structure esd protection circuit structure charts of Fig. 4.

Specific embodiment

Of the present invention is a kind of analog power domain esd protection circuit, can be to ESD in multi-power domain digital-analog mix-mode chip more Plus the analog power domain kernel circuitry of sensitivity provides reliable ESD protections, embodiment is as follows：

Such as Fig. 1, in multi-power domain digital-analog mix-mode chip, usually comprising one or more digital power domains, and one or Multiple analog power domains, by taking digital power domain DVDD therein and analog power domain AVDD as an example, the ground DVSS in digital power domain Isolated using bilateral diode 107 between 102 and the ground AVSS 104 in analog power domain, there is provided the electric discharge between two power domains Path, and two power supply DVDD 101 and AVDD's 103 of power domain is separated, current-limiting resistance R2 109 is connected to digital electricity In source DVDD 101 and analog power domain between the grid of the PMOS 106 of esd discharge circuit, the current limliting to PMOS grids is played Protective effect, the source class and substrate of PMOS are connected to analog power AVDD 103, and the drain electrode of PMOS is that output end is connected to ESD devices The grid of part NMOS 105, at the same pull down resistor R1 108 be connected to PMOS drain electrode and analog power domain ground AVSS 104 it Between, esd discharge device NMOS 105 is connected between the power supply AVDD 103 in analog power domain and ground AVSS 104, there is provided simulation The ESD protective effects of power domain.

When ESD high pressures over the ground occur in the ends of analog power AVDD 103, digital power DVDD 101 is in floating state, But due to the coupling between DVDD 101 and DVSS 102, DVDD 101 will be in the low level state close to DVSS " 0 " state, therefore digital power DVDD 101 will export level "0" by current-limiting resistance R2 109 to PMOS grids, now PMOS 106 will be opened, therefore can give the grid output level"1" of ESD device NMOS 105, so esd discharge device NMOS will Electric discharge is opened, the ESD high-voltage safeties that the ends of analog power AVDD 103 occur over the ground ground is released to rapidly, it is to avoid analog power domain There is ESD failures in kernel circuitry, effectively protect chip.The method does not influence on the esd discharge of other patterns.

When chip normal work, digital power DVDD 101 is in high level one state, by current-limiting resistance R2 109 High level " 1 " is exported to the grids of PMOS 106, therefore PMOS will protect completely closed state, PMOS is output as high-impedance state, and under The grid of ESD device NMOS 105 will be pulled down to " 0 " current potential by pull-up resistor R1, so esd discharge device NMOS 105 will be complete It is closed entirely.Different from existing triggering technique, the analog power domain ESD circuit of this method is triggered by digital power domain separation Open, therefore the noise in analog power domain will not cause opening by mistake for ESD device 105 to be opened completely, while also completely avoid simulation The electricity leakage power dissipation that the noise of power supply AVDD 103 is produced.

Claims (3)

1. a kind of analog power domain esd protection circuit, it is characterised in that in multi-power domain digital-analog mix-mode chip, digital power DVDD Electric discharge is opened by the ESD circuit in current-limiting resistance R2 control analog powers domain, digital power DVDD is connected by current-limiting resistance R2 The grid of PMOS, the grid of PMOS output ends connection esd discharge device NMOS, DVDD controls the unlatching of PMOS, so as to control ESD Discharge device NMOS opens electric discharge, realizes that digital power signal control analog power domain ESD circuit opens the isolated from power of electric discharge Triggering technique, while the grid of NMOS meets the ground AVSS in analog power domain by pull down resistor R1.

2. circuit as claimed in claim 1, it is characterised in that the ground DVSS in the digital power domain and ground AVSS in analog power domain Between by bilateral diode structure (107) connect, there is provided esd discharge path.

3. circuit as claimed in claim 1, it is characterised in that the span of resistance R2 is 1000 ohm -10000 ohm, electricity The span for hindering R1 is 1000 ohm -10000 ohm, and the width range of resistance R1 is 2um-20um, the channel width of PMOS It is 5um-200um, the channel width of NMOS is 200um-5000um.