CN101996967A - Power bus structure used for multi-power supply chip - Google Patents
Power bus structure used for multi-power supply chip Download PDFInfo
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- CN101996967A CN101996967A CN2009101944476A CN200910194447A CN101996967A CN 101996967 A CN101996967 A CN 101996967A CN 2009101944476 A CN2009101944476 A CN 2009101944476A CN 200910194447 A CN200910194447 A CN 200910194447A CN 101996967 A CN101996967 A CN 101996967A
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Abstract
The invention discloses a power bus structure used for a multi-power supply chip, which comprises a group of global power supply bus and a plurality of power supply groups. The global power bus penetrates through the whole chip and is electrically connected with each power supply group, wherein at least one of two adjacent power supply groups has a local power bus, each power supply group is provided with a plurality of power supply units, at least one power supply unit is provided with an electrostatic discharge device used for separating a high-potential local power supply bus from a low-potential global power supply bus, and at least another power supply unit is provided with an electrostatic discharge device used for separating a low-potential local power supply bus from a high-potential global power supply bus. Under the condition that the chip has more power supply groups, the power bus structure can reduce the area of the chip.
Description
Technical field
The present invention relates to the semiconductor integrated circuit design, particularly be used for the power bus structure of many power supply chips.
Background technology
Integrated circuit (IC) chip of today generally all has multi-group power in order to separate noise.It is (I/O), internal logic circuit, each analog module and be used to test that commonly used power pack is useful on input and output.For general pure logic chip, two to three groups of power supplys are just enough.But mix (Mixed Signal) chip or system level chip (SOC) for digital-to-analogue, three groups above in addition nearly tens groups of power supplys all can be integrated in the chip of an individual packages.
Along with the number of integrated circuit (IC) chip power pack is more and more, its full chip electrostatic protection design also becomes more complicated.Generally take at present the solution of the many power buss of multizone, the multi-group power of different application is arranged in the zones of different of chip, each is organized between the power supply and distinguishes with the power supply separating element.
For example, with reference to shown in Figure 1, a kind of example of many power buss of multizone structure comprises multi-group power, and wherein two groups of adjacent power supplys comprise: be used for the power pack of digital circuitry regions and be used for the power pack in analog circuit zone, wherein VDD, GND represent one group of local power line; VDDHA, VSSHA representative is used for one group of global power bus in analog circuit zone; VDDHD, VSSHD representative is used for one group of global power bus of digital circuitry regions.The power pack of digital circuitry regions comprises: have digital I/O pin power subsystem, have high potential global power bus VDDHD pin power subsystem, have the power subsystem of electronegative potential global power bus VSSHD pin.The power pack in analog circuit zone comprises: have Simulation with I/O pin power subsystem, have high potential global power bus VDDHA pin power subsystem, have the power subsystem of electronegative potential global power bus VSSHA pin.Electro-static discharging device all is set to carry out the partial electrostatic protection in each power subsystem.And at the power subsystem with high potential power bus VDDHD pin and have and also have the power supply separating element between the power subsystem of Simulation with I/O pin.
Described power supply separating element comprises the electro-static discharging device that is electrically connected high potential global power bus VDDHD, VDDHA, and the electro-static discharging device that is electrically connected electronegative potential global power bus VSSHD, VSSHA.Described electro-static discharging device makes not global power bus on the same group be communicated with, so that the circuit that the static discharge zone occurs is protected when static discharge takes place.For example, when digital circuitry regions produced static discharge, the electro-static discharging device in the power supply separating element will be communicated with VDDHD with VDDHA, or VSSHD is communicated with VSSHA, with the shunting static discharge current, the circuit of digital circuitry regions was protected.
Yet along with getting more and more of power pack in the chip, the power supply separating element of said structure will too much increase area of chip.
Summary of the invention
The present invention solves the power bus structure that prior art is applied to the chip of many power supplys, can increase area of chip more for a long time in power pack, and influences the problem of full chip electrostatic protective benefits.
For addressing the above problem, the invention provides a kind of power bus structure that is used for many power supply chips, comprising: run through one group of global power bus of full chip and respectively organize power supply with described global power bus is electrically connected, wherein,
Have at least one group of power supply to have one group of locally supplied power source's bus in the two adjacent groups power supply, have a plurality of power subsystems in the described power pack, wherein at least one power subsystem has the electro-static discharging device of separating high potential locally supplied power source's bus and electronegative potential global power bus; At least another power subsystem has the electro-static discharging device of separating electronegative potential locally supplied power source's bus and high potential global power bus.
Compared with prior art, above-mentioned power bus structure has the following advantages: by the electro-static discharging device of respective electrical source unit in one group of power supply in the two adjacent groups power supply, realize separating the purpose of different two groups power supply.Therefore, need not between two groups of power supplys, to be provided with extra power supply separating element.Under the more situation of the power pack number of chip, can reduce area of chip.
Description of drawings
Fig. 1 is the example schematic of existing a kind of many power buss of multizone structure;
Fig. 2 is a kind of embodiment schematic diagram of the present invention's power bus structure of being used for many power supply chips;
Fig. 3 is the another kind of embodiment schematic diagram of the present invention's power bus structure of being used for many power supply chips.
Embodiment
Power supply separating element in the existing power supply bus structures, it is respectively by electro-static discharging device that is used for high potential and the electro-static discharging device that is used for electronegative potential, the separation of high potential global power bus and electronegative potential global power bus between realizing not on the same group, and each group power supply carried out electrostatic defending.And bus-structured further analysis can be found to existing power supply, and each is organized in the power subsystem in the power supply has had electro-static discharging device that is used for electronegative potential global power bus and the electro-static discharging device that is used for high potential global power bus.Therefore, if can be when separating the global power bus with above-mentioned power subsystem in electro-static discharging device realization of the same race shared, just need not between two groups of power supplys, to be provided with again the power supply separating element.
Based on this, the present invention is used for a kind of execution mode of the power bus structure of many power supply chips, comprising: run through one group of global power bus of full chip and respectively organize power supply with described global power bus is electrically connected, wherein,
Have at least one group of power supply to have one group of locally supplied power source's bus in the two adjacent groups power supply, have a plurality of power subsystems in the described power pack, wherein at least one power subsystem has the electro-static discharging device of separating high potential locally supplied power source's bus and electronegative potential global power bus; At least another power subsystem has the electro-static discharging device of separating electronegative potential locally supplied power source's bus and high potential global power bus.
In the above-mentioned execution mode,, make that this group power supply is bus-powered by locally supplied power source, and another group power supply is bus-powered by global power by at least one group of power supply in the two adjacent groups power supply locally supplied power source's bus being set.Thereby,, need not to carry out the power supply separation at the level of global bus for the two adjacent groups power supply.
And, to use in the existing power supply bus structures, each organizes power supply itself electro-static discharging device that is applied to high potential that has had and the electro-static discharging device that is applied to electronegative potential, realizes the separation of global power bus and local power bus.
Therefore, the power bus structure of above-mentioned execution mode, it need not to be provided with the power supply separating element again between the two adjacent groups power supply, under the more situation of the power pack number of chip, can reduce area of chip.
Below sum up structure example by concrete power supply and further specify.
With reference to shown in Figure 2, a kind of embodiment that the present invention is used for the power bus structure of many power supply chips comprises multi-group power, and wherein two groups of adjacent power supplys comprise:
Be used for the power pack of digital circuitry regions and be used for the power pack in analog circuit zone, wherein VDD, GND represent one group of local power line; VDDHDG, VSSHDG represent one group of global power bus, and this group global power bus runs through entire chip; VDDHAG, VSSHAG representative is used for one group of locally supplied power source's bus in analog circuit zone, and it is exclusively used in the power supply in analog circuit zone.
The power pack of digital circuitry regions comprises: have digital I/O pin power subsystem 10, have electronegative potential global power bus VSSHDG pin power subsystem 11, have the power subsystem 12 of high potential global power bus VDDHDG pin.
The electro-static discharging device that has two series connection in the power subsystem 10, be electrically connected between high potential global power bus VDDHDG and the electronegative potential global power bus VSSHDG, the lead-in wire of described digital I/O pin is electrically connected with described two electro-static discharging devices respectively.For example, as electro-static discharging device, what connect VDDHDG is the PMOS pipe with metal-oxide-semiconductor, and connection VSSHDG's is the NMOS pipe.
Respectively have an electro-static discharging device in the power subsystem 11,12, its two ends are electrically connected in respectively between high potential global power bus VDDHDG and the electronegative potential global power bus VSSHDG.
The power pack in analog circuit zone comprises: have Simulation with I/O pin power subsystem 20, have the bus VSSHAG of electronegative potential locally supplied power source pin power subsystem 21, have the power subsystem 22 of the bus VDDHAG of high potential locally supplied power source pin.
The structural similarity of the structure of power subsystem 20 and power subsystem 10, its difference are that two electro-static discharging devices are electrically connected between bus VDDHAG of high potential locally supplied power source and the bus VSSHAG of electronegative potential locally supplied power source.
The structural similarity of the structure of power subsystem 21 and power subsystem 11, its difference are that electro-static discharging device is electrically connected between high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source.Described electro-static discharging device essence has been separated high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source.And when digital circuitry regions produced static discharge, described electro-static discharging device was communicated with high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source, and the shunting static discharge current is with the protection digital circuitry regions.If as electro-static discharging device, is the NMOS pipe with metal-oxide-semiconductor herein.The static discharge of positive voltage is in fact by the parasitic BJT discharge among the NMOS, and the static discharge of negative voltage is by leakage and the discharge of the parasitic diode between substrate of NMOS.
The structural similarity of the structure of power subsystem 22 and power subsystem 12, its difference are that electro-static discharging device is electrically connected between bus VDDHAG of high potential locally supplied power source and the electronegative potential global power bus VSSHDG.Described electro-static discharging device essence has been separated bus VDDHAG of high potential locally supplied power source and electronegative potential global power bus VSSHDG.And when digital circuitry regions produced static discharge, described electro-static discharging device was communicated with bus VDDHAG of high potential locally supplied power source and electronegative potential global power bus VSSHDG, and the shunting static discharge current is with the protection digital circuitry regions.If as electro-static discharging device, is the NMOS pipe with metal-oxide-semiconductor herein.The static discharge of positive voltage is in fact by the parasitic BJT discharge among the NMOS, and the static discharge of negative voltage is by leakage and the discharge of the parasitic diode between substrate of NMOS.
With reference to shown in Figure 3, the another kind of embodiment that the present invention is used for the power bus structure of many power supply chips comprises multi-group power, and wherein two groups of adjacent power supplys comprise:
Be used for the power pack of digital circuitry regions and be used for the power pack in analog circuit zone, wherein VDD, GND represent one group of local power line; VDDHDG, VSSHDG represent one group of global power bus, and this group global power bus runs through entire chip; VDDHAG, VSSHAG representative is used for one group of locally supplied power source's bus in analog circuit zone, and it is exclusively used in the power supply in analog circuit zone; VDDHDG1, VSSHDG1 representative is used for one group of locally supplied power source's bus of digital circuitry regions, and it is exclusively used in the power supply of digital circuitry regions.
The power pack of digital circuitry regions comprises: have digital I/O pin power subsystem 100, have electronegative potential global power bus VSSHDG pin power subsystem 101, have the power subsystem 102 of high potential global power bus VDDHDG pin.
The electro-static discharging device that has two series connection in the power subsystem 100, be electrically connected between bus VDDHDG1 of high potential locally supplied power source and the bus VSSHDG1 of electronegative potential locally supplied power source, and bus VDDHDG1 of high potential locally supplied power source and global power bus VDDHDG are electrically connected, bus VSSHDG1 of electronegative potential locally supplied power source and global power bus VSSHDG are electrically connected, and the lead-in wire of described digital I/O pin is electrically connected with described two electro-static discharging devices respectively.For example, as electro-static discharging device, what connect VDDHDG1 is the PMOS pipe with metal-oxide-semiconductor, and connection VSSHDG1's is the NMOS pipe.
Respectively have an electro-static discharging device in the power subsystem 101,102, its two ends are electrically connected in respectively between bus VDDHDG1 of high potential locally supplied power source and the bus VSSHDG1 of electronegative potential locally supplied power source.
The power pack in analog circuit zone comprises: have Simulation with I/O pin power subsystem 200, have the bus VSSHAG of electronegative potential locally supplied power source pin power subsystem 201, have the power subsystem 202 of the bus VDDHAG of high potential locally supplied power source pin.
The structural similarity of the structure of power subsystem 200 and power subsystem 100, its difference are that two electro-static discharging devices are electrically connected between bus VDDHAG of high potential locally supplied power source and the bus VSSHAG of electronegative potential locally supplied power source.
The structural similarity of the structure of power subsystem 201 and power subsystem 101, its difference are that electro-static discharging device is electrically connected between high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source.Described electro-static discharging device essence has been separated high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source.And when digital circuitry regions produced static discharge, described electro-static discharging device was communicated with high potential global power bus VDDHDG and the bus VSSHAG of electronegative potential locally supplied power source, and the shunting static discharge current is with the protection digital circuitry regions.If as electro-static discharging device, is the NMOS pipe with metal-oxide-semiconductor herein.
The structural similarity of the structure of power subsystem 202 and power subsystem 102, its difference are that electro-static discharging device is electrically connected between bus VDDHAG of high potential locally supplied power source and the electronegative potential global power bus VSSHDG.Described electro-static discharging device essence has been separated bus VDDHAG of high potential locally supplied power source and electronegative potential global power bus VSSHDG.And when digital circuitry regions produced static discharge, described electro-static discharging device was communicated with bus VDDHAG of high potential locally supplied power source and electronegative potential global power bus VSSHDG, and the shunting static discharge current is with the protection digital circuitry regions.If as electro-static discharging device, is the NMOS pipe with metal-oxide-semiconductor herein.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a power bus structure that is used for many power supply chips is characterized in that, comprising: run through one group of global power bus of full chip and respectively organize power supply with described global power bus is electrically connected, wherein,
Have at least one group of power supply to have one group of locally supplied power source's bus in the two adjacent groups power supply, have a plurality of power subsystems in the described power pack, wherein at least one power subsystem has the electro-static discharging device of separating high potential locally supplied power source's bus and electronegative potential global power bus; At least another power subsystem has the electro-static discharging device of separating electronegative potential locally supplied power source's bus and high potential global power bus.
2. the power bus structure that is used for many power supply chips as claimed in claim 1 is characterized in that, only has one group of power supply to have one group of locally supplied power source's bus in the two adjacent groups power supply.
3. the power bus structure that is used for many power supply chips as claimed in claim 1, it is characterized in that, the two adjacent groups power supply all has one group of locally supplied power source's bus separately, and wherein locally supplied power source's bus of one group of power supply is electrically connected with corresponding global power bus respectively.
4. the power bus structure that is used for many power supply chips as claimed in claim 1 is characterized in that, the electro-static discharging device of described separation high potential locally supplied power source bus, electronegative potential global power bus is the NMOS pipe.
5. the power bus structure that is used for many power supply chips as claimed in claim 1 is characterized in that, the electro-static discharging device of described separation electronegative potential locally supplied power source's bus and high potential global power bus is the NMOS pipe.
6. the power bus structure that is used for many power supply chips as claimed in claim 1 is characterized in that, the power pack that described two adjacent groups power supply is respectively applied for the power pack of digital circuitry regions and is used for the analog circuit zone.
7. the power bus structure that is used for many power supply chips as claimed in claim 6, it is characterized in that, the described power pack that is used for digital circuitry regions comprises the power subsystem with digital I/O pin, the described power pack that is used for the analog circuit zone comprises having Simulation with I/power subsystem of O pin, described have digital I/O pin and have in the power subsystem of Simulation with I/O pin include: the electro-static discharging device that links to each other with high potential global power bus or high potential locally supplied power source bus, and the electro-static discharging device that links to each other with electronegative potential global power bus or electronegative potential locally supplied power source bus.
8. the power bus structure that is used for many power supply chips as claimed in claim 7 is characterized in that, the electro-static discharging device that links to each other with high potential global power bus or high potential locally supplied power source bus is the PMOS pipe.
9. the power bus structure that is used for many power supply chips as claimed in claim 7 is characterized in that, the electro-static discharging device that links to each other with electronegative potential global power bus or electronegative potential locally supplied power source bus is the NMOS pipe.
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| CN2009101944476A CN101996967B (en) | 2009-08-17 | 2009-08-17 | Power bus structure used for multi-power supply chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600687A (en) * | 2015-01-06 | 2015-05-06 | 武汉新芯集成电路制造有限公司 | Electrostatic protection circuit of three-dimensional integrated circuit |
| CN106786451A (en) * | 2016-11-30 | 2017-05-31 | 北京中电华大电子设计有限责任公司 | A kind of analog power domain esd protection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100538601C (en) * | 2005-02-14 | 2009-09-09 | 高通股份有限公司 | Be used to enable the distributed feed power switch circuit of each power domain |
| US7420789B2 (en) * | 2005-10-21 | 2008-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection system for multi-power domain circuitry |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600687A (en) * | 2015-01-06 | 2015-05-06 | 武汉新芯集成电路制造有限公司 | Electrostatic protection circuit of three-dimensional integrated circuit |
| CN104600687B (en) * | 2015-01-06 | 2018-03-30 | 武汉新芯集成电路制造有限公司 | The electrostatic discharge protective circuit of three dimensional integrated circuits |
| CN106786451A (en) * | 2016-11-30 | 2017-05-31 | 北京中电华大电子设计有限责任公司 | A kind of analog power domain esd protection circuit |
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| CN101996967B (en) | 2012-06-27 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20131128 |
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Effective date of registration: 20131128 Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |