CN107240585B

CN107240585B - Circuit device with electrostatic protection function

Info

Publication number: CN107240585B
Application number: CN201610185943.5A
Authority: CN
Inventors: 李传胜; 高秉佑
Original assignee: Ali Corp
Current assignee: Ali Corp
Priority date: 2016-03-29
Filing date: 2016-03-29
Publication date: 2020-03-17
Anticipated expiration: 2036-03-29
Also published as: CN107240585A

Abstract

A circuit device with electrostatic protection function comprises a first signal connecting pad, a first electrostatic discharge path and a second electrostatic discharge path. The first ESD path includes a first power rail, a first signal ESD circuit, and at least a first power ESD circuit. The first signal electrostatic discharge circuit is coupled between the first power rail and the first signal pad. The at least one first power ESD circuit is coupled between the first power rail and the ground power rail. The second ESD path includes a second power rail and at least one second power ESD circuit. The at least one second power ESD circuit is coupled between the second power rail and the ground power rail. The voltage level of the first power rail is lower than the voltage level of the second power rail. When static electricity is generated by the first signal connecting pad, a first external signal is released through a first static discharge path.

Description

Circuit device with electrostatic protection function

Technical Field

The present invention relates to a circuit device with electrostatic discharge protection, and more particularly, to a circuit device with multiple power rails.

Background

Substances in nature may gain or lose electrons through friction or induction charging, and such charges are called static electricity. When these charges are accumulated, a potential difference is generated between the charges and the surrounding environment, and if the charges are transferred between different potentials through a Discharge path, a phenomenon called Electrostatic Discharge (ESD) occurs.

JEDEC organizes the cause of ESD generation and the way it discharges into Integrated Circuits (ICs) differently, classifying ESD into several different modes, including Human-Body Model (HBM), Machine Model (MM), and Device charging Model (CDM). For example, static electricity may accumulate when a person walks on the ground, and when the person touches the integrated circuit, the static electricity may enter the integrated circuit through the pins of the integrated circuit, causing damage to the internal components of the integrated circuit. As the integrated circuit is advanced in process technology, the device size is gradually reduced, and the protection capability of the device against ESD is gradually reduced, but the static electricity generated in the external environment is not reduced. Therefore, how to properly design the ESD protection circuit is one of the issues addressed in the industry.

Disclosure of Invention

An objective of the present invention is to provide a circuit device with electrostatic discharge protection function, which is suitable for circuits with different voltage power supplies and can provide better electrostatic discharge protection capability. When the electrostatic signal enters from the signal connecting pad, the electrostatic can be released by the better releasing power rail.

According to an embodiment of the present invention, a circuit device with an electrostatic discharge protection function is provided, which includes a first signal pad, a first electrostatic discharge path, and a second electrostatic discharge path. The first signal pad receives a first external signal. The first ESD path includes a first power rail, a first signal ESD circuit, and at least a first power ESD circuit. The first signal electrostatic discharge circuit is coupled between the first power rail and the first signal pad. The at least one first power ESD circuit is coupled between the first power rail and the ground power rail. The second ESD path includes a second power rail and at least one second power ESD circuit. The at least one second power ESD circuit is coupled between the second power rail and the ground power rail. The voltage level of the first power rail is lower than the voltage level of the second power rail. When static electricity is generated by the first signal connecting pad, the first external signal is released through the first static discharge path.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a first embodiment of the invention.

FIG. 2 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a third embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a fourth embodiment of the present invention.

Detailed Description

The ESD protection circuit is used for ESD protection, and provides an ESD current path for discharging ESD current, so as to prevent the IC from being damaged due to the ESD current flowing into the IC internal circuit. Due to ESD from the integrated circuitExternally, the ESD protection circuit is usually disposed adjacent to the signal PAD (PAD). Taking a Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit as an example, the signal pad is usually connected to the gate (gate) of the input stage device, and since the gate Oxide layer is easily broken through by ESD, a set of ESD protection circuits can be disposed beside the signal pad to protect the input stage device from ESD damage. In addition, since the power supply rail (V) is supplied_DD) And a grounded power rail (V)_SS) May also be subject to ESD discharge between the pins, and thus, in the supply power rail (V)_DD) And a ground power rail (V)_SS) The ESD protection circuitry is also typically disposed beside.

The ESD protection circuitry is inactive under normal operating conditions of the integrated circuit. Therefore, in addition to meeting the ESD protection capability required by the integrated circuit, the design also needs to reduce the cost increased by the ESD protection circuit, such as the increase of the circuit layout (layout) area or the increase of the manufacturing steps, as much as possible.

With the increasing demand for integrating various functional integrated circuit chips and the emphasis on low power consumption of the products, multi-power domain (multi-power domain) designs are widely used. The present invention provides an ESD protection circuit that can be applied to a circuit with multiple power domains, and can provide a good electrostatic protection capability and effectively save the occupied circuit area.

In a multi-domain circuit, at least two different supply voltages may be included, e.g., one of the power rails may provide a voltage level of V_DDAnother power rail may provide a voltage level of V_DDHOf supply voltage of, wherein V_DD<V_DDHE.g. V_DD＝3.3V，V_DDH5V to correspond to different supply voltages required by different elements in the circuit. The circuit further includes a ground power rail, where the ground power rail represents the most negative supply voltage V in the circuit_SSThe voltage level of the ground power rail is not limited to 0 volts. The multi-power-domain circuit may include a plurality ofA signal pad, wherein a voltage range of a signal received or output by a part of the signal pad corresponds to V_DDThe voltage range of the signal received or output by the other part of the signal connecting pad corresponds to V_DDH。

In the following description, the ESD protection circuit may include a plurality of ESD circuits, and taking the above-mentioned multi-power domain circuit as an example, each power rail may have a corresponding ESD circuit to discharge ESD current. For example, a power ESD circuit may be coupled between the power rail and the ground power rail; another power ESD circuit may be coupled between another power rail and a ground power rail. The components used in the esd circuit are, for example, a diode (diode) or a Metal Oxide Semiconductor (MOS), and the esd circuit may also be formed by the diode and/or the MOS and a resistor, but the invention is not limited thereto. For the power rail with higher voltage level, since the corresponding ESD circuit needs to be designed at high voltage, more cascaded diodes or more cascaded (cascode) MOS devices may be required, and thus, when ESD current needs to flow through the ESD circuit, a large area of the cascaded diodes or MOS devices must be placed to support the high voltage of the ESD circuit. However, the multi-stage clamping circuit may result in an increased chance of ESD failure or a reduced ESD voltage level that the circuit can withstand during ESD testing.

According to the method of an embodiment of the present invention, a target power rail that is most suitable for being used as an ESD current release path can be selected from a plurality of power rails of a circuit, and an ESD circuit of a signal pad is coupled to the target power rail. The target power rail may be selected by selecting the power rail with the lower voltage to avoid the above-mentioned problems (area and protection capability) of the multi-stage cascode device. In another embodiment, the target power rail may be selected by selecting the power rail with the smallest equivalent resistance or selecting the power rail providing the largest number of power esd circuit paths. The circuit device with electrostatic protection function according to the present invention will be described in detail with several embodiments.

Fig. 1 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a first embodiment of the invention. The circuit device 1 with the electrostatic discharge protection function includes a first signal pad 210 for receiving a first external signal X, a first electrostatic discharge path, and a second electrostatic discharge path. The first esd path includes the first signal esd circuit 211, the first power rail P1, and at least one first power esd circuit 110. The first signal esd circuit 211 is coupled between the first power rail P1 and the first signal pad 210. The first power ESD circuit 110 is coupled between the first power rail P1 and the ground power rail P0. The second ESD path includes the second power rail P2 and the second power ESD circuit 120 coupled between the second power rail P2 and the ground power rail P0. In one embodiment, the voltage level V of the first power rail P1_DDLower than the voltage level V of the second power rail P2_DDH. When static electricity is generated from the first signal pad 210, the circuit device 1 discharges the first external signal X through the first esd path via the first signal esd circuit 211, the first power rail P1, and the first power esd circuit 110. That is, when an electrostatic signal enters from the first signal pad 210, the electrostatic signal can be discharged through the preferred discharging power rail (the first power rail P1).

For simplicity, the first power source esd circuit 110, the second power source esd circuit 120, and the first signal esd circuit 221 in fig. 1 are all shown as esd circuits, but it can be understood by those skilled in the art that the three esd circuits can be implemented in different structures to be respectively suitable for power rails and signal pads with different voltage levels. In addition, in fig. 1, the first power esd circuit 110 is shown as a block, in an actual circuit, the first power esd circuit 110 may include a plurality of esd circuits coupled between the first power rail P1 and the ground power rail P0, and similarly, the second power esd circuit 120 may include a plurality of esd circuits coupled between the second power rail P2 and the ground power rail P0.

As shown in figure 1In one example, the target power rail is selected to have the lower voltage level (V) of the two power rails_DD) The first signal esd circuit 211 is coupled to the first power rail P1, wherein a voltage range of the first external signal X received by the first signal pad 210 does not necessarily correspond to the voltage level V of the first power rail P1_DD. In one embodiment, the voltage range of the first external signal X received by the first signal pad 210 corresponds to the voltage level V of the second power rail P2_DDH. In this embodiment, the power rail with the lower voltage (the first power rail P1) is selected from the circuit device 1, and the first signal esd circuit 211 is coupled to the first power rail P1. Therefore, no matter the circuit device 1 performs the ESD test or the circuit device 1 actually operates normally, when the voltage level of the first external signal X received by the first signal pad 210 is higher than the voltage level V of the first power rail P1_DDThe first external signal X can be released through the first signal esd circuit 211, the first power rail P1, and the first power esd circuit 110. The first external signal X can be a high voltage signal during ESD test, or a voltage range V during normal operation of the circuit_DDHOf the signal of (1).

Since in this embodiment, the high voltage signal (V)_DDH) Can be discharged through the power rail (the first power rail P1) with a relatively low voltage level, thereby avoiding the need for a large circuit area for the power ESD circuit using a power rail with a relatively high voltage level, avoiding the need for high voltage tolerant devices that may be needed for high voltage circuits, and reducing the chance of ESD failure and increasing the ESD voltage level.

FIG. 2 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a second embodiment of the present invention. In contrast to FIG. 1, the first power ESD circuit 110 originally illustrated in FIG. 1 is represented in FIG. 2 as three first

power ESD circuits

111, 112, and 113 coupled between the first power rail P1 and the ground power rail P0. In this embodiment, when selecting the target power rail, one of the paths providing the most ESD circuits or one of the paths providing the least ESD circuits with the smallest equivalent resistance can be selected. For example, in one embodiment, the first

power ESD circuits

111, 112, 113 have more circuits coupled between the first power rail P1 and the ground power rail P0, and the second power ESD circuit 120 has less circuits coupled between the second power rail P2 and the ground power rail P0, in which case the equivalent resistance of all of the first

power ESD circuits

111, 112, 113 is less than the equivalent resistance of the second power ESD circuit 120, so that the first power rail P1 is selected as the target power rail and the first signal ESD circuit 211 is coupled to the first power rail P1.

Since the selected target power rail provides one of the most ESD circuit paths or the smallest equivalent resistance of the ESD circuit, it is equivalent to providing a better ESD discharging pipeline, so that ESD can be discharged more quickly and effectively, and a higher ESD voltage level can be obtained. As will be appreciated by those skilled in the art, the ESD voltage level can be achieved with a lower ESD circuit area by utilizing an ESD circuit path with a lower equivalent resistance within the circuit. In evaluating ESD quality, a common indicator (form of Merit, FOM) is ESD voltage level divided by ESD circuit area, and as described above, by selecting a power rail with a smaller equivalent resistance ESD circuit, a better FOM can be achieved.

In addition, in the embodiment shown in fig. 2, the circuit device 1 further includes a second signal esd circuit 212 coupled between the first signal pad 210 and the ground power rail P0. The second signal ESD circuit 212 and the first signal ESD circuit 211 can be implemented by different circuits. When the voltage level of the first external signal X received by the first signal pad 210 is lower than the ground power rail P0 (V)_SS) At this time, the first external signal X can be released through the second signal esd circuit 212, the ground power rail P0, and the first

power esd circuits

111, 112, 113.

FIG. 3 is a schematic diagram illustrating a circuit device with electrostatic discharge protection according to a third embodiment of the present invention. In this embodiment, the circuit device 1 further includes a second signal pad 220 for receiving a second external signal Y, and a third signal padA discharge circuit 221 and a fourth signal electrostatic discharge circuit 222. The third signal esd circuit 221 is coupled between the second signal pad 220 and the first power rail P1, and the fourth signal esd circuit 222 is coupled between the second signal pad 220 and the ground power rail P0. When the static electricity is generated from the second signal pad 220, the voltage level of the received second external signal Y is higher than the ground, and the circuit device 1 discharges the second external signal Y through the third signal esd circuit 221, the first power rail P1 and the first power esd circuit 110. When static electricity is generated from the second signal pad 220, the voltage level of the second external signal Y is lower than the voltage level V of the ground power rail P0_SSIn this case, the circuit device 1 can release the second external signal Y through the fourth esd circuit 222, the ground power rail P0, and the first esd circuit 110.

In the embodiment shown in fig. 3, after the target power rail (in this case, the first power rail P1) in the circuit device 1 is selected, the first signal pad 210 and the second signal pad 220 are respectively coupled to the target power rail by respective esd circuits. The voltage range of the first external signal X received by the first signal pad 210 may be different from the voltage range of the second external signal Y received by the second signal pad 220, that is, the signal pad may be coupled to a target power rail of the circuit device 1, which is most likely to successfully discharge ESD, by using an electrostatic discharge circuit, regardless of the voltage range of the external signal received by the signal pad.

For example, the voltage range of the first external signal X may correspond to the voltage level V of the second power rail P2_DDHThe voltage range of the second external signal Y may correspond to the voltage level V of the first power rail P1_DDFor example, the first signal pad 210 and the second signal pad 220 may respectively receive signals from different external circuits, and have different voltage ranges, and in the circuit device 1, the first signal pad 210 and the second signal pad 220 may be respectively coupled to the same first power rail P1 through the first signal ESD circuit 211 and the third signal ESD circuit 221, so as to achieve an optimal FOM for ESD.

FIG. 4 is a schematic representation ofA circuit device with electrostatic discharge protection according to a fourth embodiment of the present invention is shown. In this embodiment, the circuit device 1 further includes a third esd path including a third power rail P3 and a third power esd circuit 130 coupled between the third power rail P3 and the ground power rail P0. In one embodiment, the voltage level V of the third power rail P3_DDLA voltage level V lower than the first power rail P1_DD。

In this embodiment, the circuit arrangement 1 may use more than two power domains, i.e. in addition to V_DDAnd V_DDHBesides, it also includes a voltage level lower than V_DDV of_DDL，V_DDLFor example below 1.8V. The first signal ESD circuit 211 and the third signal ESD circuit 221 are not necessarily coupled to the power rail with the lowest voltage level, but may be coupled to the power rail with the best ESD release capability. For example, the voltage level V of the third power rail P3_DDLAlbeit at a voltage level V higher than that of the first power rail P1_DDHowever, in the circuit device, there may be fewer components using the third power rail P3, and there may be fewer esd circuits coupled between the third power rail P3 and the ground power rail P0, such that the equivalent resistance of all of the at least one first power esd circuits 110 is smaller than that of all of the at least one third power esd circuits 130, and therefore the first power rail P1 is selected as the target power rail, and the first signal pad 210 and the second signal pad 220 are coupled to the first power rail P1 through the first signal esd circuit 211 and the third signal esd circuit 221, respectively.

By using the circuit device of the above embodiment of the invention, a target power rail with the best ESD discharging capability in a multi-power-domain circuit device can be found, and the signal pad is coupled to the target power rail through the electrostatic discharge circuit. Thus, the circuit area required by the power supply electrostatic discharge circuit using the high-voltage power supply rail can be avoided, and high-voltage resistant elements with higher cost can be avoided. And because the target power rail has good ESD release capacity, the circuit device can effectively improve the ESD voltage level, or can achieve the same ESD voltage level by using a lower electrostatic discharge circuit area to achieve better FOM.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A circuit device with electrostatic discharge protection, comprising:

a first signal pad for receiving a first external signal;

a first electrostatic discharge path comprising:

a first power rail;

a first signal electrostatic discharge circuit coupled between the first power rail and the first signal pad; and

at least one first power ESD circuit coupled between the first power rail and a ground power rail; and

a second electrostatic discharge path comprising:

a second power rail; and

at least one second power ESD circuit coupled between the second power rail and the ground power rail;

wherein the voltage level of the first power rail is lower than the voltage level of the second power rail;

when static electricity is generated by the first signal connecting pad, the circuit device selects the first power rail between the first power rail and the second power rail, and the circuit device enables the first signal connecting pad to be coupled to the first power rail through the first signal static electricity discharging circuit so as to release the first external signal through the first static electricity discharging path corresponding to the first power rail.

2. The circuit device of claim 1, wherein an equivalent resistance of all of the at least one first power ESD circuit is less than an equivalent resistance of all of the at least one second power ESD circuit.

3. The circuit arrangement of claim 1, further comprising:

and the second signal electrostatic discharge circuit is coupled between the first signal connecting pad and the grounding power rail.

4. The circuit arrangement of claim 1, further comprising:

a third electrostatic discharge path comprising:

a third power rail; and

at least one third power ESD circuit coupled between the third power rail and the ground power rail;

wherein a voltage level of the third power rail is different from a voltage level of the first power rail.

5. The circuit device of claim 4, wherein an equivalent resistance of all of the at least one first power ESD circuit is less than an equivalent resistance of all of the at least one third power ESD circuit.

6. The circuit arrangement of claim 1, further comprising:

a second signal pad for receiving a second external signal; and

a third signal electrostatic discharge circuit coupled between the second signal pad and the first power rail;

when static electricity is generated by the second signal connecting pad, the second external signal is released through the third signal electrostatic discharge circuit, the first power rail and the at least one first power supply electrostatic discharge circuit.

7. The circuit device as claimed in claim 6, wherein the voltage range of the first external signal received by the first signal pad is different from the voltage range of the second external signal received by the second signal pad.

8. The circuit device of claim 6, wherein a voltage range of the first external signal received by the first signal pad corresponds to a voltage level of the second power rail.

9. The circuit device of claim 8, wherein the voltage range of the second external signal received by the second signal pad corresponds to the voltage level of the first power rail.

10. The circuit arrangement of claim 6, further comprising:

and the fourth signal electrostatic discharge circuit is coupled between the second signal connecting pad and the grounding power rail.