CN101258597A - Integrated circuit with electro-static discharge protection - Google Patents
Integrated circuit with electro-static discharge protection Download PDFInfo
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Abstract
A rail-based Electro- Static Discharge (ESD) protection scheme for multi- voltage-domain Integrated Circuits (ICs) is proposed. Distributed parts of clamp transistors (Tl, T2) for every voltage domain are comprised within each I/O cell (LV IO, HV IO), no matter to which voltage domain it belongs. These clamp transistors are activated using a dedicated power track for each voltage domain. An ESD trigger circuit (TCl, TC2) senses first and second supply voltages and sends signals via respective power tracks to respective first and second clamp devices inside all I/O cells in case an ESD event is detected. The ESD protection scheme according to the invention provides the flexibility in placing circuits and I/O cells on a die of the IC, since it does not matter which voltage domain these I/O cells refer to. The invention is suitable for ICs with considerable difference in supply voltages, e.g. 3 V and 20V.
Description
Technical field
The present invention relates to integrated circuit fields, more specifically, the present invention can be applied in the multivoltage domain integrated circuit.The present invention relates to the electrostatic discharge (ESD) protection field of integrated circuit.The invention provides the electrostatic discharge (ESD) protection of integrated circuit and the electrostatic discharge protection method of integrated circuit with a plurality of supply voltages.
Background technology
The Electrostatic Discharge phenomenon is one of topmost failure mechanism type in the microelectronics industry.In addition, in modern integrated circuits (IC) technology, be target with the high integration.It is very general being integrated in that circuit on the same tube core moves with diverse supply voltage.In this case, must develop the special esd protection that is integrated in IC input and output (I/O) end.This has caused so-called strategy based on pad (Pad-based).A major defect of this strategy is that the protection of operating in so-called " fast quick-recovery (snap-back) " mode of being developed can not be by emulation.Because result that can't emulation component, the development time of the Quick Restorer spare in new process can reach several years.In addition, the fact that these assemblies are operated in " parasitism " mode makes them very responsive for technological parameter and manufacturing step.Therefore, in process transfer (process transfer), be difficult to their behavior of prediction.
As substituting to this problem, another strategy has been proposed in the past few years, be called " based on main line (rail-based) "---reference example: people such as C.A.Torres. " Modular, Portable and Easily Simulated ESD protectionNetworks for advanced CMOS techno1ogies " EOS/ESD Symposium2001.Be based on based on the strategy of main line and use the big clamping device that is connected between positive voltage and the ground.The advantage of this method is can use any business simulation device to carry out emulation, because described clamping device (for example realizing with metal oxide semiconductor transistor (MOST)) is operated under normal mode.
Yet in this optional strategy, trend is to be separated out different power domain---reference example: M.Stockinger in IC, J.W.Miller " Advanced ESD railclamp network design for high voltage CMOS applications ", 2004 by Freescale Semiconductor and T.J.Maloney, S.Dabral, IntelCorporation introduces on EOS/ESD Symposium 95-1-95-12.
The demand that is increasing at IC with a plurality of power domain (different on the certain degree each other), also do not have on a large scale, to propose about the notion of " based on main line ", main because this notion has been introduced among the digital IC such as picture processor, controller, the circuit on wherein nearly all IC all only moves with a kind of supply voltage.The appearance of mixed-signal IC (wherein microcontroller for example can be integrated on the identical tube core with Power Management Unit) requires the principle of " based on main line " is made more complicated consideration.
For example, in Power Management Unit, low-voltage (3V) I/O and high voltage (20V) I/O place on the tube core in the mode of dangerous (hazardous).Here, in order to realize the notion of " based on main line ", guarantee that this identical notion is applied to the voltage domain of 3V and 20V.The problem that this realization produced is an area efficiency.Placement unit can be gone up in power track (track) and produce extra resistance randomly, and this size that need increase the clamping device of distribution compensates.
Summary of the invention
Purpose of the present invention can be regarded as provides a kind of integrated circuit (IC) with esd protection characteristic of improvement.The present invention is limited by independent claims.Dependent claims defines useful embodiment.
In an embodiment, each input and output (I/O) unit comprises the one group of clamping device that is associated with the first and second supply voltage territories (such as 3V and 20V).I.e. all I/O unit of IC preferably, or be most of I/O unit of IC at least, no matter which voltage domain the I/O unit belongs to, and all is equipped with first and second clamping devices, and each clamping device all is suitable for beginning its supply voltage separately of clamp when esd event occurs.Together with special first and second power track or the bus that link to each other with these clamping devices, detecting under the situation of esd event, the ESD circuits for triggering can activate the clamping device that the particular power source voltage in all I/O unit with IC is associated.Like this, all clamping devices of all I/O unit help the clamp in the esd event, for example, provide supply voltage with ESD problem and electrically between short circuit, thereby shunt current is connected to the sensitive circuit and the assembly of this voltage domain with protection.
Be appreciated that first clamping device (for example transistor) preferably suitable for handling first supply voltage, correspondingly, second clamping device is suitable for handling second source voltage.
Described IC is provided at the possibility of placing any input and output (I/O) unit that is associated with any territory in a plurality of supply voltages territory on the tube core of IC randomly.Here the main advantage that produces is the flexibility of placing circuit and I/O unit on tube core, and is unimportant because which voltage domain they relate to.
In addition, described IC provides the possibility that the clamping device of all distributions in use low voltage territory is evacuated the esd event of higher voltage domains.This causes the loose requirement to the size of the rail clamp of this voltage domain in the I/O unit.Notice that supply voltage is high more, transistorized area efficiency is low more, needs more transistor because drive the electric current of equal number.
Therefore, utilize according to IC of the present invention, might also introduce the method based on main line in the mixed-signal IC product, wherein owing to the attribute of its mixed signal, the flexibility of placement becomes necessary.
In addition, rail clamp all can be used for evacuating the esd event on the higher voltage domains, and this causes the less rail clamp of this voltage domain in the I/O unit.In addition, the parasitic track resistance between the I/O unit obviously reduces the influence of esd protection size of component, because all clamping devices (for example transistor) all are used as discharge path, no matter where the pressure of ESD occurs.
In a preferred embodiment, the power track that is suitable for by separately of electro-static discharge trigger circuit activates first and second clamping devices.Like this, first and second power track are used for evacuating the clamping device that has its voltage domain separately in the I/O unit as special esd bus.Because the I/O unit of all distributions all has the clamping device that links to each other with the specific esd bus of its voltage at each voltage domain, the clamping device of all I/O unit all helps to remedy esd event around the IC.Like this, compare, can reduce the width of optimal clamp to a great extent with conventional rail clamp approaches according to prior art.
Electro-static discharge trigger circuit activates first and second clamping devices when surpassing first and second predetermined thresholds separately in first and second values separately of first and second supply voltages that detected.
Suppose that second source voltage greater than first supply voltage, arranges preferred embodiment, make, activate first and second clamping devices in first and second groups of clamping devices when second source voltage during above second predetermined threshold.Especially, the ESD circuits for triggering can be suitable for when second source voltage surpasses second predetermined threshold, activate first clamping device in first and second groups of clamping devices by first power track.In this embodiment, when esd event occurring, utilize first and second clamping devices shunting of I/O unit to produce the ESD voltage that destroys potentially, a large amount of like this clamping devices becomes the part in the protection process.
First clamping device of first and second groups of clamping devices can be suitable for by first power track first supply voltage being connected to electrically when activating.Similarly, second clamping device of first and second groups of clamping devices can be suitable for by the second source path second source voltage being connected to electrically when activating.Yet in a preferred embodiment, second clamping device is suitable for second source voltage is connected to first supply voltage.Thus, can utilize first and second clamping devices (for example transistor), when the esd event of second source voltage occurring, participate in evacuating.Like this, be higher than at second source voltage under the situation of first supply voltage, the total voltage span (span) of second source voltage can be divided between first and second clamping devices, and does not also need to handle the signal transistor of second source voltage.Thus, clamping device (for example transistor) can be designed to littler size, has therefore saved the space.
Preferably, clamping device comprises the transistor that is connected to power track, and the ESD circuits for triggering are when detecting esd event, send signal by power track, purpose is in order to open (open) transistor, clamp supply voltage then, and make the influence of esd event thus up.
In simple embodiment, the ESD circuits for triggering comprise that transistor is to, two resistors and two capacitors.Preferably, transistor is to comprising PMOST and NMOST.
First input-output unit can comprise the input/output pads that is connected to first supply voltage by first diode, and this input/output pads also is connected to electrically by second diode.These diodes will be described in the back in further detail as the part of esd protection.
First and second input-output units can all be positioned on the tube core of integrated circuit.Like this, utilize IC, might be provided at the IC of a plurality of circuit of the supply voltage that has mixing on the single tube core with described esd protection feature.
With reference to this first aspect, be understandable that the preferred embodiment of integrated circuit can comprise usually according to the defined a plurality of input-output units of first aspect.In addition, be appreciated that substantially, the principle of this first aspect helps being suitable for the embodiment of the integrated circuit of a plurality of different electrical power voltages usually, and just the voltage domain of Hun Heing for example operates in the digital circuit of 3V or 5V and operates in the more analog circuit of high power supply voltage (such as 10V or 20V).
In second aspect; the invention provides electrostatic discharge protection method to integrated circuit with a plurality of input-output units; described integrated circuit is connected to first and second supply voltages; described method comprises the steps: to detect the value of first supply voltage; when the value of first supply voltage surpasses first predetermined threshold; on first power track, send first activation signal; and when receiving first activation signal, activate the clamping device that is arranged in a large amount of at least unit of a plurality of input-output units.
To a large amount of at least understanding in a plurality of input-output units be, for example greater than 50% in the I/O unit, be preferably more than 60% in the I/O unit, more preferably greater than 70% in the I/O unit, more preferably greater than 80% in the I/O unit, most preferably greater than 90% in the I/O unit, such as all I/O unit.
Method according to second aspect is favourable, because use special power track and be distributed in that the clamping device in a large amount of at least unit obtains esd protection in the I/O unit among the IC, has obtained more efficiently ESD clamp thus.Preferred embodiment further describe in detail and other advantages will with description that the IC of first aspect is associated in find out.
Suppose that second source voltage is greater than first supply voltage, this method preferably also comprises the steps: to detect the value of second source voltage, when the value of second source voltage surpasses second predetermined threshold, on the second source path, send activation signal, and when receiving second activation signal, activate second clamping device that is arranged in a large amount of at least unit of a plurality of input-output units.Preferably, when second source voltage surpassed predetermined threshold, first and second clamping devices all were activated.Therefore, occurring under the situation of esd event, might be by on power track separately, activating to utilize first and second clamping devices to participate in the clamp of second (promptly higher) supply voltage.This is for using transistor to realize that clamping device is favourable.
The present invention advantageously is applied to comprise in the equipment according to integrated circuit of the present invention.This equipment can be any electronic equipment that comprises the integrated circuit that is connected to a plurality of supply voltages, for example Power Management Unit, microcontroller, digital signal processor, automobile-used integrated circuit etc.This equipment is any wireless and/or battery powered product on can be usually.This equipment for example can be audio frequency apparatus, video equipment, mobile phone, MP3 player or digital camera.
Description of drawings
Next, by coming more at large to describe the present invention with reference to the accompanying drawings, wherein,
Fig. 1 shows the esd protection schematic diagram of the IC of prior art, and this IC has based on pad with based on the framework of main line, and the example of the position of the I/O unit of Power Management Unit.
Fig. 2 shows the schematic diagram of the preferred esd protection part of the IC that is connected to two supply voltages,
Fig. 3 shows the circuit diagram of the preferred esd protection circuit part of the IC that is connected to two supply voltages, and
Fig. 4 shows the circuit diagram of the preferred simple embodiment of ESD circuits for triggering.
Embodiment
The top of Fig. 1 shows under IC P_B and the IC R_B situation based on main line based on pad, the ESD clamp route (route) of the prior art between o pads OUT and ground GND.In IC P_B based on pad, use so-called snap-back clamp, the directapath from o pads OUT to ground GND is provided.If allow to have the snap-back clamp of robustness, then this esd protection scheme is firm.But, can not carry out emulation to this snap-back clamp.
In the IC R_B based on main line, the non-snap-back clamp of distribution is used for a plurality of I/O are carried out esd protection, like this, and usually can be elongated from OUT through the clamp path of VDD to GND.This can be by emulation, but this method causes big clamping device, can not place I/O easily on IC.
The bottom of Fig. 1 shows the example of the plane graph of Power Management Unit IC, and this IC has low power domain I/O LP_IO (for example 3V) and high power domain I/O HP_IO (for example 20V), is positioned on the IC tube core in the mode of danger.In order to realize notion in this example, must in two power domain, use identical notion based on main line.The resistance that increases owing to long power track must be by the ESD clamping device that distributes the size of increase compensate.This problem can be along with the increase of the quantity of the different voltage domains that occurred and is increased.
Fig. 2 shows preferred embodiment according to the esd protection relevant portion of IC of the present invention in the mode of signal.The first and second I/O unit LV_IO, HV_IO are indicated by dotted line, and each includes first clamping device T1 that is connected to the first supply voltage Vdd1 and the second clamping device T2 that is connected to second source voltage Vdd2.Connect ESD circuits for triggering TC, to detect the first and second supply voltage Vdd1, Vdd2.These circuits for triggering TC is connected to special power track RCB1, RCB2, these power track also are connected to the first and second clamping device T1, T2 separately, like this, circuits for triggering TC can activate clamping device T1, T2 separately by power track RCB1, RCB2 separately, to respond by the detected esd event of circuits for triggering TC.Only for illustrative purposes, first and second clamping devices shown in Fig. 3 have the ground symbol.This ground symbol indication clamping device T1, T2 will be separately supply voltage Vdd1, Vdd2 clamp to ground when activating.May be like this, but can be explained further below, at least the second clamping device T2 preferably otherwise be connected.
Circuit as shown in Figure 2 can provide esd protection: the value that detects the first supply voltage Vdd1 in the following way; When the value of the first supply voltage Vdd1 surpasses first predetermined threshold, on the first power track RCB1, send first activation signal; And behind first activation signal that receives on the first power track RCB1, activation is arranged in the first a large amount of at least clamping device T1 of a plurality of input-output unit LV_IO, HV_IO.Similarly, can provide esd protection in the following way: the value that detects second source voltage Vdd2; When the value of second source voltage Vdd2 surpasses second predetermined threshold, on second source path RCB2, send activation signal; And after receiving second activation signal, activation is arranged in the second a large amount of at least clamping device T2 of a plurality of input-output unit LV_IO, HV_IO.
Fig. 3 more at large shows the schematic diagram of the preferred embodiment of the relevant circuit of the esd protection of the IC with three I/O unit, and each I/O unit is shown by dashed lines: power supply I/O cell S UPP_IO; I/O unit LV_IO has the pad PAD1 that is associated with first (lower) supply voltage Vdd1; And I/O unit HV_IO, have the pad PAD2 that is associated with second (higher) supply voltage Vdd2.ESD circuits for triggering separated into two parts TC1, TC2 are arranged in power supply I/O cell S UPP_IO.Connect this circuits for triggering part TC1, TC2, to detect the first and second supply voltage Vdd1, Vdd2 separately.In addition, described circuits for triggering TC1, TC2 are connected to the first and second power track RCB1, RCB2 separately, the special esd bus of each voltage domain Vdd1, Vdd2 just, wherein after detecting esd event on supply voltage Vdd1, the Vdd2 separately, circuits for triggering TC1, TC2 send ESD and evacuate (evacuation) signal on this power track.
Power track RCB1, RCB2 guide all I/O cell S UPP_IO, LV_IO, HV_IO into.All I/O cell S UPP_IO, LV_IO, HV_IO are placed with the first and second clamping device T1, the T2 at each voltage domain Vdd1, Vdd2.This clamping device T1, T2 are preferably with transistor realization, the preferably transistor of MOST type.The described first and second clamping device T1, T2 separately is connected to power track RCB1, RCB2 separately, therefore can activate independently.
The first and second voltage Vdd1, Vdd2 may be very different, for example Vdd1=3V, Vdd=20V.Therefore, path clamping device T1, the T2 of described distribution must be applicable to power domain separately.Like this, in Fig. 3, T1, A1, B1 are low-voltage (for example 3V) assemblies, and T2, A2, B2 are high voltage (for example 20V) assemblies.
Each I/O cell S UPP_IO, LV_IO, HV_IO (no matter which voltage domain Vdd1, Vdd2 belong to) comprise identical protective transistor (being T1, T2 in this case).Transistor T 1 is shunted (shunt) to ground Vss with electric current from Vdd1 as the clamping device that is applied to the esd event of I/O unit, LVPS territory (being LV_IO or SUPP_IO).Transistor T 2 branches to Vdd1 then to ground Vss with electric current from Vdd2 as the clamping device that is applied to the esd event of I/O unit, high-voltage power supply territory.
In addition, described principle has been guaranteed the current path at all possible pressure (stress) combination:
1) for positive " beating (zap) " of (belonging to different voltage domains) between PAD1 and the PAD2, electric current will flow through diode A1 and arrive Vdd1.When on the Vdd1 power track, esd event occurring, be placed on the clamping transistor T1 that circuits for triggering TC1 among the power supply I/O SUPP_IO will detect all distributions of this incident and this power domain of conducting Vdd1.All transistor Ts 1 will be connected concurrently and electric current is branched to ground Vss.Then, electric current flows through ground Vss power track, finally passes through diode B2, and will arrive PAD2.
2) for negative " the beating " between PAD1 and the PAD2, electric current will flow through from diode A2 and arrive Vdd2.When esd event occurring on the Vdd2 power track, the circuits for triggering TC2 that is placed among the power supply I/O SUPP_IO will detect this incident and all high voltage transistor T2 of conducting.These transistor Ts 2 will be connected concurrently and electric current will be diverted to Vdd1.When instantaneous signal arrives Vdd1, the circuits for triggering TC1 of low voltage domain Vdd1 will detect it, and activate the rail clamp transistors T1 that all low voltage domain Vdd1 distribute, and its electric current is diverted to ground Vss from Vdd1.Finally, electric current also flows through ground Vss path and diode B1 arrival PAD1.
The advantage of the circuit among Fig. 3 is, voltage on the Vdd2 path (being applied to top transistorized grid) keeps Vgs enough high, allow transistor T 2 under the situation of low-voltag transistor, " to open (open) " more, thereby shunt more electric current with less size.
Fig. 4 shows the preferred embodiment of the part of circuits for triggering, promptly from the TC1 or the TC2 of circuit shown in Figure 3.These circuits for triggering comprise that transistor is to T11, T12 (preferably PMOST/NMOST to) and two resistor-capacitor circuit group R11, C11, R12, C12.NMOSTT12 is connected between supply voltage Vdd and the ground Vss, and PMOST T11 is connected between supply voltage Vdd and the resistor R 12.
During positive esd event, supply voltage Vdd increases rapidly.Transient current flows into and triggers resistor R 11 and give capacitor C11 charging.In this instantaneous process, the grid-source voltage (Vgs) that resistor R 11 two ends manifest drives PMOST T11 and is higher than its threshold values, triggers power unit thus and connects.The ESD electric current will flow to ground Vss from Vdd.In instantaneous process end, when triggering capacitor C11 and be recharged, owing to disappear by the electric current of resistor R 11, so Vgs voltage drops to zero, and the PMOST T11 part of cutting off the electricity supply.
Select RC part R12, C12 at quick response.R11 and C11 need keep NMOST T12 to disconnect in the whole duration of esd pulse, just, their time constant must be chosen as the duration much larger than esd pulse.On the other hand, circuits for triggering need prevent that power unit is activated during normally the powering on of IC, and this is usually in the 0.3-0.5 scope of second.Time constant is preferred for 0.5-2 second, such as 0.8-1.2 second, most preferably is about 1 second.Like this, the typical components values that realizes this time constant is: R11=500kOhm and C11=2pF.
By the description to the possible implementation of circuits for triggering, the technical staff will know how to realize the circuits for triggering TC1 and the TC2 that are equal to Fig. 3.
The preferred embodiments of the present invention list in following table with the advantage that traditional path clamp is compared-at high voltage and low voltage domain.In following table, the fixed resistance R between supply voltage and the ground shows the optimal clamp width.
As can be seen from the table, under low voltage domain and high voltage domain situation, obviously less according to the optimal clamp width of esd protection scheme of the present invention.This means that the size for clamping transistor has had more loose requirement.
With reference to all embodiment, should be understood that the circuit with two voltage domains of simple description can be cascaded in principle, be used to have three thus, four, five or even the IC of more a plurality of different electrical power voltages.This also sets up for the clamping device of each I/O unit and circuits for triggering, wherein the technical staff can expand to be fit to any amount of voltage domain it easily, thereby the clamping device that can learn all voltage domains is included in the I/O unit, and preferably with the clamp that all participates in than corresponding all clamping devices of low supply voltage than the esd event of high power supply voltage.Like this, preferred embodiment comprises the IC that is applicable to three different electrical power voltages of connection.For example, these three different electrical power voltages can be: a digital circuit part that is used for IC, an artificial circuit part that is used for IC also has a circuit part that is used for by the external charger power supply, for example generally uses in digital camera, MP3 player and mobile phone.
To being summarized as follows of preferred embodiment.A kind of Electrostatic Discharge protection scheme based on main line at multivoltage domain integrated circuit (IC) has been proposed.Distribution at the clamping transistor (T1, T2) of each voltage domain partly is included in each I/O unit (LV_IO, HV_IO), and no matter which voltage domain it belongs to.At each voltage domain, use special power track to activate these clamping transistors.ESD circuits for triggering (TC1, TC2) detect first and second supply voltages, and are detecting separately the first and second clamping devices transmission signal of power line in all I/O unit that passes through under the situation of esd event separately.In a preferred embodiment, be included in the I/O unit at the clamping device of all voltage domains, and preferably, with the clamp that participates in than corresponding all clamping devices of low supply voltage than the esd event of high power supply voltage.Preferably, each I/O unit has first clamping transistor (T1) that is suitable for carrying out clamp when activating between first supply voltage and ground, and second clamping transistor (T2) that is suitable for carrying out clamp when activating between second (higher) supply voltage and first voltage.Because these first and second clamping transistors are shared total (higher) supply voltage, so their size can be reduced.Owing to used method, can carry out emulation to the characteristic of esd protection circuit based on main line.Esd protection scheme according to the present invention provides the flexibility of placing circuit and I/O unit on the tube core of IC, because the voltage domain that these I/O unit relate to can not exert an influence.The present invention is suitable for that a great difference is arranged on the supply voltage IC of (for example 3V and 20V).
Should, the present invention is not limited to embodiment above-mentioned, and under the prerequisite of the scope that does not deviate from claims, those skilled in the art can design many optional embodiments.In the claims, be placed on Reference numeral between the bracket and should not be construed as restriction claim.Speech " comprises " that not getting rid of those is listed in the element beyond the claim or the existence of step.Speech " " or " one " before the element do not get rid of the existence that many this elements are arranged.The present invention can realize by means of the hardware that comprises some different elements, and/or realize by means of the processor of suitably programming.In enumerating the equipment claim of some devices, some in these devices can be embodied by same hardware.The minimum fact is that the certain measures of narrating in different mutually dependent claims does not represent that the combination of these measures can not produce advantage.
Claims (11)
1. an integrated circuit is suitable for being connected to first and second supply voltages (Vdd1, Vdd2), and described integrated circuit comprises:
Electro-static discharge trigger circuit (TC1, TC2) is connected to and detects described first and second supply voltages (Vdd1, Vdd2), and described electro-static discharge trigger circuit (TC1, TC2) is also connected to first and second power track (RCB1, RCB2) separately,
First input-output unit (LV_IO), comprise first input/output pads (PAD1) that is associated with described first supply voltage (Vdd1), described first input-output unit (LV_IO) comprises first group first and second clamping devices (T1, T2) of first and second power track (RCB1, RCB2) that are connected to separately, and
Second input-output unit (HV_IO), comprise second input/output pads (PAD2) that is associated with described second source voltage (Vdd2), described second input-output unit (HV_IO) comprises second group first and second clamping devices (T1, T2) of first and second power track (RCB1, RCB2) that are connected to separately.
2. integrated circuit according to claim 1, wherein, first and second power track (RCB1, RCB2) that described electro-static discharge trigger circuit (TC1, TC2) is suitable for by separately activate described first and second clamping devices (T1, T2).
3. integrated circuit according to claim 1, wherein, described electro-static discharge trigger circuit (TC1, TC2) is suitable for activating described first and second clamping devices (T1, T2) when first and second supply voltages that detected (Vdd1, Vdd2), first and second values separately surpass separately first and second predetermined thresholds.
4. integrated circuit according to claim 1, wherein, described second source voltage (Vdd2) is greater than described first supply voltage (Vdd1), and when described second source voltage (Vdd2) surpassed described second predetermined threshold, described first and second clamping devices (T1, T2) in described first and second groups of clamping devices all were activated.
5. integrated circuit according to claim 4, wherein, when described second source voltage (Vdd2) surpassed described second predetermined threshold, described electro-static discharge trigger circuit (TC1, TC2) was suitable for activating described first clamping device (T1) in described first and second groups of clamping devices by described first power track (RCB1).
6. integrated circuit according to claim 1, wherein, described first clamping device (T1) in described first and second groups of clamping devices is suitable for when activation described first supply voltage (Vdd1) being connected to ground (Vss), and described second clamping device (T2) in described first and second groups of clamping devices is suitable for when activating described second source voltage (Vdd2) being connected to described first supply voltage (Vdd1).
7. integrated circuit according to claim 1, wherein, described electro-static discharge trigger circuit (TC) comprises that transistor is to (T11, T12), two resistors (R11, R12) and two capacitors (C11, C12).
8. integrated circuit according to claim 1, wherein, described first and second input-output units (LV_IO, HV_IO) comprise the input/output pads separately (PAD1, PAD2) that is connected to first and second supply voltages (Vdd1, Vdd2) separately by first and second diodes (A1, A2) separately, and described input/output pads (PAD1, PAD2) separately also third and fourth diode (B1, B2) by separately is connected to ground (Vss).
9. integrated circuit according to claim 1, wherein, described first and second input-output units (LV_IO, HV_IO) all are positioned on the tube core of described integrated circuit.
10. the electrostatic discharge protection method of an integrated circuit, described method comprises step:
Detect the value of supply voltage,
When the value of described supply voltage surpasses predetermined threshold, on power track, send activation signal, and
When receiving described activation signal, activate the clamping device that is arranged in a plurality of input-output units.
11. method according to claim 10 also comprises step:
Detect the value of the second source voltage different with described supply voltage,
When the value of described second source voltage surpasses second predetermined threshold, on the second source path, send second activation signal, and
When receiving described second activation signal, activate second clamping device that is arranged in described a plurality of input-output units.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05106282.6 | 2005-07-08 | ||
| EP05106282 | 2005-07-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101258597A true CN101258597A (en) | 2008-09-03 |
Family
ID=37452831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800327233A Pending CN101258597A (en) | 2005-07-08 | 2006-07-04 | Integrated circuit with electro-static discharge protection |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1905084A2 (en) |
| JP (1) | JP2009500840A (en) |
| CN (1) | CN101258597A (en) |
| WO (1) | WO2007007237A2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102257731A (en) * | 2008-12-18 | 2011-11-23 | 桑迪士克股份有限公司 | Electrostatic discharge protective circuit having rise time detector and discharge sustaining circuitry |
| CN102457053A (en) * | 2010-10-18 | 2012-05-16 | 联咏科技股份有限公司 | Electrostatic discharge protection device applicable to multi-voltage system |
| CN103001206A (en) * | 2012-09-25 | 2013-03-27 | 香港应用科技研究院有限公司 | Electrostatic discharge (ESD) power clamp for clamping high-voltage power supply in mixed-voltage chip by means of low-voltage transistor |
| CN104160447A (en) * | 2011-11-01 | 2014-11-19 | 硅存储技术公司 | A mixed voltage non-volatile memory integrated circuit with power saving |
| CN105656017A (en) * | 2014-11-13 | 2016-06-08 | 旺宏电子股份有限公司 | Protection circuit and input circuit suitable for integrated circuit |
| CN105977938A (en) * | 2016-06-17 | 2016-09-28 | 中国电子科技集团公司第二十四研究所 | ESD protection circuit for chip |
| CN106415818A (en) * | 2014-06-20 | 2017-02-15 | 哉英电子股份有限公司 | Semiconductor device |
| CN110138375A (en) * | 2018-02-02 | 2019-08-16 | 华为技术有限公司 | A kind of circuit for chip pin |
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| JP5562246B2 (en) * | 2007-10-30 | 2014-07-30 | アギア システムズ インコーポレーテッド | ESD protection circuit |
| EP2238686A1 (en) | 2008-01-29 | 2010-10-13 | Nxp B.V. | Electronic clamps for integrated circuits and methods of use |
| DE102008001368A1 (en) * | 2008-04-24 | 2009-10-29 | Robert Bosch Gmbh | Electrostatic discharge protective circuit for protecting series circuit, has electrostatic discharge transistor that is controlled by single transistor which is controlled by inverter with inverted potential of center tap |
| FR2955699B1 (en) * | 2010-01-26 | 2013-08-16 | St Microelectronics Rousset | PROTECTIVE STRUCTURE OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES |
| CN106533419B (en) * | 2016-10-12 | 2022-11-01 | 格科微电子（上海）有限公司 | ESD protection circuit and clock path of MIPI interface |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5946177A (en) * | 1998-08-17 | 1999-08-31 | Motorola, Inc. | Circuit for electrostatic discharge protection |
| US20030076636A1 (en) * | 2001-10-23 | 2003-04-24 | Ming-Dou Ker | On-chip ESD protection circuit with a substrate-triggered SCR device |
| JP3908669B2 (en) * | 2003-01-20 | 2007-04-25 | 株式会社東芝 | Electrostatic discharge protection circuit device |
| US6970336B2 (en) * | 2003-10-10 | 2005-11-29 | Freescale Semiconductor, Inc. | Electrostatic discharge protection circuit and method of operation |
| DE102004004789B3 (en) * | 2004-01-30 | 2005-03-03 | Infineon Technologies Ag | Electrostatic discharge protection circuit for electronic circuit with several supply voltages has control bus connecting protection element control inputs, overvoltage detector controlling bus depending on potential at first supply node |
-
2006
- 2006-07-04 CN CNA2006800327233A patent/CN101258597A/en active Pending
- 2006-07-04 JP JP2008520044A patent/JP2009500840A/en not_active Withdrawn
- 2006-07-04 WO PCT/IB2006/052252 patent/WO2007007237A2/en active Application Filing
- 2006-07-04 EP EP06766003A patent/EP1905084A2/en not_active Withdrawn
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102257731A (en) * | 2008-12-18 | 2011-11-23 | 桑迪士克股份有限公司 | Electrostatic discharge protective circuit having rise time detector and discharge sustaining circuitry |
| CN102457053A (en) * | 2010-10-18 | 2012-05-16 | 联咏科技股份有限公司 | Electrostatic discharge protection device applicable to multi-voltage system |
| US9378838B2 (en) | 2011-11-01 | 2016-06-28 | Silicon Storage Technology, Inc. | Mixed voltage non-volatile memory integrated circuit with power saving |
| CN104160447A (en) * | 2011-11-01 | 2014-11-19 | 硅存储技术公司 | A mixed voltage non-volatile memory integrated circuit with power saving |
| CN104160447B (en) * | 2011-11-01 | 2016-10-12 | 硅存储技术公司 | There is the mixed-voltage nonvolatile memory integrated circuit that power is saved |
| CN103001206B (en) * | 2012-09-25 | 2014-12-24 | 香港应用科技研究院有限公司 | Electrostatic discharge (ESD) power clamp for clamping high-voltage power supply in mixed-voltage chip by means of low-voltage transistor |
| CN103001206A (en) * | 2012-09-25 | 2013-03-27 | 香港应用科技研究院有限公司 | Electrostatic discharge (ESD) power clamp for clamping high-voltage power supply in mixed-voltage chip by means of low-voltage transistor |
| CN106415818A (en) * | 2014-06-20 | 2017-02-15 | 哉英电子股份有限公司 | Semiconductor device |
| CN106415818B (en) * | 2014-06-20 | 2019-06-25 | 哉英电子股份有限公司 | Semiconductor device |
| US10504860B2 (en) | 2014-06-20 | 2019-12-10 | Thine Electronics, Inc. | Semiconductor device |
| CN105656017A (en) * | 2014-11-13 | 2016-06-08 | 旺宏电子股份有限公司 | Protection circuit and input circuit suitable for integrated circuit |
| CN105977938A (en) * | 2016-06-17 | 2016-09-28 | 中国电子科技集团公司第二十四研究所 | ESD protection circuit for chip |
| CN110138375A (en) * | 2018-02-02 | 2019-08-16 | 华为技术有限公司 | A kind of circuit for chip pin |
| CN110138375B (en) * | 2018-02-02 | 2021-08-27 | 华为技术有限公司 | Circuit for chip pin |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007007237A3 (en) | 2007-03-29 |
| EP1905084A2 (en) | 2008-04-02 |
| JP2009500840A (en) | 2009-01-08 |
| WO2007007237A2 (en) | 2007-01-18 |
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