EP1905084A2

EP1905084A2 - Integrated circuit with electro-static discharge protection

Info

Publication number: EP1905084A2
Application number: EP06766003A
Authority: EP
Inventors: Igor Simonovic; Sasa Ristic; Yorgos Christoforou
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2005-07-08
Filing date: 2006-07-04
Publication date: 2008-04-02
Also published as: CN101258597A; WO2007007237A3; JP2009500840A; WO2007007237A2

Abstract

A rail-based Electro- Static Discharge (ESD) protection scheme for multi- voltage-domain Integrated Circuits (ICs) is proposed. Distributed parts of clamp transistors (Tl, T2) for every voltage domain are comprised within each I/O cell (LV IO, HV IO), no matter to which voltage domain it belongs. These clamp transistors are activated using a dedicated power track for each voltage domain. An ESD trigger circuit (TCl, TC2) senses first and second supply voltages and sends signals via respective power tracks to respective first and second clamp devices inside all I/O cells in case an ESD event is detected. The ESD protection scheme according to the invention provides the flexibility in placing circuits and I/O cells on a die of the IC, since it does not matter which voltage domain these I/O cells refer to. The invention is suitable for ICs with considerable difference in supply voltages, e.g. 3 V and 20V.

Description

Integrated circuit with electro-static discharge protection

FIELD OF THE INVENTION

The invention relates to the field of integrated circuits, more specifically the invention is applicable within multi- voltage-domain integrated circuits. The invention relates to the field of electro-static discharge protection of integrated circuits. The invention provides electro-static discharge protection of an integrated circuit with a plurality of supply voltages and a method for electro-static discharge protecting an integrated circuit.

BACKGROUND OF THE INVENTION

Electro-static Discharge (ESD) phenomena are one of the most important types of failure mechanisms in the microelectronics industry. Additionally, in modern integrated circuit (IC) processes, where the aim is a high level of integration, circuits integrated on the same die that run on very different supply voltages have become quite common. In such cases special ESD protections that are integrated on the input-output (I/O) side of the IC must be developed. This leads to the so-called Pad-based strategy. One of the main disadvantages of this strategy is the fact that the developed protections operate in a regime called "snap-back" which cannot be simulated. As consequence of the non-possibility to simulate the component, snapback devices development time in a new process can be as long as several years. Additionally, the fact that these components operate in a "parasitic" regime makes them very sensitive to process parameters as well as to fabrication steps. Therefore it is difficult to predict their behavior in case of process transfer.

As an alternative to this problem, it has been developed the last years, an alternative strategy named "rail-based" - see e.g.: C. A. Torres et al. "Modular, Portable and Easily Simulated ESD protection Networks for advanced CMOS technologies" EOS/ESD Symposium 2001. The rail-based strategy is based on the use of a big clamp connected between the positive supply and the ground. The advantage of this approach is that it can be simulated with any commercial simulator, since the clamp, e.g. implemented with a Metal- Oxide- Semiconductor Transistor (MOST), operates in normal mode.

In this alternative strategy nevertheless, the trend is to separate the different power domains in an IC - see e.g.: M. Stockinger, J. W. Miller "Advanced ESD rail clamp network design for high voltage CMOS applications", presentation by Freescale Semiconductor, 2004, and T. J. Maloney, S. Dabral, Intel Corporation, EOS/ESD Symposium 95-1 - 95-12.

The increasing demand, though, for ICs with various power domains (which vary considerably with each other) is not yet addressed in a big scale with respect to the "rail- based" concept, mainly because this concept has been introduced for digital ICs like processors, controllers, etc., where almost all the circuits on an IC run on one supply voltage only. The advent though of the mixed-signal ICs, where a micro-controller can, for instance, be integrated on the same die as the power management unit, requires a more complicated consideration of the "rail-based" principle.

For instance, in a power management unit low voltage (3 V) I/Os and a high voltage (20V) I/Os are placed in a hazardous way on the die. To implement the "rail-based" concept here one has to make sure that this same concept is applied at both the 3 V and the 20V domains. A problem with this implementation is area efficiency. The random placement of the cells creates additional resistance on the supply tracks that has to be compensated by the increase of the dimensions of the distributed clamps.

SUMMARY OF THE INVENTION

It may be seen as an object of the present invention to provide an integrated circuit (IC) with improved ESD protection properties. The invention is defined by the independent claims. The dependent claims define advantageous embodiments.

In an embodiment, each of the input-output (I/O) cells comprises a set of clamp devices associated with the first and second supply voltage domain (e.g. 3V and 20V). I.e. preferably all the I/O cells, or at least a majority of the I/O cells of the IC, no matter which supply voltage the I/O cell belongs to, are equipped with first and second clamp devices each begin adapted to clamp their respective supply voltages in case of an ESD event. Together with the dedicated first and second power tracks or buses connected to these clamp devices, it is possible for the ESD trigger circuit to activate the clamp devices associated with a specific supply voltage in all I/O cells of the IC in case an ESD event is detected. Thus, all clamp devices of all I/O cells can be used to contribute to clamping in

ESD events, e.g. provide a short circuit between the supply voltage with an ESD problem and electrical ground, thus shunting current protecting the sensible circuits and components connected to that voltage domain. It is to be understood that the first clamp devices, e.g. transistors, are preferably adapted to handle the first supply voltage, while accordingly the second clamp devices are adapted to handle the second supply voltage.

The IC may provide the possibility to place any input-output (I/O) cell associated with any of a plurality of supply voltage domains randomly on a die of the IC. The main resulting advantage here is flexibility in placing circuits and I/O cells on the die, since it is not important to which voltage domain they refer.

In addition, the IC may provide the possibility to use all distributed clamps of a lower voltage domain to evacuate ESD events on a higher voltage domain. This leads to a relaxed requirement for rail clamp size of this voltage domain in the I/O cell. Notice that the higher the supply voltage, the less area efficient is a transistor, since to drive the same amount of current more transistor area is required.

Thus, with an IC according to the invention, it may be possible to introduce the rail-based approach also in the mixed-signal IC products where placement flexibility is a must because of their mixed-signal nature.

Furthermore, the fact that both rail clamps can be used for evacuating ESD events on the higher voltage domain leads to a smaller rail clamp of this voltage domain in the I/O cell. In addition, the influence of parasitic track resistance between I/O cells on the size of the ESD protection elements is significantly reduced, since all clamp devices, e.g. transistors, are used as discharge paths no matter where the ESD stress appears.

In preferred embodiments, the electro-static discharge trigger circuit is adapted to active the first and second clamp devices via the respective power tracks. Thus, the first and second power tracks serve as dedicated ESD buses that are used to evacuate clamp devices of their respective voltage domain in the I/O cells. Since all distributed I/O cells have for each voltage domain a clamp device that is connected to its voltage specific ESD bus, clamp device of all I/O cells around the IC can contribute to remedy an ESD event. Thus, compared to conventional rail clamp approaches according to prior art, a width of an optimal clamp can be considerably reduced.

The electro-static discharge trigger circuit is preferably adapted to activate the first and second clamp devices upon respective first and levels of the sensed first and second supply voltages exceeding respective first and second predetermined threshold values.

Assuming that the second supply voltage is larger than the first supply voltage, preferred embodiments are arranged so that the first and second clamp devices of both the first and second set of clamp devices are activated upon the second supply voltage exceeding the second predetermined threshold value. Especially, the ESD trigger circuit may be adapted to activate the first clamp devices of both the first and second set of clamp devices via the first power track, upon the second supply voltage exceeding the second predetermined threshold value. In such embodiments both of the first and second clamp devices of the I/O cells are utilized upon an ESD event to shunt the potentially damaging ESD voltage, thus a larger number of clamp devices are part of the protection process.

The first clamp device of the first and second sets of clamp devices may be adapted to connect the first supply voltage to electrical ground upon activation via the first power track. Likewise, the second clamp devices of the first and second sets of clamp devices may be adapted to connect the second supply voltage to electrical ground upon activation via the second power track. However, in preferred embodiments, the second clamp devices are adapted to connect the second supply voltage to the first supply voltage. Hereby, it is possible to utilize both the first and second clamp devices, e.g. transistors, to participate in the evacuation in case of an ESD event of the second supply voltage. Thus, where the second supply voltage is higher than the first supply voltage, the total voltage span of the second supply voltage can be split between the first and second clamp devices, and there will be no need for a signal transistor that can handle the second supply voltage. Hereby, the clamp devices, e.g. transistors, can be designed smaller in size thereby saving space.

Preferably the clamp devices comprises a transistor connected to the power track, the ESD trigger circuit sending a signal via the power track upon an ESD event being detected with the purpose of opening the transistor that will then clamp the supply voltage and thus remedy the effect of the ESD event.

In a simple embodiment, the ESD trigger circuit comprises a transistor pair, two resistors, and two capacitors. Preferably the transistor pair comprises a PMOST and an NMOST.

The first input-output cell may comprise an input-output pad connected to the first supply voltage via a first diode, the input-output pad further being connected to electrical ground via a second diode. The diodes serve as part of the ESD protection as will be described in more details later. The first and second input-output cells may be both located on one die of the integrated circuit. Thus, with an IC with the ESD protection features as described, it is possible to provide an IC with a plurality of circuits with mixed supply voltages on a single die. Referring to this first aspect, it is to be understood that preferred embodiments of the integrated circuit might generally comprise a plurality of input-output cells as those defined according to the first aspect. Additionally, it is to be understood that generally, the principles of the first aspect is generally advantageous for integrated circuit embodiments adapted for a plurality of different supply voltages, i.e. mixed voltage domains, such as e.g. digital circuits running at 3V or 5V and analog circuits running at higher supply voltages such as 10V or 20V.

In a second aspect, the invention provides a method of electro-static discharge protecting an integrated circuit with a plurality of input-output cells, the integrated circuit being connected to first and second supply voltages, the method comprising the steps of: sensing a level of the first supply voltage, sending a first activation signal on a first power track upon the level of the first supply voltage exceeding a first predetermined threshold value, and activating a first clamp device located in at least a substantial number of the plurality of input-output cells by receipt of the first activation signal. By a substantial number of the plurality of input-output cells is understood such as more than 50% of the I/O cells, preferably more than 60% of the I/O cells, more preferably 70% of the I/O cells, more preferably 80% of the I/O cells, most preferably 90% of the I/O cells, such as all of the I/O cells.

The method according to the second aspect is advantageous since ESD protection is obtained with using a dedicated power track and clamp devices distributed in at least a substantial part of the I/O cells of the IC, and thus a more efficient ESD clamping is the result. A further elaboration on preferred embodiments and further advantages might be seen in the description in connection with the IC of the first aspect.

With the assumption that the second supply voltage is larger than the first supply voltage, the method preferably further comprises the steps of sensing a level of the second supply voltage, sending an activation signal on the second power track upon the level of the second supply voltage exceeding a second predetermined threshold value, and activating a second clamp device located in at least a substantial number of the plurality of input-output cells by receipt of the second activation signal. Preferably, both first and second clamp devices are activated upon the second supply voltage exceeding the predetermined threshold value. Hereby it is possible to utilize both first and second clamp devices by activation on separate power tracks to participate in clamping the second, i.e. the higher, supply voltage in case of an ESD event. This is advantageous in respect of clamp device implementation using transistors. The invention is advantageously applied in a device comprising an integrated circuit according to the invention. The device may be any electronic device that comprises an integrated circuit connected to a plurality of supply voltages, such as a power management unit, a microprocessor, a digital signal processor, an integrated circuit for automotive use etc. The device may generally be any wireless and/or battery powered product. The device may be such as an audio device, a video device, a mobile phone, an MP3 player, or a digital camera.

BRIEF DESCRIPTION OF THE DRAWINGS: In the following the invention is described in more details with reference to the accompanying figures, of which

Fig. 1 illustrates prior art ESD protection schemes for ICs with a pad-based and a rail-based architectures together with an example of positions of I/O cells of a power management unit. Fig. 2 illustrates a schematic of a preferred ESD protection part of an IC connected to two supply voltages,

Fig. 3 illustrates an electric diagram of a preferred ESD protection circuit part of an IC connected to two supply voltages, and

Fig. 4 illustrates an electric diagram of a preferred simple embodiment of an ESD trigger circuit.

DESCRIPTION OF PREFERRED EMBODIMENTS:

Fig. 1, upper part, shows prior art ESD clamping routes between an output pad OUT and ground GND in case of a pad-based IC P B and a rail-based IC R B. In the pad- based IC P B, a so-called snap-back clamp is used to provide a direct path from the output pad OUT to ground GND. If a robust snap-back clamp is available this ESD protection solution is solid. However, the snap-back clamp cannot be simulated.

In the rail-based IC R B, distributed non-snap-back clamps serve to ESD protect multiple I/Os, and thus the clamping path from OUT via VDD to GND in general becomes long. This can be simulated, but this approach leads to large clamps a non- flexible positioning of I/Os on the IC.

Fig. 1, lower part, illustrates an example of a floor plan of a power management unit IC with low power domain I/Os LP IO (e.g. 3 V) and high power domain I/Os HP IO (e.g. 20V) located in a hazardous way on the IC die. To implement the rail-based concept in this example, the same concept must be applied at both power domains. Increased resistance due to the long supply tracks must be compensated by increased dimension of the distributed ESD clamps. This problem increases with an increasing number of different voltage domains present.

Fig. 2 illustrates schematically a preferred embodiment of ESD protection relevant parts of an IC according to the invention. First and second I/O cells LV IO, HV IO, indicated by dotted lines, each comprise first clamp devices Tl connected to a first supply voltage Vddl, and second clamp devices T2 connected to a second supply voltage Vdd2. An ESD trigger circuit TC is connected to sense the first and second supply voltages Vddl, Vdd2. The trigger circuit TC is connected to dedicated power tracks RCBl, RCB2 that are also connected to respective first and second clamp device Tl, T2 and thus, it is possible for the trigger circuit TC to activate the respective clamp devices Tl, T2 via the respective power tracks RCBl, RCB2 in response to an ESD event sensed by the trigger circuit TC. For illustration purposes only, the first and second clamp devices Tl, T2 are shown in Fig. 3 with a ground symbol. The ground symbol indicates that the clamp device Tl, T2 may clamp the respective supply voltages Vddl, Vdd2 to ground upon activation. It may be so, but as will be further explained below, at least the second clamp devices T2 are preferably connected otherwise. With the circuit illustrated in Fig. 2 it is possible to provide ESD protection by sensing a level of the first supply voltage Vddl, sending a first activation signal on a first power track RCBl upon the level of the first supply voltage Vddl exceeding a first predetermined threshold value, and activating a first clamp device Tl located in at least a substantial number of the plurality of input-output cells LV IO, HV IO by receipt of the first activation signal on the first power track RCBl . Likewise, it is possible to provide ESD protection by sensing a level of the second supply voltage Vdd2, sending an activation signal on the second power track RCB2 upon the level of the second supply voltage Vdd2 exceeding a second predetermined threshold value, and activating the second clamp device T2 located in at least a substantial number of the plurality of input-output cells LV IO, HV IO by receipt of the second activation signal.

Fig. 3 illustrates in more details a diagram of a preferred embodiment of an ESD protection relevant circuit of an IC with three I/O cells each indicated by dotted lines: a supply I/O cell SUPP IO, an I/O cell LV IO with a pad PADl associated with a first (and lower) supply voltage Vddl, and an I/O cell HV IO with a pad PAD2 associated with a second (and higher) supply voltage Vdd2. An ESD trigger circuit in two parts TCl, TC2 are located in the supply I/O cells SUPP IO. The trigger circuit parts TCl, TC2 are connected to sense respective first and second supply voltages Vddl, Vdd2. In addition, the trigger circuits TCl, TC2 are connected to respective first and second power tracks RCBl, RCB2, i.e. dedicated ESD buses for each voltage domain Vddl, Vdd2 on which the trigger circuits TCl, TC2 sends ESD evacuation signals in case an ESD event is detected on respective supply voltages Vddl, Vdd2.

The power tracks RCBl, RCB2 are led to all of the I/O cells SUPP IO, LVJO, HVJO. All of the I/O cells SUPPJO, LVJO, HVJO has placed inside a first and a second clamp device Tl, T2 for each voltage domain Vddl, Vdd2. The clamp devices Tl, T2 are preferably implemented by transistors, preferably MOST type transistors. The respective first and second clamp devices Tl, T2 are connected to respective power tracks RCBl, RCB2 and can thus be independently activated. The first and second voltages Vddl, Vdd2 may be very different, e.g. Vddl =

3 V, Vdd2 = 20V. Consequently, the distributed rail clamps Tl, T2 must be qualified for the respective power domains. Thus, in Fig. 3 Tl, Al, Bl are low voltage (e.g. 3V) components while T2, A2, B2 are high voltage (e.g. 20V) components.

Each I/O cell SUPPJO, LVJO, HVJO, no matter to which voltage domain Vddl, Vdd2 it belongs, comprises the same protection transistors (in this case Tl, T2).

Transistors Tl act as a clamp for an ESD event applied to a low voltage power domain I/O cell, i.e. LVJO or SUPPJO, shunting the current from Vddl to ground Vss. Transistors T2 act as a clamp for the ESD events applied on the higher voltage power domain IO cell, shunting the current from Vdd2 to Vddl and then to ground Vss. Additionally, the principle assures current paths for all possible stress combinations:

1) For a positive "zap" between PADl and PAD2 (thus belonging to different voltage domains), a current will flow through diode Al to Vddl. When the ESD event appears on the Vddl supply track, the trigger circuit TCl placed in the power supply I/O SUPPJO will detect it and turn on all distributed clamp transistors Tl of this power domain Vddl . All transistors Tl will switch on in parallel and shunt the current to ground Vss. Then the current flows through the ground Vss supply track and finally through diode B2, and it will reach PAD2. 2) For negative "zap" between PADl and PAD2, a current will flow through diode A2 to Vdd2. When the ESD event appears on the Vdd2 supply track, the trigger circuit TC2, placed in the power supply I/O SUPP IO, will detect it and will turn on all high voltage transistors T2. These transistors T2 will switch on in parallel and will shunt the current to Vddl. When the transient signal arrives on Vddl, the trigger circuit TCl of the lower voltage domain Vddl will detect it, and activate all the lower voltage domain Vddl distributed rail clamp transistors Tl which shunt the current from Vddl to ground Vss. Finally, the current further flows through the ground Vss track and diode Bl to PADl .

An advantage of the circuit of Fig. 3 is that the voltage on the Vdd2 track is such that, applied on the gate of the upper transistor keeps Vgs high enough which allows transistor T2 to be more "open" then in the case of lower voltage transistor, thus shunting more current with smaller dimensions.

Fig. 4 shows a preferred embodiment of a part of the trigger circuit, i.e. TCl or

TC2, from the circuit shown in Fig. 3. The trigger circuit comprises a transistor pair Tl 1, Tl 2 preferably a PMOST/NMOST pair, and two resistor-capacitor sets Rl 1, Cl 1, Rl 2, C 12. The NMOST Tl 2 is connected between supply voltage Vdd and ground Vss, while the PMOST Tl 1 is connected between the supply voltage Vdd and the resistor R12. During a positive ESD event the power supply voltage Vdd increases rapidly.

A transient current flows into trigger resistor Rl 1 and charges capacitor CI l. During this transient, the gate-to-source voltage (Vgs), developed across the resistor Rl 1, drives the PMOST Tl 1 above its threshold, and thus triggers the power part on. The ESD current will flow from Vdd to ground Vss. At the end of the transient, when the trigger capacitor Cl 1 is charged, since the current through the resistor Rl 1 has vanished, the Vgs voltage drops to zero and the PMOS Tl 1 switch the power part off.

RC parts Rl 2, C12 are chosen for fast response. Rl 1 and CI l have to keep the NMOST T12 open for the whole duration of ESD pulse, i.e. their time constant must be chosen to be much larger than the duration of the ESD pulse. On the other side, trigger circuit has to prevent power part from activating during the normal power up of the IC, which normally is in the range 0.3-0.5 seconds. A time constant of 0.5-2 seconds is preferred, such as 0.8-1.2 second, most preferably around 1 second. Thus, typical component values to achieve such time constant are: Rl 1 = 500 kOhm and Cl 1 = 2 pF. From this description of a possible implementation of a trigger circuit, the skilled person will know how to implement equivalent trigger circuits TCl and TC2 of Fig. 3.

An advantage of preferred embodiments of the invention is illustrated in the below table compared to conventional rail clamping - for both a high voltage and a low voltage domain. In the below table, optimal clamp widths are shown for fixed electrical resistance R between supply voltage and ground.

R [Ohm] 0,1375 0,25 0,4

Low voltage domain clamps, optimal width [μm]

Conventional 1665 3758 8178

Invention 640 1175 1926

High voltage domain clamps, optimal width [μm]

Conventional 473 525 624

Invention 211 228 267

As seen in the table, both for low and high voltage domains, the optimal clamp width is significantly smaller with the ESD protection scheme according to the invention. This means that there is a relaxed demand to clamp transistors with respect to their size.

Referring to all embodiments, it is to be understood that circuits described for simplicity with two voltage domains can in principle be cascaded and thus be used for ICs with three, four, five or even more different supply voltages. This holds for the clamp devices of each I/O cell as well as for the trigger circuits that are both easily extended by the skilled person to suit any number of voltage domains so that it can be obtained that clamp devices for all voltage domains are included in the I/O cells, and that preferably all clamp devices corresponding to lower supply voltages participate in clamping an ESD event in a higher supply voltage. Thus, preferred embodiments include an IC adapted for connection to three different supply voltages. The three different voltage supplies may be such as: one for digital circuit parts of the IC, one for analog circuit part of the IC, and one for circuit parts supplied by an external charger, such as it is commonly used in a digital camera, an MP3 player and a mobile phone.

A preferred embodiment can be summarized as follows. A rail-based Electro- Static Discharge (ESD) protection scheme for multi-voltage-domain Integrated Circuits (ICs) is proposed. Distributed parts of clamp transistors (Tl , T2) for every voltage domain are comprised within each I/O cell (LV IO, HV IO), no matter to which voltage domain it belongs. These clamp transistors are activated using a dedicated power track for each voltage domain. An ESD trigger circuit (TCl, TC2) senses first and second supply voltages and sends signals via respective power tracks to respective first and second clamp devices inside all I/O cells in case an ESD event is detected. In preferred embodiments clamp devices for all voltage domains are included in the I/O cells, and preferably all clamp devices corresponding to lower supply voltages participate in clamping an ESD event in a higher supply voltage. Preferably, each I/O cell has a first clamp transistor (Tl) adapted to clamp between a first supply voltage and ground upon activation, while a second clamp transistor (T2) is adapted to clamp between a second, higher, supply voltage and the first supply voltage, upon activation. As these first and second clamp transistors share the total (higher) supply voltage, their size can be reduced. As the rail-based approach is applied, the nature of the ESD protection circuits can be simulated. The ESD protection scheme according to the invention provides the flexibility in placing circuits and I/O cells on a die of the IC, since it does not matter which voltage domain these I/O cells refer to. The invention is suitable for ICs with considerable difference in supply voltages, e.g. 3V and 20V.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and/or by means of a suitably programmed processor. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An integrated circuit adapted for connection to first and second supply voltages (Vddl, Vdd2), the integrated circuit comprising an electro-static discharge trigger circuit (TCl, TC2) connected to sense the first and second supply voltages (Vddl, Vdd2), the electro-static discharge trigger circuit (TCl, TC2) further being connected to respective first and second power tracks (RCBl, RCB2), a first input-output cell (LV IO) comprising a first input-output pad (PADl) associated with the first supply voltage (Vddl), the first input-output cell (LV IO) comprising a first set of first and second clamp devices (Tl, T2) connected to the respective first and second power tracks (RCB 1 , RCB2), and a second input-output cell (HV IO) comprising a second input-output pad (PAD2) associated with the second supply voltage (Vdd2), the second input-output cell (HV IO) comprising a second set of first and second clamp devices (Tl, T2) connected to the respective first and second power tracks (RCBl, RCB2).

2. Integrated circuit according to claim 1, wherein the electro-static discharge trigger circuit (TCl, TC2) is adapted to active the first and second clamp devices (Tl, T2) via the respective first and second power tracks (RCBl, RCB2).

3. Integrated circuit according to claim 1, wherein the electro-static discharge trigger circuit (TCl, TC2) is adapted to activate the first and second clamp devices (Tl, T2) upon respective first and second levels of the sensed first and second supply voltages (Vddl, Vdd2) exceeding respective first and second predetermined threshold values.

4. Integrated circuit according to claim 1, wherein the second supply voltage

(Vdd2) is larger than the first supply voltage (Vddl), and wherein the first and second clamp devices (Tl, T2) of both the first and second set of clamp devices are activated upon the second supply voltage (Vdd2) exceeding the second predetermined threshold value.

5. Integrated circuit according to claim 4, wherein the electro-static discharge trigger circuit (TCl, TC2) is adapted to activate the first clamp devices (Tl) of both the first and second set of clamp devices via the first power track (RCBl), upon the second supply voltage (Vdd2) exceeding the second predetermined threshold value.

6. Integrated circuit according to claim 1, wherein the first clamp devices (Tl) of the first and second sets of clamp devices are adapted to connect the first supply voltage (Vddl) to ground (Vss) upon activation, and wherein the second clamp devices (T2) of the first and second sets of clamp devices are adapted to connect the second supply voltage (Vdd2) to the first supply voltage (Vddl) upon activation.

7. Integrated circuit according to claim 1, wherein the electro-static discharge trigger circuit (TC) comprises a transistor pair (Tl 1, T12), two resistors (Rl 1, R12), and two capacitors (CI l, C12).

8. Integrated circuit according to claim 1, wherein the first and second input- output cells (LV IO, HV IO) comprise respective input-output pads (PADl, PAD2) connected to the respective first and second supply voltages (Vddl, Vdd2) via respective first and second diodes (Al, A2), the respective input-output pads (PADl, PAD2) further being connected to ground (Vss) via respective third and fourth diodes (Bl, B2).

9. Integrated circuit according to claim 1, wherein the first and second input- output cells (LV IO, HV IO) are both located on one die of the integrated circuit.

10. Method of electro-static discharge protecting an integrated circuit, the method comprising the steps of: sensing a level of a supply voltage, sending an activation signal on a power track upon the level of the supply voltage exceeding a predetermined threshold value, and activating a clamp device located in a plurality of input-output cells upon receipt of the activation signal.

11. Method according to claim 10, further comprising the steps of sensing a level of a second supply voltage different from the supply voltage, sending a second activation signal on a second power track upon the level of the second supply voltage exceeding a second predetermined threshold value, and activating a second clamp device located in the plurality of input-output cells by receipt of the second activation signal.