CN110138375A - A kind of circuit for chip pin - Google Patents
A kind of circuit for chip pin Download PDFInfo
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- CN110138375A CN110138375A CN201810106736.5A CN201810106736A CN110138375A CN 110138375 A CN110138375 A CN 110138375A CN 201810106736 A CN201810106736 A CN 201810106736A CN 110138375 A CN110138375 A CN 110138375A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Abstract
This application discloses a kind of circuits for chip pin, discharge the voltage on chip pin, the electronic device in chip is protected not to be damaged.The application method includes: the first transistor, second transistor, the first sub-circuit, the second sub-circuit and third sub-circuit；First pole of the first transistor connect and is connected to chip pin with the first pole of the second transistor, and the second pole of the first transistor is connected to positive pole, and the second pole of the second transistor is connected to power cathode；First sub-circuit is connected between the positive pole and the power cathode, and first sub-circuit is connected to the third pole of the first transistor and the third pole of the second transistor；Second sub-circuit is connected between the positive pole and the chip pin；The third sub-circuit is connected between the chip pin and the power cathode, for the positive voltage on the chip pin to be discharged into the power cathode.
Description
Technical field
This application involves chip technology field more particularly to a kind of circuits for chip pin.
Background technique
Chip pin (Pin), also known as chip pin are drawn between chip exterior circuit from chip internal circuits
Interface.Chip pin is divided into input or output pin, and input pin is used to for the signal of external circuit to be input to chip interior electricity
Road, output pin is for exporting the signal of chip internal circuits to chip exterior circuit.
Currently, the output circuit structure inside chip input and output (input output, IO) pin is mainly by two gold
Belong to oxide semiconductor (metal oxide semiconductor, MOS) pipe to constitute, the drain electrodes of two metal-oxide-semiconductors, which is connected, goes forward side by side one
Step is connected to chip pin.First MOS transistor is connect with I O power supply, and second MOS transistor is connect with ground terminal.Work as core
Exist on piece pin and is likely to form the voltage of destruction, such as static discharge (electro static discharge, ESD) voltage,
It then needs to form effective protection to this.Therefore, when the voltage is positive voltage, the parasitic diode of first MOS transistor will
Positive voltage is discharged into I O power supply, and the positive voltage on chip pin is discharged, and prevents it from influencing chip pin signal just
Often output, therefore parasitic diode plays the function of preventing pin from damaging.Due to being connected with other a large amount of devices in I O power supply,
Therefore the positive voltage on chip pin is discharged into I O power supply, will lead to circuit system normal work and is affected.
Reverse-filling processing circuit is increased on the basis of above-mentioned output circuit structure as a result, the reverse-filling processing circuit
Positive voltage leakage path for being truncated between chip pin and I O power supply, prevents the positive voltage on chip pin to be released to IO
On power supply, to guarantee the normal work of circuit system.But reverse-filling processing circuit is avoiding positive voltage leakage path electric to IO
While source impacts, the function of preventing pin from damaging also cannot achieve.
Summary of the invention
This application provides a kind of circuits for chip pin to protect chip for discharging the voltage on chip pin
In electronic device be not damaged.
In a first aspect, this application provides a kind of circuits for chip pin, comprising: the first transistor, the second crystal
Pipe, the first sub-circuit, the second sub-circuit and third sub-circuit；First pole of the first transistor and the second transistor
First pole connects and is further attached to chip pin, and the second pole of the first transistor is connected to positive pole, and described
Second pole of two-transistor is connected to power cathode；First sub-circuit is connected to the positive pole and the power cathode
Between, first sub-circuit is connected to the third pole of the first transistor and the third pole of the second transistor, is used for
It controls the first transistor and the second transistor and exports high level signal or low level signal to the chip pin；Institute
It states the second sub-circuit to be connected between the positive pole and the chip pin, for preventing the positive electricity on the chip pin
Pressure is released to the positive pole；The third sub-circuit is connected between the chip pin and the power cathode, is used
In the positive voltage on the chip pin is discharged into the power cathode.
From above technical scheme, it can be seen that the application has the following advantages: preventing chip pin in the second sub-circuit
On positive voltage be discharged into positive pole, reduce the adverse effect to positive pole, meanwhile, positive voltage is released by third sub-circuit
It is put into power cathode, is provided for the positive voltage on chip pin and lets out electric channel, to protect electronic device, such as the first transistor or
Two-transistor is not damaged by positive voltage, to reduce crash rate of the chip in production, test or use process.
With reference to first aspect, in the first possible implementation of the first aspect, the first transistor is P-channel
Metal-oxide semiconductor (MOS) (positive channel metal oxide semiconductor, PMOS) transistor, it is described
Second transistor be N-channel metal-oxide semiconductor (MOS) (negative channel metal oxide semiconductor,
NMOS) transistor, the first pole of the first transistor and the first pole of the second transistor are drain electrode, the first crystal
Second pole of pipe and the second pole of the second transistor are source electrodes, the third pole of the first transistor and second crystal
The third pole of pipe is grid.
With reference to first aspect or the first possible implementation of first aspect, second in first aspect are possible
In implementation, the third sub-circuit includes: first diode, the second diode and the 4th sub-circuit；One or two pole
The anode of pipe is connect with the chip pin, and the anode of second diode is connect with the positive pole, and the described 1st
The cathode of the cathode of pole pipe and second diode is connected to first node；4th sub-circuit is connected to the first segment
Between point and the power cathode, for the positive voltage to be discharged into the power cathode.
The possible implementation of second with reference to first aspect, in the third possible implementation of first aspect
In, the third sub-circuit further include: third diode；The cathode of the third diode is connected to the first diode
The anode of the positive and chip pin, the third diode is connect with the power cathode；The third diode is used for
Negative voltage on the chip pin is discharged to the power cathode.
The third possible implementation of the possible implementation of second with reference to first aspect or first aspect,
In 4th kind of possible implementation of first aspect, the 4th sub-circuit includes the first ESD protection circuit.
With reference to first aspect, the possible implementation of the first of first aspect to first aspect the 4th kind of possible reality
Any one of existing mode, in the fifth possible implementation of the first aspect, the positive voltage is higher than the chip pipe
The proof voltage threshold value of foot.
With reference to first aspect, the possible implementation of the first of first aspect to first aspect the 5th kind of possible reality
Any one of existing mode, in the sixth possible implementation of the first aspect, the power cathode are ground terminal.It can replace
Ground is changed, the power cathode is negative power end.
With reference to first aspect, the possible implementation of the first of first aspect to first aspect the 6th kind of possible reality
Any one of existing mode, in a seventh possible implementation of the first aspect, the circuit further include: the second electrostatic is put
Electric protection circuit is connected between the positive pole and the power cathode, for releasing the voltage on the positive pole
It is put into the power cathode.
With reference to first aspect, the possible implementation of the first of first aspect to first aspect the 7th kind of possible reality
Any one of existing mode, in the 8th kind of possible implementation of first aspect, the positive voltage is by being connected to the core
The test equipment of piece pin generates.Optionally, the test equipment includes universal meter.
With reference to first aspect, the possible implementation of the first of first aspect to first aspect the 8th kind of possible reality
Any one of existing mode, in the 9th kind of possible implementation of first aspect, second sub-circuit is for preventing institute
The positive voltage stated on chip pin is released to the positive pole through the parasitic diode of the first transistor.Optionally,
Second sub-circuit includes reverse-filling processing circuit.
Second aspect, this application provides a kind of chip, the chip include above-mentioned first aspect, first aspect first
Kind possible implementation is to circuit, the chip pipe described in any one of the 8th kind of possible implementation of first aspect
Foot, the positive pole and the power cathode.
The advantages of with circuit described in above-mentioned first aspect, is similar, which has the electronics device protected in its export structure
Part is not had by the voltage on chip pin such as the function that static discharge voltage damages such as the first transistor or second transistor
Effect, which is reduced, leads to core due to being damaged chip there are voltage on output pin in chip production, test or use process
The case where piece fails, to reduce crash rate of the chip in production, test or use process.
Detailed description of the invention
Fig. 1 is a chip structure schematic diagram in the embodiment of the present application；
Fig. 2 is one embodiment schematic diagram of circuit in the embodiment of the present application；
Fig. 3 is another embodiment schematic diagram of circuit in the embodiment of the present application；
Fig. 4 is another embodiment schematic diagram of circuit in the embodiment of the present application.
Specific embodiment
This application provides a kind of circuits for chip pin to protect chip for discharging the voltage on chip pin
In electronic device be not damaged, reduce crash rate of the chip in production, test or use process.
Below in conjunction with the attached drawing in the application, the technical solution in the application is clearly and completely described, is shown
So, described embodiments are only a part of embodiments of the present application, instead of all the embodiments.The description of the present application and
Claims and term " first " in above-mentioned attached drawing, " second ", " third ", " the 4th " etc. are for distinguishing similar right
As without being used to describe a particular order or precedence order.In addition, term " includes " and " having " and their any change
Shape, it is intended that cover it is non-exclusive include, for example, contain the process, method of series of steps, function or unit, system,
Product or equipment those of are not necessarily limited to be clearly listed step, function or unit, but may include being not clearly listed
Or other steps, function or the unit intrinsic for these process, methods, product or equipment.
Chip (chip) be semiconductor element general designation, be by electronic device by design, test, manufacture and encapsulation after
It obtains.Chip can be the carrier such as silicon wafer of integrated circuit (integrated circuit, IC), be also possible to integrated for referring to
Circuit, therefore it is also semiconductor chip.It is as shown in Figure 1 a chip structure schematic diagram of chip, chip specifically includes that core
Piece pin, input structure circuit, internal logic control circuits, export structure circuit.Wherein, chip pin is also known as pin or IO draws
Foot is mainly used for input or outputs level signals.12 pins are shown in Fig. 1, pin 1 is power pins, for connecting electricity
Anode such as I O power supply in source is chip power supply, for digital circuit the pin of pin 13, for connecting power cathode.Pin 2 is to drawing
Foot 7 be input pin, each input pin with an input structure circuit connection so that outer signals are input to core
In piece, and respective handling is carried out to input signal (high level signal or low level signal) by input structure circuit.Internal logic
Control circuit carries out a series of mathematical logic operation and controls export structure circuit output to export letter accordingly to input signal
Number (high level signal or low level signal).Pin 8 to pin 12 is output pin, each output pin is exported with one
Structural circuit connection, output signal is exported to corresponding output pin.
Circuit in the embodiment of the present application for chip pin is mainly used in above-mentioned export structure circuit, to protect output
Electronic device in structural circuit is not damaged by the high voltage on output pin, such as realizes electrostatic discharge (ESD) protection.In view of
This, is below in conjunction with specific embodiments described in detail the circuit in the application.As shown in Fig. 2, the embodiment of the present application
In be used for the circuit of chip pin, comprising: the first transistor 201, second transistor 202, the first son electricity of sub-circuit 203, second
Road 204, third sub-circuit 205.Fig. 2 also shows chip pin 206, electricity for exporting high level signal or low level signal
Source anode 207 and power cathode 208.
First pole of the first transistor 201 is connect with the first pole of second transistor 202, and is further attached to chip pipe
Foot 206.Second pole of the first transistor 201 is connected to positive pole 207, and the second pole of second transistor 202 is connected to power supply
Cathode 208.First sub-circuit 203 is connected between positive pole 207 and power cathode 208, also, the first sub-circuit 203 divides
It is not connect with the third pole of the second pole of the first transistor 201 and second transistor 202, the first sub-circuit 203 is for controlling the
One transistor 201 and second transistor 202 export high level signal or low level signal to chip pin 206.Specifically, same
One moment, the first sub-circuit 203 control only one transistor turns in the first transistor 201 and second transistor 202, with to
Chip pin 206 exports high level signal or low level signal.When the first transistor 201 is connected, exported to chip pin 206
High level signal exports low level signal to chip pin 206 when second transistor 202 is connected.Second sub-circuit 204 connects
It is connected between positive pole 207 and chip pin 206, the second sub-circuit 204 is used to preventing positive voltage on chip pin through the
The parasitic diode (not shown) of one transistor 201 is released to positive pole 207.Third sub-circuit 205 is connected to core
Between piece pin 206 and power cathode 208, third sub-circuit 205 is used to the positive voltage on chip pin 206 being discharged into power supply
Cathode 208, so that the positive voltage on chip pin 206 is adjusted to the proof voltage threshold value lower than chip pin 206.
From above-mentioned output circuit shown in Fig. 2 it is found that the positive voltage greater than proof voltage threshold value on chip pin 206 can
To be released to power cathode 208 by third sub-circuit 205, so that the voltage value of the positive voltage on chip pin 206 is adjusted
The whole proof voltage threshold value for less than chip pin 206, to avoid at least one in the first transistor 201 and second transistor 202
A crystal is damaged, to achieve the effect that protect chip, and reduces failure of the chip in production, test or use process
Rate.
Optionally, as shown in circuit in Fig. 3, above-mentioned the first transistor 201 can be PMOS transistor 301, the second crystal
Pipe 202 can be NMOS transistor 302, and the first of the first transistor 201 and second transistor 202 extremely drains, first crystal
The extremely source electrode of the second of pipe 201 and second transistor 202, the third extremely grid of the first transistor 201 and second transistor 202
Pole, at least one transistor in the first transistor 201 and second transistor 202 be also possible to other with PMOS transistor or
NMOS transistor has one or more switching tubes of identity function, e.g. diode or carbon nanotube, for realizing control
Chip pin 206 exports high level signal or low level signal, does not do any restrictions to this application.Optionally, above-mentioned implementation
Power cathode in example can be ground terminal such as digital signal ground end, be also possible to negative supply.
Circuit in the application can be used I O power supply and be powered to it, as shown in figure 3, circuit in the embodiment of the present application
Another embodiment, comprising: PMOS transistor 301, NMOS transistor 302, chip interior logic circuit 303, reverse-filling
Processing circuit 304, first diode 306, the second diode 307, ESD protection circuit 308 and ESD protection circuit
309.Chip pin 305, I O power supply 310 and ground terminal 311, the chip pin being respectively equivalent in Fig. 2 are also shown in Fig. 3
206, positive pole 207 and power cathode 208.PMOS transistor 301, NMOS transistor 302, chip interior logic circuit
303 and the associated description of reverse-filling processing circuit 304 can be respectively refering to the first transistor 201, second transistor in above-mentioned Fig. 2
202, the associated description of the first sub-circuit 203 and the second sub-circuit 204, to this, details are not described herein again.
In the present embodiment, the substrate of PMOS transistor 301 is floating substrate, the i.e. grid and source electrode of PMOS transistor 301
Between threshold voltage it is adjustable.Also, reverse-filling processing circuit 304 is also connect with PMOS transistor 301, in turn, reverse-filling
Processing circuit 304 is used to adjust 301 threshold value of PMOS transistor electricity according to the voltage of I O power supply 310 and the voltage of chip pin 305
Pressure is so that the parasitic diode (not shown) of PMOS transistor 301 is not turned in reverse-bias state always.It is easy to know
Road, the direction of the parasitic diode of PMOS transistor 301 is drained by it is directed toward its source electrode, therefore the positive electricity on chip pin 305
Pressure can not be released to I O power supply 310, reduce the influence to I O power supply 310.
Logic circuit 303 is used to generate the grid of control PMOS transistor 301 and NMOS transistor 302, with control two
The on and off of transistor, so that chip pin 305 exports high level signal or low level signal.The logic circuit 303 can
Including logic control circuit or computing circuit, may also comprise processor, as central processing unit, microcontroller, microprocessor,
Digital signal processor etc., and necessary drive software or application software can be run.
It should be noted that above-mentioned parasitic diode is since the manufacture craft of MOS transistor is formed, function is equivalent
In general-purpose diode, when the cathode voltage of parasitic diode is higher than its cathode voltage, parasitic diode conducting, when parasitic two poles
When the cathode voltage of pipe is lower than its cathode voltage, parasitic diode is not turned on, and is also referred to as parasitic diode for above-mentioned conducting
In forward bias condition, the above-mentioned also referred to as parasitic diode that is not turned on is in reverse-bias state.The parasitism of MOS transistor
Diode is the equivalent diode come out of MOS transistor, but substantially the two can correspond to same physical structure.Wherein, PMOS
Source electrode is directed toward by drain electrode in the direction of the parasitic diode of transistor 301, and the direction of the parasitic diode of NMOS transistor 302 is by source
It is directed toward drain electrode in pole.
It is equal with above-mentioned third sub-circuit 205, first diode 306, the second diode 307 and ESD protection circuit
308 composition high pressures let out electric channel, wherein the anode of first diode 306 is connect with said chip pin 305, the second diode
307 anode is connect with I O power supply 310, and the cathode of the cathode of first diode 306 and the second diode 307 is connected to first segment
Point.ESD protection circuit 308 is connected between first node and ground terminal 311.When there are positive voltages on chip pin 305
When, ESD protection circuit 308 discharges positive voltage to ground terminal 311, to prevent the positive electricity on chip pin 305
Pressure is more than that the proof voltage threshold value of chip pin 305 leads to the impaired situation of the circuit of chip pin 305.Certainly, static discharge
Protection circuit 308 can also not be this application any as replaced other circuits with above-mentioned positive voltage drainage function
Limitation.Second diode 307 is used to provide fixed voltage for electrostatic discharge protection circuit 308, so that electrostatic discharge protection circuit 308 can be with
It works normally, so that above-mentioned high pressure, which lets out electric channel, realizes that it lets out Electricity Functional, and then positive voltage on chip pin 305 is released
To ground terminal 311.
ESD protection circuit 309 or other circuits with similar functions are for releasing the electrostatic in I O power supply 310
It puts to ground terminal 311, to enhance the protective capability of circuit, the protecting effect to chip is promoted, so that chip is not damaged by electrostatic
It is bad.In practical applications, due to I O power supply 310 and ground terminal 311 can also with the circuit of other in chip or with other chips
Connection, therefore, by the Electro-static Driven Comb in I O power supply 310 to ground terminal 311, it is also possible that other circuits in chip or other
Chip works normally.
It was found from the description of above-mentioned pair nmos transistor: the direction of the parasitic diode of NMOS transistor 302 is referred to by source electrode
To drain electrode.Therefore, in the electronic circuit as shown in figure 3, when, there are when negative voltage, negative voltage can be through NMOS crystalline substance on chip pin 305
The parasitic diode of body pipe 302 is released to ground terminal 311.But NMOS transistor 302 is used for a long time to the negative electricity of chip pin 305
Pressure is released, and be will lead to NMOS transistor 302 and is damaged or is lowered its service life.Therefore, in order to preferably protect
NMOS transistor 302 and negative high voltage is released quickly against ground terminal, present invention also provides another embodiments.
As shown in figure 4, in the embodiment of the present application circuit another embodiment, comprising: PMOS transistor 401, NMOS are brilliant
Body pipe 402, the logic circuit 403 of chip interior, reverse-filling processing circuit 404, first diode 406, the second diode 407,
ESD protection circuit 408, ESD protection circuit 409 and third diode 410.Chip pin is also shown in Fig. 4
405, I O power supply 411 and ground terminal 412.
In the present embodiment, PMOS transistor 401, NMOS transistor 402, the logic circuit 403 of chip interior, at reverse-filling
Manage circuit 404, first diode 406, the second diode 407, ESD protection circuit 408 and ESD protection circuit
409 associated description can be respectively refering to the logic electricity of PMOS transistor 301, NMOS transistor 302, chip interior in above-mentioned Fig. 3
Road 303, reverse-filling processing circuit 304, first diode 306, the second diode 307, ESD protection circuit 308 and electrostatic
The associated description and the associated description in the corresponding embodiment of Fig. 2 of electric discharge protection circuit 309, to this, details are not described herein again.
The associated description of rest part in Fig. 4 sees the description of relevant portion in above-mentioned Fig. 2 and Fig. 3, such as core
Piece pin 405, I O power supply 411 and ground terminal 412 are respectively equivalent to chip pin 305, I O power supply 310 and ground terminal in Fig. 3
311.410 cathode of third diode is connected to the anode and chip pin 405 of first diode 406, and third diode 410 is just
Pole is connect with ground terminal 412；Third diode 410 is for discharging the negative voltage of chip pin 405 to ground terminal 412.
Be illustrated below with reference to working principle of the concrete application scene to the circuit in the embodiment of the present application, specifically such as with
For Fig. 4, when chip in the detection process, be that a kind of common chip is examined by impedance value of the detection chip pin to ground terminal
Survey method.In above-mentioned detection method, usually used test equipment, such as the buzzing shelves of universal meter, detection chip pin 405
Whether the impedance value between ground terminal 412 is obvious less than normal, is, for example, less than 1000 ohm, universal meter will issue buzzing and mention
Show.Buzzing shelves testing principle are as follows: generate a current source, inside universal meter to export constant current, example to testee
Such as 1mA.Since the impedance of testee is different, it can be automatically adjusted and be exported according to the size of testee impedance inside universal meter
Voltage, to guarantee the output electric current of 1mA.Testee impedance is no more than certain preset value, if it does, buzzing shelves are just
It is basic to maintain one fixed voltage of output, it is equivalent to open-circuit voltage.
When detecting, universal meter is adjusted to buzzing shelves, and connects chip pin 405, due to posting for NMOS tube at this time
Raw diode is not turned in reverse-bias state, and impedance is equivalent to greatly open circuit very much.Since universal meter exports a perseverance at this time
Constant current, so that there are an open-circuit voltages on chip pin 405, if the open-circuit voltage is not above the resistance to of chip pin 405
Voltage threshold, then electrostatic discharge protection circuit 408 is not turned in high-impedance state, if the open-circuit voltage is more than the resistance to electricity of chip pin 405
Threshold value is pressed, then electrostatic discharge protection circuit 408 is in low resistance state conducting, and the high voltage on chip pin 405 passes through electrostatic discharge protection circuit
408 are discharged into and connect low side, to reduce the high voltage of chip pin 405 to the proof voltage threshold value of chip pin 405 hereinafter, to,
It protects the chip pin 405 of chip not damaged by high voltage, and then reduces the chip failure rate in chip testing process.Together
Sample, similar with above-mentioned detection process, the circuit in the application also can be applied in the production and use process, protect chip pipe
Foot causes chip not to be available to prevent chip pin from being damaged by high voltage.
The embodiment of the present application also provides a kind of chip, which includes that the corresponding method of above-mentioned Fig. 2, Fig. 3 and Fig. 4 is implemented
Any circuit, chip pin, I O power supply and ground terminal described in example specifically may refer to the corresponding chip signal of Fig. 1
Figure.Similar with the beneficial effect of the circuit of the description in above-mentioned Fig. 2, Fig. 3 and Fig. 4, which, which has, protects in its export structure
Electronic device (such as the first transistor or second transistor) not by chip pin high voltage damage function, to guarantee
Stating chip and the circuit system including the chip can work normally, while effectively reduce in chip production, test or use
In the process since there are voltages on output pin, chip is made to be damaged the case where leading to chip failure such as static discharge voltage
Occur, to reduce crash rate of the chip in production, test or use process.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, shown or discussed different components or the mutual company of module
Connect expression is a kind of coupling or electric connection.This connection can be directly connected, and be also possible to be connected by other devices,
To realize the electric connection of different components or module.
The above, above embodiments are only to illustrate the technical solution of the application, rather than its limitations；Although referring to before
Embodiment is stated the application is described in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, each embodiment technical proposal scope of the application that it does not separate the essence of the corresponding technical solution.
Claims (11)
1. a kind of circuit for chip pin characterized by comprising
The first transistor, second transistor, the first sub-circuit, the second sub-circuit and third sub-circuit；
First pole of the first transistor connect and is further attached to chip pin with the first pole of the second transistor,
Second pole of the first transistor is connected to positive pole, and the second pole of the second transistor is connected to power cathode；
First sub-circuit is connected between the positive pole and the power cathode, and first sub-circuit is connected to institute
The third pole of the first transistor and the third pole of the second transistor are stated, for controlling the first transistor and described second
Transistor exports high level signal or low level signal to the chip pin；
Second sub-circuit is connected between the positive pole and the chip pin, for preventing the chip pin
Positive voltage be discharged into the positive pole；
The third sub-circuit is connected between the chip pin and the power cathode, for will be on the chip pin
The positive voltage is discharged into the power cathode.
2. circuit according to claim 1, which is characterized in that the first transistor is that P-channel metal oxide is partly led
Body PMOS transistor, the second transistor are N-channel metal-oxide semiconductor (MOS) NMOS transistor, the first transistor
First pole and the first pole of the second transistor are drain electrodes, the second pole of the first transistor and the second transistor
Second pole is source electrode, and the third pole of the first transistor and the third pole of the second transistor are grids.
3. circuit according to claim 1 or 2, which is characterized in that the third sub-circuit includes: first diode,
Two diodes and the 4th sub-circuit；The anode of the first diode is connect with the chip pin, second diode
Positive to connect with the positive pole, the cathode of the cathode of the first diode and second diode is connected to first segment
Point；4th sub-circuit is connected between the first node and the power cathode, for will be on the chip pin
The positive voltage is discharged into the power cathode.
4. circuit according to claim 3, which is characterized in that the third sub-circuit further include: third diode；
The cathode of the third diode is connected to the anode and the chip pin of the first diode, the three or two pole
The anode of pipe is connect with the power cathode；The third diode is for discharging the negative voltage on the chip pin to institute
State power cathode.
5. circuit according to claim 3 or 4, which is characterized in that the 4th sub-circuit is anti-including the first static discharge
Protection circuit.
6. circuit according to any one of claim 1 to 5, which is characterized in that the positive voltage is higher than the chip pipe
The proof voltage threshold value of foot.
7. circuit according to any one of claim 1 to 6, which is characterized in that the power cathode is ground terminal.
8. circuit according to any one of claim 1 to 7, which is characterized in that the circuit further include: the second electrostatic is put
Electric protection circuit is connected between the positive pole and the power cathode, for releasing the voltage on the positive pole
It is put into the power cathode.
9. circuit according to any one of claim 1 to 8, which is characterized in that the positive voltage is by being connected to the core
The test equipment of piece pin generates.
10. circuit according to any one of claim 1 to 9, which is characterized in that second sub-circuit is for preventing institute
The positive voltage stated on chip pin is released to the positive pole through the parasitic diode of the first transistor.
11. a kind of chip, which is characterized in that the chip includes circuit according to any one of claim 1 to 10, institute
State chip pin, the positive pole and the power cathode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810106736.5A CN110138375B (en) | 2018-02-02 | 2018-02-02 | Circuit for chip pin |
| PCT/CN2019/072881 WO2019149126A1 (en) | 2018-02-02 | 2019-01-24 | Circuit for use in chip pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810106736.5A CN110138375B (en) | 2018-02-02 | 2018-02-02 | Circuit for chip pin |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110138375A true CN110138375A (en) | 2019-08-16 |
| CN110138375B CN110138375B (en) | 2021-08-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810106736.5A Active CN110138375B (en) | 2018-02-02 | 2018-02-02 | Circuit for chip pin |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110138375B (en) |
| WO (1) | WO2019149126A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112596570A (en) * | 2021-03-03 | 2021-04-02 | 上海灵动微电子股份有限公司 | Input/output circuit |
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|---|---|---|---|---|
| CN1998120A (en) * | 2004-06-08 | 2007-07-11 | 沙诺夫公司 | Method and apparatus for providing current controlled electrostatic discharge protection |
| CN101258597A (en) * | 2005-07-08 | 2008-09-03 | Nxp股份有限公司 | Integrated circuit with electro-static discharge protection |
| US20100226055A1 (en) * | 2009-03-06 | 2010-09-09 | Yang-Han Lee | Electrostatic discharge protection devices |
| CN105556666A (en) * | 2013-09-12 | 2016-05-04 | 高通股份有限公司 | Electro-static discharge protection for integrated circuits |
| JP2017054864A (en) * | 2015-09-07 | 2017-03-16 | アルプス電気株式会社 | ESD protection circuit and semiconductor integrated circuit device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101039027B (en) * | 2007-05-10 | 2010-05-26 | 北京中星微电子有限公司 | Improved electrostatic discharge protecting circuit |
| CN107453342A (en) * | 2017-05-19 | 2017-12-08 | 上海北京大学微电子研究院 | A kind of ESD power clamps circuit and IC chip |
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2018
- 2018-02-02 CN CN201810106736.5A patent/CN110138375B/en active Active
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2019
- 2019-01-24 WO PCT/CN2019/072881 patent/WO2019149126A1/en active Application Filing
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|---|---|---|---|---|
| CN1998120A (en) * | 2004-06-08 | 2007-07-11 | 沙诺夫公司 | Method and apparatus for providing current controlled electrostatic discharge protection |
| CN101258597A (en) * | 2005-07-08 | 2008-09-03 | Nxp股份有限公司 | Integrated circuit with electro-static discharge protection |
| US20100226055A1 (en) * | 2009-03-06 | 2010-09-09 | Yang-Han Lee | Electrostatic discharge protection devices |
| CN105556666A (en) * | 2013-09-12 | 2016-05-04 | 高通股份有限公司 | Electro-static discharge protection for integrated circuits |
| JP2017054864A (en) * | 2015-09-07 | 2017-03-16 | アルプス電気株式会社 | ESD protection circuit and semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112596570A (en) * | 2021-03-03 | 2021-04-02 | 上海灵动微电子股份有限公司 | Input/output circuit |
| CN112596570B (en) * | 2021-03-03 | 2021-04-30 | 上海灵动微电子股份有限公司 | Input/output circuit |
Also Published As
| Publication number | Publication date |
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| WO2019149126A1 (en) | 2019-08-08 |
| CN110138375B (en) | 2021-08-27 |
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