CN106783789A - Strip substrate and its manufacture method - Google Patents
Strip substrate and its manufacture method Download PDFInfo
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- CN106783789A CN106783789A CN201610652235.8A CN201610652235A CN106783789A CN 106783789 A CN106783789 A CN 106783789A CN 201610652235 A CN201610652235 A CN 201610652235A CN 106783789 A CN106783789 A CN 106783789A
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- 239000000758 substrate Substances 0.000 title claims abstract description 197
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000002708 enhancing effect Effects 0.000 claims abstract description 64
- 230000002093 peripheral effect Effects 0.000 claims abstract description 22
- 238000009434 installation Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000003855 Adhesive Lamination Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Disclose a kind of strip substrate and its manufacture method.Strip substrate includes the enhancing component of the peripheral part for being attached to strip substrate according to an embodiment of the invention.
Description
Technical field
The present invention relates to a kind of strip substrate and its manufacture method.
Background technology
The package substrate for being mainly used in the substrate for memory package has constantly been developed as new form and more next
More all kinds, to tackle increasing for the demand that there is higher functionality for smaller electronic installation faster.
Specifically, make package substrate it is smaller it is relatively thin become important task, and carrying out numerous studies with by
The memory of Large Copacity is packaged according to high density.
If however, do not have for bearing the enough rigidity of its manufacturing process for the substrate of memory package,
Substrate can occur warpage, if substrate becomes relatively thin, such warpage will likely be larger.
As a result, when manufacture encapsulation superposition (package-on-package) product, warpage issues can become to reduce yield
(yield) main cause, it is therefore desirable to study can further carry large-duty encapsulating structure.
Correlation technique (open on July 4th, 2001) is described in 10-2001-0056778 Korean Patent Publications.
The content of the invention
An aspect of of the present present invention provides a kind of strip substrate, and the strip substrate includes being attached to the periphery of strip substrate
The enhancing component for dividing, to strengthen the warp stiffness of strip substrate.
Here, enhancing component can be formed and than strip substrate relative thick, and must be attached to the side surface of strip substrate.
Additionally, enhancing component can be attached to strip substrate by being laminated to peripheral part of strip substrate.
According to a total aspect, a kind of strip substrate includes multiple cell substrates, every in the multiple cell substrate
It is individual with the circuit pattern layer being formed in each in the multiple cell substrate and insulating barrier, the strip substrate includes：
Enhancing component, is attached to peripheral part of strip substrate.
According to another total aspect, a kind of method of manufacture strip substrate includes：Preparation includes the bar of multiple cell substrates
Shape substrate, wherein, each in the multiple cell substrate has the electricity in each being formed in the multiple cell substrate
Road patterned layer and insulating barrier；Enhancing component is attached to strip substrate along peripheral part of strip substrate, to strengthen strip base
The warp stiffness of plate.
Brief description of the drawings
Fig. 1 is the top view for briefly showing strip substrate according to an embodiment of the invention.
Fig. 2 is the sectional view for briefly showing strip substrate according to an embodiment of the invention.
Fig. 3 is the sectional view for briefly showing strip substrate according to another embodiment of the present invention.
Fig. 4 to Fig. 7 diagrammatically illustrates the method for manufacturing strip substrate according to an embodiment of the invention.
The description of label
110：Cell substrate
111：Circuit pattern layer
113：Insulating barrier
120：Dummy portions
200：Enhancing component
300：Electronic installation
1000、2000：Strip substrate
Specific embodiment
The term used in this specification is meant only to describe specific embodiment, and is in no way intended to limit the present invention.Unless in addition
Clearly use, the statement of otherwise singulative includes the implication of plural form.
In this manual, such as " including " or "comprising" statement be intended to refer to characteristic, quantity, step, operation, element,
Part or combinations thereof, and be not construed as excluding one or more other characteristics, quantity, step, operation, element,
Any presence of part or combinations thereof or possibility.Additionally, throughout the specification, when element, to be described as " being located at " right
As " on " when, its meaning should be the element on or below object, and be not necessarily mean that the element and be located at object
Gravity direction upside.
When an element is described as " with reference to " to another element, physics directly connects between it refers not only to these elements
Touch, and should include what each of another element between these elements and in these elements was contacted with another element
Possibility.
The such as term of " first " and " second " can be only used for distinguishing an element with another identical or corresponding element
Open, and said elements should not be limited to above-mentioned term.
The size and thickness of each element shown in accompanying drawing are provided for the ease of describing and illustrating, the present invention does not answer office
It is limited to shown size and thickness.
Hereinafter, the specific reality of strip substrate of the invention and its manufacture method is described in detail with reference to the accompanying drawings
Apply example.When the present invention is described with reference to the accompanying drawings, any identical or corresponding element will be indicated using identical label, will not provided
Their redundancy description.
Fig. 1 is the top view for briefly showing strip substrate according to an embodiment of the invention.Fig. 2 is briefly to show root
According to the sectional view of the strip substrate of embodiments of the invention.
As depicted in figs. 1 and 2, strip substrate 1000 includes enhancing component 200 according to an embodiment of the invention.So
In the case of, electronic installation 300 may be provided on strip substrate 1000.
Strip substrate 1000 is the part for including multiple cell substrates 110 and dummy portions 120, wherein, multiple unit bases
Each in plate 110 has circuit pattern layer 111 and insulating barrier 113 formed therein, as shown in figure 1, the cloth of electronic installation 300
Put in each in cell substrate 110, dummy portions 120 be not arranged after SMT (surface mounting technique) technique but
It is removed.
In this case, as shown in Fig. 2 each in cell substrate 110 can be therein with being continuously laminated to
Circuit pattern layer 111 and insulating barrier 113, and with electronic circuit and the insulating coating for electronic circuit formed therein
Structure, to perform predetermined function.
Circuit pattern layer 111 can be formed by using the engraving method of photoetching or by additive process (that is, plating), and
Can be connected with another circuit pattern layer 111 for example, by the via through insulating barrier 113.However, circuit pattern layer 111 is not limited to
In described here, and can be to carry out various modifications as required.
Meanwhile, as the mobile device of such as smart phone has rapidly become smaller, lighter and high functionality, encapsulate base
Plate has also become thinner and more integrated.Therefore, as package substrate becomes thinner, warpage defect is non-right due to package substrate
Title property and aggravate, this causes to be difficult to set electronic installation 300 and causes to connect defect.
During the high temperature reflux that electronic installation 300 and solder are engaged with each other, the warpage very great Cheng of package substrate
Influenceed by the room temperature state of package substrate and the state of package substrate on degree, the manufacturing process meeting reason of package substrate is in temperature
Degree and the alteration of form of the package substrate of buckling deformation and it is complicated.
Specifically, can be by manufacturing the bar element of strip substrate 1000 and carrying out underfill (under-
Filling then), shaping carries out sawing to each in cell substrate 110 to complete the manufacture of package substrate.Therefore, thin
In the case of type strip substrate 1000 (thickness of strip substrate 1000 is comparatively small), SMT machinabilitys can be due to above-mentioned warpage
And substantially deteriorate.
Therefore, the strip substrate 1000 according to the present embodiment have be attached to its enhancing component 200, to be significantly enhanced
Warp stiffness, and SMT machinabilitys are improved by enhanced warp stiffness.
That is, as depicted in figs. 1 and 2, enhancing component 200 is such part：Along the week of strip substrate 1000
The warp stiffness for being partially attached to strip substrate 1000 to strengthen strip substrate 1000 is enclosed, and can support strip substrate 1000
Peripheral part is being partially prevented from the warpage in SMT steps of strip substrate 1000.
Here, enhancing component 200 can be made up of the material with the rigidity relatively high of the rigidity than strip substrate 1000, institute
Stating material includes such as metal, polymer composites or thin metal layer adhesive (thin-type metal layer
Binder), but for strengthen the material of component 200 be not limited to it is described herein, and can be any material, as long as its have
There are high rigidity and good hot property and be conducive to preventing warpage.Enhancing component 200 can be used adhesive attachment to bar
Shape substrate 1000.
Meanwhile, the construction shown in Fig. 1 and Fig. 2 is only an example of the strip substrate according to the present embodiment, and can
It is implemented as various other constructions.For example, enhancing component 200 may be affixed to any surface of peripheral part of strip substrate 1000
Or it is attached to each surface of peripheral part of strip substrate 1000.
Electronic installation 300 is arranged in each in cell substrate 110, and can be the active device of such as IC chip
Or the passive device of such as capacitor and inductor.Electronic installation 300 can have be formed thereon for circuit pattern layer 111
The terminal of electrical connection, and can be bonded by welding, underfill, wire bonding or flip-chip and be arranged on cell substrate
In each in 110.
Here, in the strip substrate 1000 according to the present embodiment, due to can be used enhancing component 200 to prevent strip base
The warpage of plate 1000, therefore can be easier and firmly electronic installation 300 is arranged in each in cell substrate 110.
In the strip substrate 1000 according to the present embodiment, enhancing component 200 can be coupled to the side table of strip substrate 1000
Face.Specifically, it may be preferred to strengthen the dummy portions 120 that component 200 is attached to strip substrate 1000.Assuming that enhancing structure
Part 200 is the supplement component for improving SMT machinabilitys, then enhancing component 200 is needed from the package substrate construction for completing
It is removed.
Therefore, the dummy portions 120 of strip substrate 1000 are attached to by strengthening component 200, after SMT techniques, when
When removing dummy portions 120 for example, by sawing process, enhancing component 200 can be simultaneously removed, without for removing increasing
The additional technique of strong component 200.
In the strip substrate 1000 according to the present embodiment, enhancing component 200 can be along the face each other of strip substrate 1000
To two side surfaces be attached to strip substrate 1000.That is, enhancing component 200 can support two of strip substrate 1000
Relative side surface.
As a result, even if producing warping stress in strip substrate 1000, also can be by being attached to two of strip substrate 1000
A pair of enhancing components 200 of the either side of relative side surface relatively evenly absorb warping stress, make due to strip substrate
Warpage defect is minimized caused by 1000 asymmetry.
In the strip substrate 1000 according to the present embodiment, enhancing component 200 can be formed must be more relative than strip substrate 1000
Side surface that is thick and being attached to strip substrate 1000.That is, as shown in Fig. 2 by by the increasing thicker than strip substrate 1000
Strong component 200 is attached to the side surface of strip substrate 1000, can strengthen the warp stiffness of strip substrate 1000.
For example, using adhesive bond to the side of strip substrate 1000 in the enhancing component 200 thicker than strip substrate 1000
In the case of surface, relatively thick enhancing component 200 can provide larger warp stiffness, strip substrate 1000 by enhancing
The part of the engagement of component 200 can be coupled to strengthen component 200, so as to limit the generation of warpage.
As described above, the strip substrate 1000 according to the present embodiment can be attached to by by the enhancing component 200 of relative thick
The relatively simple process of the side surface of strip substrate 1000 efficiently controls the warpage of strip substrate 1000.
Fig. 3 is the sectional view for briefly showing strip substrate according to another embodiment of the present invention.
As shown in figure 3, strip substrate 2000 according to another embodiment of the present invention can have by being laminated to strip base
The enhancing component 200 of strip substrate 2000 is attached on peripheral part of plate 2000.That is, as shown in figure 3, can pass through
Enhancing component 200 is laminated on peripheral part of strip substrate 2000 so that peripheral part of strip substrate 2000 becomes to compare strip
The remainder thickness of substrate 2000 strengthens the warp stiffness of strip substrate 2000.
For example, in the enhancing component 200 being made up of the insulating barrier with predetermined thickness using such as adhesive lamination in bar
In the case of on peripheral part of shape substrate 2000, the warpage that peripheral part offer of the relative thick of strip substrate 2000 is larger is firm
Degree, so as to limit the generation of warpage.
As described above, the strip substrate 2000 according to the present embodiment can be laminated to strip substrate by by enhancing component 200
Relatively simple process on 2000 peripheral part efficiently controls the warpage of strip substrate 2000.
Simultaneously as the main element of strip substrate 2000 according to another embodiment of the present invention with reference to according to this hair
It is same or similar that the strip substrate 1000 of bright embodiment is described, therefore it is same or similar redundantly to describe these herein
Element.
Fig. 4 to Fig. 7 diagrammatically illustrates the method for manufacturing strip substrate according to an embodiment of the invention.Here, in order to
It is easy to description, methods described will be described using strip substrate referring to Figures 1 and 2.
As shown in Figures 4 to 7, the method for manufacture strip substrate starts from preparing including many according to an embodiment of the invention
The strip substrate 1000 of individual cell substrate 110, each in the multiple cell substrate 110 has circuit diagram formed therein
Pattern layer 111 and insulating barrier 113 (Fig. 4).
Here, strip substrate 1000 includes cell substrate 110 and dummy portions 120, cloth in each in cell substrate 110
Electronic installation 300 is equipped with, dummy portions 120 are not arranged but are removed after SMT (surface mounting technique) technique.This
Outward, each in cell substrate 110 can have and continuously be laminated to circuit pattern layer therein 111 and insulating barrier 113, and have
There is electronic circuit and the insulating coating structure for electronic circuit formed therein, for performing predetermined function.
Then, enhancing component 200 is attached to strip substrate 1000 along peripheral part of strip substrate 1000, to strengthen
The warp stiffness (Fig. 5) of strip substrate 1000.That is, enhancing component 200 is such part：Along strip substrate 1000
Peripheral part strip substrate 1000 is attached to strengthen the warp stiffness of strip substrate 1000, and sustainable strip substrate
1000 peripheral part is being partially prevented from the warpage in SMT steps of strip substrate 1000.
Therefore, the method for the manufacture strip substrate according to the present embodiment can be attached to strip base by by enhancing component 200
Plate 1000 strengthens the warp stiffness of strip substrate 1000, and SMT machinabilitys are improved by enhanced warp stiffness.
The method of the manufacture strip substrate according to the present embodiment may additionally include in cell substrate 110 each on electricity is set
The step of sub-device 300 (Fig. 6).Electronic installation 300 can have the end being formed thereon for being electrically connected with circuit pattern layer 111
Son, and can be bonded in each being arranged in cell substrate 110 by welding, underfill, wire bonding or flip-chip.
Due to preventing strip substrate using enhancing component 200 according to the method for the manufacture strip substrate of the present embodiment
1000 warpage, therefore can be easier and firmly electronic installation 300 is arranged in each in cell substrate 110.
The method of the manufacture strip substrate according to the present embodiment may also include the dummy portions 120 of removal strip substrate 1000
With enhancing component 200 and the step of cell substrate 110 is separated from each other (Fig. 7).That is, can be incited somebody to action for example, by Sawing Process
Each in cell substrate 110 completes to be single package substrate.
Here, enhancing component 200 can be coupled to the dummy portions 120 of strip substrate 1000.Assuming that enhancing component 200 is use
In the supplement component for improving SMT machinabilitys, then enhancing component 200 needs to be removed from the package substrate construction for completing.
Therefore, by the way that enhancing component 200 to be attached to the dummy portions 120 of strip substrate 1000, after SMT techniques,
When dummy portions 120 are removed for example, by Sawing Process, enhancing component 200 can be simultaneously removed, without for going
Except the additional technique of enhancing component 200.
According to the method for the manufacture strip substrate of the present embodiment, be may include shape with reference to the step of enhancing component 200
The step of must be attached to the side surface of strip substrate 1000 than the enhancing component 200 of the relative thick of strip substrate 1000.Namely
Say, by the way that the enhancing component 200 thicker than strip substrate 1000 to be attached to the side surface of strip substrate 1000, strip base can be strengthened
The warp stiffness of plate 1000.
Additionally, according to the method for the manufacture strip substrate of the present embodiment, be may include with reference to the step of enhancing component 200
Enhancing component 200 is attached to strip substrate by the way that enhancing component 200 is laminated on peripheral part of strip substrate 1000
1000。
As described above, the method that the manufacture strip substrate according to the present embodiment can be used, by by the enhancing structure of relative thick
Part 200 is attached to the side surface of the strip-like surface of strip substrate 1000 or enhancing component 200 is laminated into strip substrate 1000
Relatively simple process on peripheral part efficiently controls the warpage of strip substrate 1000.
Simultaneously as being described and reality of the invention with reference to strip substrate 1000 according to an embodiment of the invention
The related element of the method for the manufacture strip substrate of example is applied, therefore will not redundantly describe these elements herein.
Although being described above the particular embodiment of the present invention, for the common skill of this area belonging to the present invention
Art personnel should be understood that in the case where the technological thought of the invention and scope that should be defined by the claims is not departed from, can
There is various displacements of the invention and modification.It will be further understood that claim of the invention is included except above-described embodiment
Outside multiple other embodiments.
Claims (12)
1. a kind of strip substrate, the strip substrate includes multiple cell substrates, and each in the multiple cell substrate has
The circuit pattern layer and insulating barrier being formed in each in the multiple cell substrate, the strip substrate include：
Enhancing component, is attached to peripheral part of strip substrate.
2. strip substrate as claimed in claim 1, wherein, enhancing component uses adhesive attachment to strip substrate.
3. strip substrate as claimed in claim 1, wherein, enhancing component is attached to the side surface of strip substrate.
4. strip substrate as claimed in claim 3, wherein, enhancing component along strip substrate opposed facing two side tables
Face is attached to strip substrate.
5. the strip substrate as any one of Claims 1-4, wherein, enhancing component must be than strip substrate by being formed
Relative thick and be attached to the side surface of strip substrate.
6. the strip substrate as any one of Claims 1-4, wherein, enhancing component is by being laminated to strip substrate
Strip substrate is attached on peripheral part.
7. it is a kind of manufacture strip substrate method, including：
Preparation includes the strip substrate of multiple cell substrates, wherein, each in the multiple cell substrate is with being formed in institute
State the circuit pattern layer and insulating barrier in each in multiple cell substrates；
Enhancing component is attached to strip substrate along peripheral part of strip substrate, to strengthen the warp stiffness of strip substrate.
8. method as claimed in claim 7, methods described also includes：
Electronic installation is set in each in the multiple cell substrate.
9. method as claimed in claim 8, methods described also includes：
The dummy portions and enhancing component of strip substrate are removed, and the multiple cell substrate is separated from each other.
10. method as claimed in claim 9, wherein, enhancing component is attached to the dummy portions of strip substrate.
11. method as any one of claim 7 to 10, wherein, include with reference to the step of enhancing component：
Enhancing component is attached to the side surface of strip substrate, enhancing component is formed must be than strip substrate relative thick.
12. method as any one of claim 7 to 10, wherein, include with reference to the step of enhancing component：
Enhancing component is attached to strip substrate by the way that enhancing component is laminated on peripheral part of strip substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150164301A KR20170059833A (en) | 2015-11-23 | 2015-11-23 | Strip substrate and manufacturing method thereof |
| KR10-2015-0164301 | 2015-11-23 |
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| Publication Number | Publication Date |
|---|---|
| CN106783789A true CN106783789A (en) | 2017-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610652235.8A Pending CN106783789A (en) | 2015-11-23 | 2016-08-10 | Strip substrate and its manufacture method |
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| Country | Link |
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| KR (1) | KR20170059833A (en) |
| CN (1) | CN106783789A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950212A (en) * | 2017-12-20 | 2019-06-28 | 海太半导体（无锡）有限公司 | Anti-warping substrate |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1163480A (en) * | 1996-03-19 | 1997-10-29 | 松下电器产业株式会社 | Chip carrier and semiconductor device with it |
| JP2001053108A (en) * | 1999-08-06 | 2001-02-23 | Sharp Corp | Semiconductor device, manufacture thereof, and liquid crystal module, and mounting method therefor |
| CN101261967A (en) * | 2008-04-29 | 2008-09-10 | 日月光半导体制造股份有限公司 | Enhanced encapsulation carrier board and its making method |
| CN101325182A (en) * | 2007-06-15 | 2008-12-17 | 日本特殊陶业株式会社 | Wiring substrate with reinforcing member |
| CN101621894A (en) * | 2008-07-04 | 2010-01-06 | 富葵精密组件(深圳)有限公司 | Circuit board assembling method and circuit board prefabricated product |
| CN103596354A (en) * | 2012-08-14 | 2014-02-19 | 钰桥半导体股份有限公司 | Hybrid wiring board with built-in stopper, interposer and build-up circuitry |
| CN103936291A (en) * | 2013-01-18 | 2014-07-23 | 大高Tech有限公司 | Bearing Device Frame Structure |
| CN104094387A (en) * | 2012-02-09 | 2014-10-08 | 罗伯特·博世有限公司 | Connecting device for electrical and/or electronic components |
-
2015
- 2015-11-23 KR KR1020150164301A patent/KR20170059833A/en not_active Application Discontinuation
-
2016
- 2016-08-10 CN CN201610652235.8A patent/CN106783789A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1163480A (en) * | 1996-03-19 | 1997-10-29 | 松下电器产业株式会社 | Chip carrier and semiconductor device with it |
| JP2001053108A (en) * | 1999-08-06 | 2001-02-23 | Sharp Corp | Semiconductor device, manufacture thereof, and liquid crystal module, and mounting method therefor |
| CN101325182A (en) * | 2007-06-15 | 2008-12-17 | 日本特殊陶业株式会社 | Wiring substrate with reinforcing member |
| CN101261967A (en) * | 2008-04-29 | 2008-09-10 | 日月光半导体制造股份有限公司 | Enhanced encapsulation carrier board and its making method |
| CN101621894A (en) * | 2008-07-04 | 2010-01-06 | 富葵精密组件(深圳)有限公司 | Circuit board assembling method and circuit board prefabricated product |
| CN104094387A (en) * | 2012-02-09 | 2014-10-08 | 罗伯特·博世有限公司 | Connecting device for electrical and/or electronic components |
| CN103596354A (en) * | 2012-08-14 | 2014-02-19 | 钰桥半导体股份有限公司 | Hybrid wiring board with built-in stopper, interposer and build-up circuitry |
| CN103936291A (en) * | 2013-01-18 | 2014-07-23 | 大高Tech有限公司 | Bearing Device Frame Structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109950212A (en) * | 2017-12-20 | 2019-06-28 | 海太半导体（无锡）有限公司 | Anti-warping substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20170059833A (en) | 2017-05-31 |
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