CN106783727B - The forming method of interconnection structure - Google Patents

The forming method of interconnection structure Download PDF

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Publication number
CN106783727B
CN106783727B CN201510817979.6A CN201510817979A CN106783727B CN 106783727 B CN106783727 B CN 106783727B CN 201510817979 A CN201510817979 A CN 201510817979A CN 106783727 B CN106783727 B CN 106783727B
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Prior art keywords
layer
cap
forming method
interconnection structure
hole
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CN106783727A (en
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周鸣
李小雨
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

Abstract

A kind of forming method of interconnection structure, the forming method of the interconnection structure include: offer substrate；Dielectric layer is formed in the substrate surface；Cap is formed in the dielectric layer surface；Mask layer is formed in the nut cap layer surface, the mask layer exposes part nut cap layer surface；Using mask layer as exposure mask, etching cap to dielectric layer surface forms opening in cap；The side wall for etching the mask layer exposes the surface of part cap；The dielectric layer of opening etched portions thickness in the cap forms first through hole；Oxidation processes are carried out to the part cap that opening sidewalls are not covered by mask layer, form oxide layer；The dielectric layer to substrate surface is etched along first through hole and forms the second through-hole, and the top width of second through-hole is made to be greater than bottom width；Form the metal layer for filling full second through-hole.The performance for the interconnection structure to be formed can be improved in the above method.

Description

The forming method of interconnection structure
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of forming method of interconnection structure.
Background technique
With introducing, the stress engineering technology, pocket of the continuous development of semiconductor process technique, such as high-K gate dielectric layer Ion implanting and material and device architecture are continued to optimize, and the size of semiconductor devices constantly reduces, adjacent semiconductor bodies Between spacing it is also smaller and smaller.
In ic manufacturing process, after semiconductor device structure such as is formed on the substrate, it is also necessary to use multiple gold Each semiconductor devices is joined together to form circuit by categoryization layer, and metalization layer includes interconnection line and the gold that is formed in contact hole Belong to plug, the metal plug in through-hole interconnection connects semiconductor devices, and interconnection line is by the metal plug on different semiconductor devices It connects to form circuit.As the size of semiconductor devices constantly reduces, the spacing between semiconductor devices also constantly reduces, Spacing between the size and through-hole of through-hole also reduces therewith.
Clear size of opening reduce, cause it is subsequent metal material is filled in through-hole, formed metal plug difficulty improve, it is existing It often will appear hole in the metal plug that technology is formed, influence the switching performance of interconnection structure.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of interconnection structure, improves the performance of interconnection structure.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, comprising: provide substrate；Described Substrate surface forms dielectric layer；Cap is formed in the dielectric layer surface；Mask layer is formed in the nut cap layer surface, it is described Mask layer exposes part nut cap layer surface；Using mask layer as exposure mask, etching cap is to dielectric layer surface, the shape in cap At opening；The side wall for etching the mask layer exposes the surface of part cap；Opening etching portion in the cap Divide the dielectric layer of thickness, forms first through hole；Oxidation processes are carried out to the part cap that opening sidewalls are not covered by mask layer, Form oxide layer；It etches the oxide layer and etches the dielectric layer to substrate surface along first through hole, form the second through-hole, make The top width of second through-hole is greater than bottom width；Form the metal layer for filling full second through-hole.
Optionally, the material of the cap is silicon carbide.
Optionally, the cap with a thickness of
Optionally, using plasma enhancing chemical vapor deposition process forms the cap.
Optionally, the reaction gas that the plasma enhanced chemical vapor deposition technique uses is tetramethylsilane or three Methyl-monosilane.
Optionally, the forming method of the mask layer includes: to form mask layer in the nut cap layer surface；Described Mask material layer surface forms graphical photoresist layer；Using the graphical photoresist layer as exposure mask, the mask material is etched Layer forms mask layer to cap.
Optionally, using plasma enhancing chemical vapor deposition process forms the mask layer.
Optionally, the mask layer with a thickness of
Optionally, the side wall of the mask layer is etched using dry etch process.
Optionally, in the dry etch process, the etching selection ratio of the mask layer and dielectric layer is greater than 20.
Optionally, the dry etch process is etching technics containing chlorine plasma.
Optionally, the material of the mask layer is boron nitride or aluminium nitride.
Optionally, the part cap that opening sidewalls are not covered by mask layer is carried out using oxygen plasma treatment technique Oxidation processes form oxide layer.
Optionally, the oxygen plasma treatment technique uses O2As plasma source, O2Flow be 100sccm~ 3000sccm, pressure are 0.1mtorr~10torr, and power is 100W~2000W.
Optionally, the oxide layer with a thickness of
Optionally, using the dielectric layer of fluorine-containing plasma etch process etched portions thickness, first through hole is formed.
Optionally, the dielectric layer is etched extremely using fluorine-containing plasma etch process etching oxidation layer and along first through hole Substrate surface forms the second through-hole.
Optionally, second through-hole includes the first part of position and substrate surface, and above first part Second part；The first part has vertical sidewall, and second part has sloped sidewall, and the top dimension of second part is big In bottom size.
Optionally, the sidewall slope angle of the second part of second through-hole is 45 °~90 °.
Compared with prior art, technical solution of the present invention has the advantage that
In technical solution of the present invention, dielectric layer, the cap positioned at dielectric layer surface and position are formed in substrate surface It in the mask layer of nut cap layer surface, and is formed and is open as mask etching cap using mask layer, then the side wall of etching mask layer, Part cap is exposed, after opening etch media layer formation first through hole, the cap of opening sidewalls is aoxidized Processing forms oxide layer, then etching oxidation layer, and forms the second through-hole along first through hole etch media layer, and described second is logical The top opening width in hole is greater than bottom opening width, then forms metal layer in second through-hole.Due to the second through-hole Top opening width be greater than bottom opening width avoid so being conducive to the deposited metal material in the second through-hole second There is the problems such as hole in the metal layer formed in through-hole, so as to improve the electrical connection properties of the metal layer.
Detailed description of the invention
Fig. 1 to Figure 11 is the structural schematic diagram of the forming process of the interconnection structure of the embodiment of the present invention.
Specific embodiment
As described in the background art, the performance for the interconnection structure that the prior art is formed needs to be further improved.
In the embodiment of the present invention, a kind of forming method of interconnection structure, the top width of the second through-hole of formation are provided Greater than bottom width, to be conducive to fill metal layer in the second through-hole, to improve the connectivity of the interconnection structure of formation Energy.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.
Referring to FIG. 1, providing substrate 100, dielectric layer 101 is formed on the substrate 100.
The substrate 100 can be including semiconductor materials such as silicon, germanium, SiGe or GaAs, and the substrate 100 can be with It is that body material is also possible to composite construction such as silicon-on-insulator.The substrate 100 can also include semiconductor layer and dielectric layer Composite construction.Those skilled in the art can select the semiconductor to serve as a contrast according to the semiconductor devices formed on substrate 100 The type at bottom 100, therefore the type of the substrate 100 should not limit the scope of the invention.In the present embodiment, the substrate 100 material is monocrystalline silicon.It could be formed with various semiconductor devices, such as transistor, capacitor or resistance in the substrate 100 Deng；Metal interconnection structure can also be formed in the substrate 100.
Dielectric layer 101 is formed on 100 surface of substrate, it is subsequent to form through-hole in the dielectric layer 101, described logical The metal layer of the device or interconnection structure in connection substrate 100 is formed in hole.Institute can be formed using chemical vapor deposition process State dielectric layer 101.The material of the dielectric layer 101 can be the insulating dielectric materials such as phosphorosilicate glass or boron-phosphorosilicate glass.It is described The surface of dielectric layer 101 is flat.
Referring to FIG. 2, forming cap 102 on 101 surface of dielectric layer.
The cap 102 can protect the surface of the dielectric layer 101, improves and subsequent to be formed in cap 102 The adhesion strength of mask layer, and the mask layer when cap 102 is also used to be formed subsequent etching dielectric layer.
The cap 102 is different from the material for being subsequently formed mask layer, and the two is in same etching technics, etch rate Differ larger.In the present embodiment, the material of the cap 102 is silicon carbide.Chemical gaseous phase can be enhanced with using plasma Depositing operation forms the cap 102.Specifically, the reaction gas that the plasma activated chemical vapour deposition technique uses can To be tetramethylsilane or trimethyl silane, reaction gas flow is 10sccm~1000sccm, and pressure is 20Pa~200Pa, Temperature is 100 DEG C~500 DEG C.In the present embodiment, the cap 102 of formation with a thickness ofSuch as it can be Or
Referring to FIG. 3, forming mask layer 103 on 102 surface of cap.
The mask layer 103 is used to form mask layer, logical to define subsequent to be formed in dielectric layer 101 first The positions and dimensions in hole.
There is biggish etching selection ratio between the material and dielectric layer 101 of the mask layer 103.The present embodiment In, the material of the mask layer 103 is boron nitride, and in other embodiments, the material of the mask layer 103 may be used also To be aluminium nitride.Chemical vapor deposition process can be enhanced with using plasma and form the mask layer 103.The present embodiment In, the reaction gas that the plasma activated chemical vapour deposition technique uses includes B2H6And NH3, B2H6Flow be 10sccm~ 1000sccm, NH3Flow be 10sccm~1000sccm, pressure be 1mtorr~10torr, temperature be 400 DEG C~800 DEG C.
The mask layer 103 needs enough thickness, is formed by avoid subsequent with the mask layer Mask layer is exposure mask, and during etch media layer 101, the mask layer is all lost, and the pattern of first through hole to be formed is influenced. In the present embodiment, the mask layer 103 of formation with a thickness ofSuch as it can beOr
Referring to FIG. 4, forming graphical photoresist layer 200 on 103 surface of mask layer.
Using spin coating proceeding 103 surface of mask layer formed photoresist layer after, to the photoresist layer into Row exposure development, forms the graphical photoresist layer 200, the figure of the graphical photoresist layer 200, define it is subsequent to The positions and dimensions of the first through hole of formation.
In the present embodiment, the spacing between the figure of the graphical photoresist 200 is 30nm~130nm.
Referring to FIG. 5, being exposure mask with the graphical photoresist layer 200, etches the mask layer 103 and (please refer to Fig. 4) to cap 102, mask layer 103a is formed.
Using dry etch process, it is exposure mask with the graphical photoresist layer 200, etches the mask layer 103. In the present embodiment, for the dry etch process using chlorine-containing gas as etching gas, the chlorine-containing gas can be HCl, Cl2 Or CHCl3Deng.In the present embodiment, the mask layer 103 is performed etching using etching technics containing chlorine plasma, it is described Plasma etch process uses Cl2With the mixed gas of HCl as etching gas, wherein Cl2Flow be 10sccm~ The flow of 1000sccm, HCl are 10sccm~1000sccm, and temperature is 10 DEG C~60 DEG C.
The etching technics containing chlorine plasma is exposing the etching selection ratio with higher of mask layer 103 When 102 surface of cap, stop etching, mask layer 103a is formed, by the pattern transfer of graphical photoresist layer 200 to mask layer 103a。
Referring to FIG. 6, etching cap 102 to 101 surface of dielectric layer, in nut cap using the mask layer 103a as exposure mask Opening 104 is formed in layer 102.
Before etching the cap 102, the graphical photoresist layer 200 is first removed.Wet etching can be used Or cineration technics removes the graphical photoresist layer 200.
Using dry etch process, using the mask layer 103a as exposure mask, the cap 102 is etched.The dry method is carved Etching technique can be gas containing F using the etching gas to cap 102 with higher etch rate, the etching gas Body.Specifically, etching the cap 102 using fluorine-containing plasma etch process, the plasma is carved in the present embodiment Etching technique uses CF4As etching gas, the flow of the etching gas is 10sccm~1000sccm, and temperature is 10 DEG C~60 ℃。
The fluorine-containing plasma etch process is exposing medium to the Etch selectivity with higher of cap 102 When 101 surface of layer, stop etching, forms opening 104 in cap 102.
Referring to FIG. 7, etching the side wall of the mask layer 103a, the surface of part cap 102 is exposed.
The side wall of the mask layer 103a is etched using dry etch process, specifically, the dry etch process can be with It is plasma etch process.The dry etch process can choose isotropic etching technics, to mask layer 103a's Top and side wall perform etching simultaneously, and while exposing part cap 102, the thickness of the mask layer 103a also reduces .When the dry etch process performs etching, the etching selection ratio of the mask layer 103a and dielectric layer 101 is greater than 20, To which when etching the side wall of the mask layer 103a, dielectric layer 101 is barely affected.
In the present embodiment, the side wall of the mask layer 103a is etched using etching technics containing chlorine plasma.It is described to contain chlorine Plasma etch process will not etch cap 102 and dielectric layer to mask layer 103a Etch selectivity with higher 101.The etching technics containing chlorine plasma uses Cl2As etching gas, the etching gas flow be 10sccm~ 1000sccm, pressure are 1mtorr~10torr.
In the present embodiment, the size to the mask layer 103a lateral etching isThe lateral etching Size is bigger, and the opening size for the second via top being subsequently formed is bigger.
It etches the mask layer 103a and exposes 102 surface of part cap, convenient for subsequent to the cap 102 exposure Part carries out oxidation processes.
Referring to FIG. 8, the dielectric layer 101 of the 104 etched portions thickness of opening in the cap 102, forms first Through-hole 105.
The dielectric layer 101 is performed etching using dry etch process, and the dry etch process is anisotropy Etching technics, etching direction is vertical with the surface of dielectric layer 101, forms the side wall first through hole vertical with 101 surface of dielectric layer 105。
The dry etch process can be plasma etch process, and the plasma etch process, which uses, contains fluorine gas Body includes: CF as etching gas, the etching gas4、CHF3Or C3H8One or more of equal fluoro-gas.This implementation In example, the dielectric layer 101 is performed etching using fluorine-containing plasma etch process, the etching gas used is CF4, buffering Gas is He, and pressure is 20mTorr~200mTorr, wherein CF4Flow be 50sccm~1000sccm, the flow of He is 50sccm~1000sccm.The fluorine-containing plasma etch process is to the Etch selectivity with higher of dielectric layer 101.It is described The bottom of first through hole 105 is located in dielectric layer 101.
Although fluorine-containing plasma etch process also has certain corrasion to cap 102, to dielectric layer 101 etch rate is much larger than the etch rate to cap 102, so, during forming first through hole 105, nut cap Layer 102 is by being influenced very little.
Referring to FIG. 9, the part cap 102 not covered by mask layer 103a to 104 side walls of opening carries out oxidation processes, Form oxide layer 102a.
Oxidation processes are carried out to the cap 102 using having directive oxidation technology.In the present embodiment, using etc. Gas ions treatment process carries out the oxidation processes, and oxygen plasma is made to react with 102 material of cap, forms oxide layer 102a。
In the present embodiment, the oxygen plasma treatment technique, using O2As plasma source, by controlling oxygen plasma The direction of motion of body carries out oxidation processes to the cap 102 of 104 side walls of opening.In the oxygen plasma treatment technique, O2 Flow is 100sccm~3000sccm, and pressure is 0.1mtorr~10torr, and power is 100W~2000W.In the present embodiment, The oxide layer 102a with a thickness of
In the present embodiment, the material of the cap 102 is silicon carbide, by 102 oxygen of part cap of 104 two sides that is open The material of the oxide layer 102a formed after change processing is silica, so that the oxide layer 102a is from cap 102 with different Etch rate.
It is formed referring to FIG. 10, etching the dielectric layer 101 to 100 surface of substrate along first through hole 105 (please referring to Fig. 9) Second through-hole 106 makes the top width of second through-hole 106 be greater than bottom width.
The dielectric layer 101 is etched along first through hole 105 using dry etch process, forms the second through-hole 106.It is described dry Method etching technics can be with plasma etch process, in the present embodiment, and using fluorine-containing plasma etch process, etching is given an account of Matter layer 101 forms the second through-hole 106.During etching dielectric layer 101, while the oxide layer 102a is etched, most End form is greater than the second through-hole 106 of bottom width at top width.The fluorine-containing plasma etch process can use CF4Make For etching gas, the etching gas flow can be 10sccm~1000sccm, and temperature is 10 DEG C~60 DEG C.
In the present embodiment, second through-hole 106 includes the first part 106a of position and 100 surface of substrate, and is located at Second part 106b above first part 106a；The first part 106a has vertical sidewall, and second part 106b has Sloped sidewall, and the top dimension of second part 106b is greater than bottom size.The second part 106b's of second through-hole 106 If sidewall slope angle is excessive, or causes spacing between the top of adjacent second through-hole 106 too small, subsequent logical adjacent second Electrical connection problem is easy to happen between the metal layer formed in hole 106；If the sidewall slope angle of the second part 106b It is too small, the quality for the metal layer filled in the second through-hole 106 cannot be effectively improved.In the present embodiment, the second part The sidewall slope angle of 106b is 45 °~90 °, and the sidewall slope angle is relative to the side for being parallel to the substrate surface To described 45 °~90 ° the case where not including 90 °, such as can be 50 °, 70 ° or 89 °.
The top width of second through-hole 106 is greater than bottom width, is conducive to subsequent fill out in second through-hole 106 Metal material is filled, hole occurs in surface, improves the filling quality of the metal layer formed in the second through-hole 106.
After forming second through-hole 106,106 inner wall of the second through-hole can also be cleaned, removal is carved Remaining impurity of erosion process etc., to further increase the deposition quality of the subsequent metal layer formed in the second through-hole 106.
Figure 11 is please referred to, the metal layer 107 for filling full second through-hole 106 (please referring to Figure 10) is formed.
The method for forming the metal layer 107 includes: to form full second through-hole 106 of filling and the covering mask layer The metal material layer of 103a planarizes the metal material layer, shape then using the cap 102 as stop-layer At metal layer 107.The metal material layer can be formed using chemical vapor deposition process, sputtering technology or electroplating technology.
The material of the metal layer 107 can be the metal materials such as W, Al, Cu, Ag or Au.In the present embodiment, the metal The material of layer 107 is W.
In the present embodiment, when planarizing to metal material layer, retain the cap 102 of segment thickness.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (19)

1. a kind of forming method of interconnection structure characterized by comprising
Substrate is provided；
Dielectric layer is formed in the substrate surface；
Cap is formed in the dielectric layer surface；
Mask layer is formed in the nut cap layer surface, the mask layer exposes part nut cap layer surface；
Using mask layer as exposure mask, etching cap to dielectric layer surface forms opening in cap；
The side wall for etching the mask layer exposes the surface of part cap；
The dielectric layer of opening etched portions thickness in the cap forms first through hole；
Oxidation processes are carried out to the part cap that opening sidewalls are not covered by mask layer, form oxide layer；
It etches the oxide layer and etches the dielectric layer to substrate surface along first through hole, form the second through-hole, make described the The top width of two through-holes is greater than bottom width；
Form the metal layer for filling full second through-hole.
2. the forming method of interconnection structure according to claim 1, which is characterized in that the material of the cap is carbonization Silicon.
3. the forming method of interconnection structure according to claim 1, which is characterized in that the cap with a thickness of
4. the forming method of interconnection structure according to claim 2, which is characterized in that using plasma enhances chemical gas Phase depositing operation forms the cap.
5. the forming method of interconnection structure according to claim 4, which is characterized in that the plasma enhanced chemical gas The reaction gas that phase depositing operation uses is tetramethylsilane or trimethyl silane.
6. the forming method of interconnection structure according to claim 1, which is characterized in that the forming method packet of the mask layer It includes: forming mask layer in the nut cap layer surface；Graphical photoresist layer is formed in the mask material layer surface；With institute Stating graphical photoresist layer is exposure mask, etches the mask layer to cap, forms mask layer.
7. the forming method of interconnection structure according to claim 6, which is characterized in that using plasma enhances chemical gas Phase depositing operation forms the mask layer.
8. the forming method of interconnection structure according to claim 1, which is characterized in that the mask layer with a thickness of
9. the forming method of interconnection structure according to claim 1, which is characterized in that etch institute using dry etch process State the side wall of mask layer.
10. the forming method of interconnection structure according to claim 9, which is characterized in that in the dry etch process, institute The etching selection ratio for stating mask layer and dielectric layer is greater than 20.
11. the forming method of interconnection structure according to claim 10, which is characterized in that the dry etch process be containing Chlorine plasma etching technics.
12. the forming method of interconnection structure according to claim 10, which is characterized in that the material of the mask layer is nitrogen Change boron or aluminium nitride.
13. the forming method of interconnection structure according to claim 1, which is characterized in that use oxygen plasma treatment work Skill carries out oxidation processes to the part cap that opening sidewalls are not covered by mask layer, forms oxide layer.
14. the forming method of interconnection structure according to claim 13, which is characterized in that the oxygen plasma treatment work Skill uses O2As plasma source, O2Flow is 100sccm~3000sccm, and pressure is 0.1mtorr~10torr, and power is 100W~2000W.
15. the forming method of interconnection structure according to claim 13, which is characterized in that the oxide layer with a thickness of
16. the forming method of interconnection structure according to claim 1, which is characterized in that use fluorine-containing plasma etching The dielectric layer of technique etched portions thickness forms first through hole.
17. the forming method of interconnection structure according to claim 1, which is characterized in that use fluorine-containing plasma etching Technique etching oxidation layer simultaneously etches the dielectric layer to substrate surface along first through hole, forms the second through-hole.
18. the forming method of interconnection structure according to claim 1, which is characterized in that second through-hole includes being located at The first part of substrate surface, and the second part above first part；The first part has vertical sidewall, the Two parts have sloped sidewall, and the top dimension of second part is greater than bottom size.
19. the forming method of interconnection structure according to claim 18, which is characterized in that second of second through-hole The sidewall slope angle divided is 45 °~90 °, and described 45 °~90 ° do not include 90 °, and the sidewall slope angle is relative to parallel In the direction of the substrate surface.
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CN111627808B (en) * 2019-02-28 2023-10-20 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
CN112164647B (en) * 2020-09-25 2022-12-27 华虹半导体(无锡)有限公司 Method for etching groove
CN116053203B (en) * 2023-03-07 2023-06-30 合肥晶合集成电路股份有限公司 Method for preparing interconnection structure

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CN104347488A (en) * 2013-08-07 2015-02-11 中芯国际集成电路制造(上海)有限公司 Forming method of interconnection structure

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