CN106783705A - A kind of wafer transfer approach for optimizing defects of wafer edge - Google Patents
A kind of wafer transfer approach for optimizing defects of wafer edge Download PDFInfo
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- CN106783705A CN106783705A CN201611076590.1A CN201611076590A CN106783705A CN 106783705 A CN106783705 A CN 106783705A CN 201611076590 A CN201611076590 A CN 201611076590A CN 106783705 A CN106783705 A CN 106783705A
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- 238000012546 transfer Methods 0.000 title claims abstract description 29
- 230000007547 defect Effects 0.000 title claims abstract description 22
- 238000013459 approach Methods 0.000 title claims abstract description 20
- 238000010521 absorption reaction Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 20
- 230000005540 biological transmission Effects 0.000 claims description 10
- 238000007373 indentation Methods 0.000 claims description 5
- 230000007306 turnover Effects 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 abstract description 6
- 239000001307 helium Substances 0.000 abstract description 5
- 229910052734 helium Inorganic materials 0.000 abstract description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 144
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
- H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a kind of wafer transfer approach for optimizing defects of wafer edge, four possible blocking positions during by judging wafer alignment breach in advance by isolation valve position sensors, initial angle is carried out on controller is carried, the setting of the single anglec of rotation and rotation angle range, to avoid wafer alignment breach from causing the erroneous judgement for carrying controller to wafer home position by position sensor from four blocking positions, so as to realize transmitting wafer the precise control of position, reach the purpose for making wafer be placed in Electrostatic Absorption disk center, the generation of delay machine and the crystal edge defect that avoid causing backside helium gas flow amount to cause extremely.It is convenient that the inventive method is realized, effect is significant, is applicable to processing procedure higher to alignment request to crystal circle center in technical process.
Description
Technical field
The present invention relates to microelectronic, transmitted more particularly, to a kind of wafer for optimizing defects of wafer edge
Method.
Background technology
With the development of semiconductor integrated circuit technology, dimensions of semiconductor devices constantly reduces, to the manufacturing technology of device
It is required that more and more higher, therefore, the required precision overlapped between wafer and Electrostatic Absorption disk center in etching cavity during for etching
Also more and more higher.
Can all be recorded at it per wafer and be designed with alignment notch at wafer numbering, when wafer adsorption is on Electrostatic Absorption disk
When, the Electrostatic Absorption panel surface at the alignment notch will just be exposed.Therefore, shallow ridges is groove etched or etching polysilicon during,
In order to protect Electrostatic Absorption disk, it is to avoid it is subjected to the continuous bombardment of plasma on the surface that wafer alignment indentation, there is exposed, extension
Its service life, when the gradually transmission of wafer is carried out by carrying arm, takes between wafer and wafer every time according to suitable
The mode that clockwise turns an angle successively is transmitted, and is successively adsorbed on Electrostatic Absorption disk to work as different wafers
When, the position of alignment notch on each wafer on Electrostatic Absorption disk constantly converts, with minimizing electrostatic suction tray in same position
It is subjected to the continuous bombardment of plasma.But while shallow trench isolation and polycrystalline silicon etching process technology reach its maturity, there is also
Some following problems.
Refer to Fig. 1-Fig. 4, Fig. 1-Fig. 4 is location status schematic diagram when wafer passes through etching cavity separation valve door.Such as
Shown in Fig. 1, etching cavity is provided with for transmitting isolating valve F during wafer for wafer turnover, in the both sides of isolating valve F, with left and right
Asymmetric manner is respectively provided with a position sensor G, forms asymmetrical position sensor G, in the side profile of wafer two position
Put and sense passing through for wafer respectively.Therefore, when the edge of wafer is by cavity separation valve door F, four times are had block and be placed in
The chance of the asymmetric position sensor G on valve.When the alignment notch E of wafer is asymmetric without two in transmit process
Position sensor G wherein any one when, the carrying controller of link position sensor G just can accurately recognize first by
The A points position of the crystal round fringes for sensing.Afterwards, during the wafer passes through, the position B on wafer will successively be recognized
Point, C points and D points, as shown in figs 2-4.
Refer to Fig. 5-Fig. 6, Fig. 5-Fig. 6 be respectively the non-aligned gap position of wafer by position sensor when and wafer pair
The wafer home position of controller calculating and the pass of wafer actual home position are carried when quasi- gap position is by position sensor
It is schematic diagram.As shown in figure 5, carrying tetra- point positions of crystal round fringes A, B, C, D that controller can sense according to position sensor
Put, the home position of wafer is accurately calculated by its line and symmetrical center line, and correct the final placement position for carrying arm
Put, so as to wafer to be placed in the correct position being aligned with Electrostatic Absorption disk center.
As shown in fig. 6, when wafer alignment breach passes through any one position sensor in wafer transmit process, such as just
The good position sensor by the isolating valve left side, then the position for carrying the crystal round fringes A points that controller is recognized will be as wafer
The edge of breach；Afterwards, position B points, C points and D points are can obtain successively.Because the distance of the A points to the wafer center of circle is less than wafer
Radius, therefore, the wafer center of circle being so calculated will no longer be the actual center of circle of wafer, thus calculate the center of circle (reality of diagram
Line is justified) skew is there occurs with the actual center of circle (broken circle of diagram), cause the final installation position in the actual center of circle of wafer will deviate from
The center of Electrostatic Absorption disk.
Shallow ridges is groove etched or etching polysilicon during, in order to protect Electrostatic Absorption disk, will be suitable between wafer and wafer
Sequence is gradually transmitted by the way of deflection certain angle in the direction of the clock.But such load mode has determination
Hidden danger：When certain wafer deflect into its alignment notch just by position sensor position when, carry controller judge
Erroneous judgement just occurs during the wafer center of circle.As indicated with 6, the A points relative to non-notched wafer by when the A points position that obtains it is inclined
To the interior survey of wafer, and the change of A points position, the center of circle being calculated by A-B lines and C-D lines will be caused to deviate actual
The center of circle.Carry arm and transmit wafer according to the home position that is calculated, will accurate placement wafer in Electrostatic Absorption disk
Center.
Due to the limitation that currently used dry etching equipment is designed, position sensor and carrying controller all cannot be just
Really identification wafer alignment breach and real crystal round fringes, thus cannot by wafer accurate placement in the center of Electrostatic Absorption disk,
Cause the Traffic Anomaly of the cooling helium sprayed by the Electrostatic Absorption disk back side higher.The big flow helium can be by Electrostatic Absorption disk side
The etching product of edge is splashed to the surface of wafer, so as to the exception for causing wafer defect increases, will particularly cause wafer side
Low yield or zero yield issues at edge.
The content of the invention
It is an object of the invention to the drawbacks described above for overcoming prior art to exist, there is provided one kind lacks for optimizing crystal round fringes
Sunken wafer transfer approach.
To achieve the above object, technical scheme is as follows：
A kind of wafer transfer approach for optimizing defects of wafer edge, the wafer is sent to etching by carrying arm
On Electrostatic Absorption disk in cavity, the etching cavity is provided with the isolating valve for wafer turnover, and the isolating valve both sides are with non-
Symmetric mode is respectively provided with a position sensor, described to carry arm and position sensor for sensing passing through for wafer respectively
Controller is carried in connection respectively, and the wafer transfer approach is comprised the following steps：
Step S01：Using the alignment notch on wafer as the starting point of the anglec of rotation, wafer biography is set on controller is carried
Initial angle, the single anglec of rotation and rotation angle range when sending, so that wafer arbitrarily rotates in rotation angle range
When, its alignment notch is in transmit process all without by any one in two position sensors；
Step S02：Carry arm and capture first wafer according to initial angle, transmitted to isolating valve direction, carry control
Four positions of the non-aligned indentation, there of crystal round fringes that device senses according to two position sensors, calculate the essence in the wafer center of circle
True position, and the final placement location for carrying arm is corrected, wafer is sent into etching cavity, wafer is placed in Electrostatic Absorption disk
On, and carry out technique positioned at the position of center alignment；
Step S03：After completing technique, first wafer is exited；
Step S04：Carry arm and gradually transmitted in rotation angle range and rotated relative to previous wafer rotation single
The subsequent wafer of angle carries out technique, until completing the wafer transmission of whole batch.
Preferably, the position on wafer direction of transfer as the starting point of the wafer anglec of rotation is located at using alignment notch, its is right
The initial angle answered is zero degree.
Preferably, the starting point using alignment notch towards the position of wafer direction of transfer as the wafer anglec of rotation.
Preferably, using alignment notch dorsad wafer direction of transfer position as the wafer anglec of rotation starting point.
Preferably, the rotation angle range rotates with initial angle as starting point to some singles of its both sides symmetric deflection
Angle is constituted.
Preferably, when certain wafer rotates the maximum angle into rotation angle range, next wafer is returned just
Beginning angle is simultaneously transmitted to one single anglec of rotation of its opposite side rotation.
Preferably, the rotation angle range turns some single anglecs of rotation with initial angle as starting point to one lateral deviation
Constitute.
Preferably, when certain wafer rotates the maximum angle into rotation angle range, next wafer is returned just
Beginning angle is transmitted.
Preferably, the size of the single anglec of rotation is determined by the opening angle of alignment notch.
From above-mentioned technical proposal as can be seen that the present invention by judging wafer alignment breach by isolating valve position sensing in advance
Four possible blocking positions during device, initial angle, the single anglec of rotation and anglec of rotation model are carried out on controller is carried
The setting enclosed, to avoid wafer alignment breach from causing carrying controller by position sensor to crystalline substance from four blocking positions
The erroneous judgement of circle home position, so as to realize transmitting wafer the precise control of position, reaching makes wafer be placed in Electrostatic Absorption disk
The purpose at center, it is to avoid cause the generation of delay machine and crystal edge defect that backside helium gas flow amount causes extremely.The inventive method reality
Now facilitate, effect is significant, be applicable to processing procedure higher to alignment request to crystal circle center in technical process.
Brief description of the drawings
Fig. 1-Fig. 4 be wafer pass through etching cavity separation valve door when location status schematic diagram；
Fig. 5-Fig. 6 be respectively the non-aligned gap position of wafer by position sensor when and wafer alignment gap position pass through
The wafer home position of controller calculating and the relation schematic diagram of wafer actual home position are carried during position sensor；
Fig. 7 is a kind of wafer transfer approach flow for optimizing defects of wafer edge of a preferred embodiment of the present invention
Figure.
Specific embodiment
Below in conjunction with the accompanying drawings, specific embodiment of the invention is described in further detail.
Refer to Fig. 1-Fig. 4.It is described in a kind of wafer transfer approach for optimizing defects of wafer edge of the invention
Wafer is sent in etching cavity and is placed on Electrostatic Absorption disk (figure is omited), the etching cavity by carrying arm (figure is omited)
It is provided with for transmitting isolating valve during wafer for wafer turnover, in the both sides of isolating valve, one is respectively provided with left and right asymmetric manner
Individual position sensor, forms asymmetrical position sensor, for sensing passing through for wafer respectively in wafer both sides outline position.
Therefore, when the edge of wafer is by cavity separation valve door, have block for four times be placed in it is asymmetric on valve
Position sensor chance.The carrying arm and position sensor connect carrying controller respectively (figure is omited).When the alignment of wafer
Breach in transmit process without two asymmetrical position sensors wherein any one when, link position sensor
Carrying controller just can accurately recognize the A points position of the crystal round fringes being sensed first.Afterwards, process is passed through in the wafer
In, will successively recognize position B points on wafer, C points and D points.By carrying controller, can to obtain two position sensors anti-
Four positional informations of crystal round fringes of feedback, such that it is able to carry out the calculating of the wafer center of circle, and finally putting for arm is carried in correction accordingly
Seated position.
Can all be recorded at it per wafer and be designed with alignment notch at wafer numbering, when wafer adsorption is on Electrostatic Absorption disk
When, the Electrostatic Absorption panel surface at the alignment notch will just be exposed.Therefore, shallow ridges is groove etched or etching polysilicon during,
In order to protect Electrostatic Absorption disk, it is to avoid it is subjected to the continuous bombardment of plasma on the surface that wafer alignment indentation, there is exposed, extension
Its service life, when the gradually transmission of wafer is carried out by carrying arm, takes between wafer and wafer every time according to suitable
The mode that clockwise turns an angle successively is transmitted, and is successively adsorbed on Electrostatic Absorption disk to work as different wafers
When, the position of alignment notch on each wafer on Electrostatic Absorption disk constantly converts, with minimizing electrostatic suction tray in same position
It is subjected to the continuous bombardment of plasma.
In specific embodiment of the invention below, Fig. 7 is referred to, Fig. 7 is one kind of a preferred embodiment of the present invention
Wafer transfer approach flow chart for optimizing defects of wafer edge.As shown in fig. 7, of the invention a kind of for optimizing wafer side
The wafer transfer approach of edge defect, it may include following steps：
Step S01：Initial angle, the single anglec of rotation and rotation angle range when setting wafer is transmitted.
Specific method is：Using the alignment notch on wafer as the starting point of the anglec of rotation, set brilliant on controller is carried
Initial angle, the single anglec of rotation and rotation angle range during circle transmission, so that wafer is any in rotation angle range
During rotation, its alignment notch is in transmit process all without by any one in two position sensors.
For example, the axis direction of the position that can be located at alignment notch on wafer direction of transfer, i.e. carrying arm is (as schemed
Vertical dotted line direction in 1) as the starting point of the wafer anglec of rotation.Now, the corresponding initial angle of the alignment notch is zero degree
(with the wafer center of circle as origin).May include the rising towards the position of wafer direction of transfer as the wafer anglec of rotation using alignment notch
Point；Or, using alignment notch dorsad wafer direction of transfer position (as shown in the alignment notch position in Fig. 1) as wafer revolve
The starting point of gyration.
The rotation angle range can revolve with initial angle as starting point to some singles of the both sides symmetric deflection of initial angle
Gyration is constituted.Or, the rotation angle range can also initial angle be starting point, turning some singles to its a certain lateral deviation revolves
Gyration is constituted.
In this case, the size of the single anglec of rotation should determine by the opening angle of alignment notch, such as single
The size of the anglec of rotation should be not less than the opening angle of alignment notch.
Step S02：First wafer is captured and transmitted according to initial angle.
Initial angle first wafer of crawl for carrying arm according to setting is instructed by carrying controller, to isolating valve side
To transmission.When wafer is by isolating valve, carrying controller can be non-right according to the crystal round fringes of two position sensors sensings
Four of quasi- indentation, there block dot position information, calculate the exact position in the wafer center of circle, and correct finally putting for carrying arm
Seated position.Then, wafer is sent into etching cavity from isolating valve by carrying arm, and makes the wafer center of circle with Electrostatic Absorption disk
Center is aligned, and wafer is placed in carries out technique on Electrostatic Absorption disk.
Step S03：After completing technique, first wafer is exited.
Step S04：In the way of to rotate the single anglec of rotation every time, wafer is gradually transmitted in rotation angle range.
Arm is carried according to controller instruction is carried, in the rotation angle range of setting, wafer is gradually transmitted.Often transmit
One subsequent wafer, all on the basis of the anglec of rotation of previous wafer, increase a single anglec of rotation is carried out to the wafer
Rotation, and the exact position in the wafer center of circle is calculated when by position sensor, the final placement of arm is carried in correction accordingly
Position.Then, wafer is sent into etching cavity from isolating valve by carrying arm, and makes the wafer center of circle and Electrostatic Absorption disk
The heart is aligned, and wafer is placed in carries out technique on Electrostatic Absorption disk, until completing wafer transmission and the technique of whole batch.
If the rotation angle range is with initial angle as starting point, to some lists of both sides symmetric deflection of initial angle
What the secondary anglec of rotation was constituted, then in the wafer transmission of whole batch and technical process, when certain wafer is rotated to the anglec of rotation
During the maximum angle spent in scope, initial angle is returned to next wafer and a single anglec of rotation is rotated to its opposite side
Transmitted.By that analogy, so as to the position of Electrostatic Absorption panel surface edge correspondence wafer alignment breach can be made to avoid continuously receiving
To plasma bombardment.
If the rotation angle range is with initial angle as starting point, deflects some singles to the side of initial angle and revolve
What gyration was constituted, then in the wafer transmission of whole batch and technical process, when certain wafer is rotated to anglec of rotation model
During maximum angle in enclosing, initial angle is returned to next wafer, and rotation is transmitted successively again.
In sum, the present invention by it is pre- judge wafer alignment breach by isolating valve position sensors when four it is possible
Blocking position, carries out the setting of initial angle, the single anglec of rotation and rotation angle range, to avoid on controller is carried
Wafer alignment breach causes the mistake for carrying controller to wafer home position from four blocking positions by position sensor
Sentence, so as to realize transmitting wafer the precise control of position, reach the purpose for making wafer be placed in Electrostatic Absorption disk center, it is to avoid
Cause the generation of delay machine and crystal edge defect that backside helium gas flow amount causes extremely.It is convenient that the inventive method is realized, effect is significant,
It is applicable to processing procedure higher to alignment request to crystal circle center in technical process, such as shallow ridges is groove etched or etching polysilicon system
Journey.
Above-described is only the preferred embodiments of the present invention, and the embodiment simultaneously is not used to limit patent guarantor of the invention
Shield scope, therefore every equivalent structure change made with specification of the invention and accompanying drawing content, similarly should be included in
In protection scope of the present invention.
Claims (9)
1. a kind of wafer transfer approach for optimizing defects of wafer edge, the wafer is sent to etch chamber by carrying arm
On Electrostatic Absorption disk in body, the etching cavity is provided with the isolating valve for wafer turnover, and the isolating valve both sides are with non-right
Title mode is respectively provided with a position sensor, for sensing passing through for wafer, the carrying arm and position sensor point respectively
Controller Lian Jie not carried, it is characterised in that the wafer transfer approach is comprised the following steps：
Step S01：Using the alignment notch on wafer as the starting point of the anglec of rotation, when wafer transmission is set on controller is carried
Initial angle, the single anglec of rotation and rotation angle range so that wafer is in rotation angle range during any rotation, its
Alignment notch is in transmit process all without by any one in two position sensors；
Step S02：Carry arm and capture first wafer according to initial angle, transmitted to isolating valve direction, carry controller root
Four positions of the non-aligned indentation, there of crystal round fringes sensed according to two position sensors, calculate the accurate position in the wafer center of circle
Put, and correct the final placement location for carrying arm, wafer is sent into etching cavity, wafer is placed on Electrostatic Absorption disk,
And carry out technique positioned at the position of center alignment；
Step S03：After completing technique, first wafer is exited；
Step S04：Carry arm and gradually transmitted in rotation angle range and rotate the single anglec of rotation relative to previous wafer
Subsequent wafer carry out technique, until complete whole batch wafer transmission.
2. the wafer transfer approach for optimizing defects of wafer edge according to claim 1, it is characterised in that to be aligned
Breach is located at starting point of the position on wafer direction of transfer as the wafer anglec of rotation, and its corresponding initial angle is zero degree.
3. the wafer transfer approach for optimizing defects of wafer edge according to claim 2, it is characterised in that to be aligned
Breach towards the position of wafer direction of transfer as the wafer anglec of rotation starting point.
4. the wafer transfer approach for optimizing defects of wafer edge according to claim 2, it is characterised in that to be aligned
Breach dorsad wafer direction of transfer position as the wafer anglec of rotation starting point.
5. the wafer transfer approach for optimizing defects of wafer edge according to claim 2, it is characterised in that the rotation
Gyration scope is constituted with initial angle as starting point to some single anglecs of rotation of its both sides symmetric deflection.
6. the wafer transfer approach for optimizing defects of wafer edge according to claim 5, it is characterised in that when certain
When wafer rotates the maximum angle into rotation angle range, initial angle is returned to next wafer and is rotated to its opposite side
One single anglec of rotation is transmitted.
7. the wafer transfer approach for optimizing defects of wafer edge according to claim 2, it is characterised in that the rotation
Gyration scope turns some single anglecs of rotation and constitutes with initial angle as starting point, to one lateral deviation.
8. the wafer transfer approach for optimizing defects of wafer edge according to claim 7, it is characterised in that when certain
When wafer rotates the maximum angle into rotation angle range, initial angle is returned to next wafer and is transmitted.
9. the wafer transfer approach for optimizing defects of wafer edge according to claim 1, it is characterised in that the list
The size of the secondary anglec of rotation is determined by the opening angle of alignment notch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076590.1A CN106783705B (en) | 2016-11-30 | 2016-11-30 | It is a kind of for optimizing the wafer transfer approach of defects of wafer edge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076590.1A CN106783705B (en) | 2016-11-30 | 2016-11-30 | It is a kind of for optimizing the wafer transfer approach of defects of wafer edge |
Publications (2)
| Publication Number | Publication Date |
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| CN106783705A true CN106783705A (en) | 2017-05-31 |
| CN106783705B CN106783705B (en) | 2019-05-14 |
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| CN201611076590.1A Active CN106783705B (en) | 2016-11-30 | 2016-11-30 | It is a kind of for optimizing the wafer transfer approach of defects of wafer edge |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109939952A (en) * | 2019-03-15 | 2019-06-28 | 福建省福联集成电路有限公司 | It is a kind of for judging the device of wafer unfilled corner |
| CN115050677A (en) * | 2022-06-20 | 2022-09-13 | 上海福赛特机器人有限公司 | Wafer transmission device and method |
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|---|---|---|---|---|
| US4618292A (en) * | 1977-02-28 | 1986-10-21 | International Business Machines Corporation | Controls for semiconductor wafer orientor |
| US20040068347A1 (en) * | 2002-10-08 | 2004-04-08 | Martin Aalund | Substrate handling system for aligning and orienting substrates during a transfer operation |
| CN101889339A (en) * | 2007-12-11 | 2010-11-17 | 株式会社爱发科 | Substrate transfer apparatus, substrate transfer method and vacuum processing apparatus |
| CN102376612A (en) * | 2010-08-20 | 2012-03-14 | 东京毅力科创株式会社 | Substrate carrying mechanism, substrate carrying method, and recording medium for recording program |
| CN102738049A (en) * | 2011-04-11 | 2012-10-17 | 东京毅力科创株式会社 | Substrate transport method, substrate transport apparatus, and coating and developing system |
-
2016
- 2016-11-30 CN CN201611076590.1A patent/CN106783705B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4618292A (en) * | 1977-02-28 | 1986-10-21 | International Business Machines Corporation | Controls for semiconductor wafer orientor |
| US20040068347A1 (en) * | 2002-10-08 | 2004-04-08 | Martin Aalund | Substrate handling system for aligning and orienting substrates during a transfer operation |
| CN101889339A (en) * | 2007-12-11 | 2010-11-17 | 株式会社爱发科 | Substrate transfer apparatus, substrate transfer method and vacuum processing apparatus |
| CN102376612A (en) * | 2010-08-20 | 2012-03-14 | 东京毅力科创株式会社 | Substrate carrying mechanism, substrate carrying method, and recording medium for recording program |
| CN102738049A (en) * | 2011-04-11 | 2012-10-17 | 东京毅力科创株式会社 | Substrate transport method, substrate transport apparatus, and coating and developing system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109939952A (en) * | 2019-03-15 | 2019-06-28 | 福建省福联集成电路有限公司 | It is a kind of for judging the device of wafer unfilled corner |
| CN115050677A (en) * | 2022-06-20 | 2022-09-13 | 上海福赛特机器人有限公司 | Wafer transmission device and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106783705B (en) | 2019-05-14 |
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