CN106783618A - A kind of preparation method of silicon nanowires - Google Patents
A kind of preparation method of silicon nanowires Download PDFInfo
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- CN106783618A CN106783618A CN201611076495.1A CN201611076495A CN106783618A CN 106783618 A CN106783618 A CN 106783618A CN 201611076495 A CN201611076495 A CN 201611076495A CN 106783618 A CN106783618 A CN 106783618A
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- silicon
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- silicon nanowires
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 42
- 239000010703 silicon Substances 0.000 title claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 41
- 239000002070 nanowire Substances 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000005260 corrosion Methods 0.000 claims abstract description 9
- 230000007797 corrosion Effects 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims abstract description 6
- 238000001459 lithography Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 239000011241 protective layer Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims 2
- 239000007864 aqueous solution Substances 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 239000000243 solution Substances 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
Abstract
The invention discloses a kind of preparation method of silicon nanowires, it is mainly comprised the following steps：One silicon semiconductor material substrate；One silicon germanium semiconductor sacrifice layer；One silicon channel layer；One SiGe ohmic contact layer；SiO is grown on the epitaxial wafer piece2Protective layer；The nano thread structure of 50 nano-widths is made using the method for beamwriter lithography；Using the method etching depth of dry etching until the fin structure of silicon substrate；Silicongermanide sacrificial layer and SiGe ohmic contact layer in fin portion are fallen using selective corrosion solution corrosion；Silicon nanowires is refined using the method for numeral corrosion.
Description
Technical field
The invention belongs to field of microelectronic fabrication, and in particular to a kind of to be applied to the later silicon nanometer of 10 nm technology nodes
The preparation method of line device architecture.
Background technology
Cmos device based on silicon is faced with physics and technological challenge when channel dimensions further reduce, while silicon materials
Mobility be insufficient for faster, the requirement of the device performance of more low-power consumption.New construction is considered as to break through silicon base CMOS skill
Art is limited and physical limit, realizes the key of higher performance cmos device.Single nano-wire MOS structure and Duo Gen nanowire MOSs
Device part is widely regarded as the device architecture with superelevation grid-control ability.Developed using the nanowire MOS device of silicon raceway groove for this
Part, to meet the requirement of the CMOS technology after 10 nm technology nodes.
The content of the invention
In order to solve the development technology problem of silicon nanowires MOS device, the present invention provides a kind of making side of silicon nanowires
Method,
It is main to use silicon germanium material as corrosion sacrifice layer, using silicon materials as channel layer, by beamwriter lithography
Method obtains nano thread structure, then erodes silicongermanide sacrificial layer using the method for selective corrosion.The present invention is simple to operate, with
Conventional silicon technology is compatible.Preparation method proposed by the present invention meets the later silicon nano-wire device of 10 nm technology nodes
Make.
A kind of preparation method of silicon nanowires that the present invention is provided, it is comprised the following steps that：
(1) a silicon semiconductor material substrate is prepared as substrate；
(2) Si of 20 nanometer thickness is grown on a silicon substrate0.8Ge0.2Semiconductor sacrificial layer；
(3) in Si0.8Ge0.2The silicon channel layer of 20 nanometer thickness is grown in semiconductor sacrificial layer；
(4) the SiGe ohmic contact layer of 30 nanometer thickness is grown on silicon channel layer；
(5) using 20 nanometers of the method growth SiO2 protective layers of PECVD on the substrate after the completion of the epitaxial growth；
(6) the nano wire dumbbell shaped pattern of the nano-width of interposition 20 is made using the method for beamwriter lithography；
(7) using the method etching depth of dry etching until the fin structure of silicon substrate；
(8) silicongermanide sacrificial layer and SiGe ohmic contact layer in fin portion are eroded using the method for wet etching；
(9) electron beam resist is removed；
(10) using the method refinement silicon nanowires of numeral corrosion.
Beneficial effect
This silicon nanowires preparation method proposed by the present invention, is set, in selective etching by simple corrosion sacrifice layer
During reach silicon nanowires refinement make, process is simple, low cost.The present invention can be obviously improved silicon nano-wire device knot
The technical barrier that structure is applied after 10 nm technology nodes in CMOS technology.
Specific implementation method
Elaboration is carried out to the present invention by specific embodiment：
A kind of preparation method of silicon nanowires that the present embodiment is proposed, it is comprised the following steps that：
(1) a silicon semiconductor material substrate is prepared as substrate；
(2) Si of 20 nanometer thickness is grown using the method for high vacuum chemical gas deposition on a silicon substrate0.8Ge0.2Partly lead
Body sacrifice layer；
(3) and then in Si0.8Ge0.2The silicon channel layer of 20 nanometer thickness is grown in semiconductor sacrificial layer；
(4) the SiGe ohmic contact layer of 30 nanometer thickness and then on silicon channel layer is grown；
(5) using 20 nanometers of the method growth SiO2 protective layers of PECVD on the substrate after the completion of the epitaxial growth；
(6) it is mask using ZEP photoresists are used, the nano-width of interposition 20 is made using the method for beamwriter lithography
Nano wire dumbbell shaped pattern；
(7) using the method etching depth of ICP etchings until the fin structure of silicon substrate；
(8) silicongermanide sacrificial layer and SiGe ohmic contact layer in fin portion are eroded using the method for wet etching；
(9) using the corrosion removal electron beam resist that removes photoresist of ZEP photoresists；
(10) finally using the method refinement silicon nanowires of oxidation+diluted hydrofluoric acid cleaning.
Claims (4)
1. a kind of preparation method of silicon nanowires, it is mainly comprised the following steps：
(1) a silicon semiconductor material substrate is prepared as substrate；
(2) Si of 20 nanometer thickness is grown on a silicon substrate0.8Ge0.2Semiconductor sacrificial layer；
(3) in Si0.8Ge0.2The silicon channel layer of 20 nanometer thickness is grown in semiconductor sacrificial layer；
(4) the SiGe ohmic contact layer of 30 nanometer thickness is grown on silicon channel layer；
(5) using 20 nanometers of the method growth SiO2 protective layers of PECVD on the substrate after the completion of the epitaxial growth；
(6) the nano wire dumbbell shaped pattern of the nano-width of interposition 20 is made using the method for beamwriter lithography；
(7) using the method etching depth of dry etching until the fin structure of silicon substrate；
(8) silicongermanide sacrificial layer and SiGe ohmic contact layer in fin portion are eroded using the method for wet etching；
(9) electron beam resist is removed；
(10) using the method refinement silicon nanowires of numeral corrosion.
2. the preparation method of a kind of silicon nanowires according to claim 1, it is characterised in that epitaxial material is to use superelevation
The method deposition of vacuum chemical vapor deposition.
3. a kind of preparation method of silicon nanowires according to claim 1, it is characterised in that the equipment that dry etching is used
It is ICP etching systems, the gas for using is CF4.
4. the preparation method of a kind of silicon nanowires according to claim 1, it is characterised in that wet etching liquid is 25%
TMAH solution is 1 with water：10 aqueous solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076495.1A CN106783618A (en) | 2016-11-30 | 2016-11-30 | A kind of preparation method of silicon nanowires |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611076495.1A CN106783618A (en) | 2016-11-30 | 2016-11-30 | A kind of preparation method of silicon nanowires |
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| CN106783618A true CN106783618A (en) | 2017-05-31 |
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| CN201611076495.1A Pending CN106783618A (en) | 2016-11-30 | 2016-11-30 | A kind of preparation method of silicon nanowires |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107871780A (en) * | 2017-11-20 | 2018-04-03 | 中国科学院上海微系统与信息技术研究所 | Field-effect transistor structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623384A (en) * | 2012-03-31 | 2012-08-01 | 上海华力微电子有限公司 | Manufacturing method of longitudinal stacking grid-last type Si-NWFET (Silicon-Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator) |
| CN103238208A (en) * | 2010-12-01 | 2013-08-07 | 英特尔公司 | Silicon and silicon germanium nanowire structures |
| US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
-
2016
- 2016-11-30 CN CN201611076495.1A patent/CN106783618A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103238208A (en) * | 2010-12-01 | 2013-08-07 | 英特尔公司 | Silicon and silicon germanium nanowire structures |
| CN102623384A (en) * | 2012-03-31 | 2012-08-01 | 上海华力微电子有限公司 | Manufacturing method of longitudinal stacking grid-last type Si-NWFET (Silicon-Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator) |
| US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107871780A (en) * | 2017-11-20 | 2018-04-03 | 中国科学院上海微系统与信息技术研究所 | Field-effect transistor structure and preparation method thereof |
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Application publication date: 20170531 |