CN106653566A - SiGe nanowire making method - Google Patents

SiGe nanowire making method Download PDF

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Publication number
CN106653566A
CN106653566A CN201611072423.XA CN201611072423A CN106653566A CN 106653566 A CN106653566 A CN 106653566A CN 201611072423 A CN201611072423 A CN 201611072423A CN 106653566 A CN106653566 A CN 106653566A
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CN
China
Prior art keywords
sige
silicon
semiconductor material
nano wire
sample
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611072423.XA
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Chinese (zh)
Inventor
刘丽蓉
王勇
丁超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongguan Guangxin Intellectual Property Services Ltd
Dongguan South China Design and Innovation Institute
Original Assignee
Dongguan Guangxin Intellectual Property Services Ltd
Dongguan South China Design and Innovation Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongguan Guangxin Intellectual Property Services Ltd, Dongguan South China Design and Innovation Institute filed Critical Dongguan Guangxin Intellectual Property Services Ltd
Priority to CN201611072423.XA priority Critical patent/CN106653566A/en
Publication of CN106653566A publication Critical patent/CN106653566A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Abstract

The invention discloses a SiGe nanowire making method. The method comprises the following steps: (1) a silicon semiconductor material is prepared as a substrate; (2) a SiGe semiconductor material layer with a thickness of 35 nanometer grows on the silicon substrate; (3) a 30-nanometer SiO2 dielectric layer grows on the SiGe semiconductor material layer; (4) electron beam photoetching and an ICP etching method are adopted to etch SiO2 nanowires with a width of 30 nanometer; (5) SiO2 serves as a mask to etch the SiGe material layer and the silicon substrate; (6) the sample is oxidized in an oxygen atmosphere in a 450-DEG annealing mode; (7) a hydrofluoric acid solution is adopted to corrode the sample, and silica is corroded; (8) steps (6) and (7) are circulated for 5 to 6 times; and (9) hydrochloric acid and ammonia water are adopted to clean the sample, and SiGe nanowires are made.

Description

A kind of preparation method of SiGe nano wire
Technical field
The invention belongs to field of microelectronic fabrication, and in particular to a kind of later SiGe of 10 nm technology nodes that is applied to is received The preparation method of nanowire device structure.
Background technology
Cmos device based on silicon is faced with physics and technological challenge when channel dimensions further reduce, while silicon materials Mobility be insufficient for faster, the requirement of the device performance of more low-power consumption.New device is considered as to break through silicon with new construction Base CMOS technology is limited and physical limit, realizes the key of higher performance cmos device.Silicon germanium material is excellent with its mobility characteristics In silicon, integrated technique is compatible with silicon CMOS technology, and silicon germanium material is considered as a kind of one of channel material of most future.Can be with By being used as raceway groove using silicon germanium material, the performance of cmos device is lifted.Simultaneously nanowire MOS device is widely regarded as having The device architecture of superelevation grid-control ability.Develop for this using the nanowire MOS device of SiGe raceway groove, to meet in 10 nanometer technologies The requirement of the later CMOS technology of node.
The content of the invention
In order to solve a development technology difficult problem for SiGe nanowire MOS device, the present invention provides a kind of system of SiGe nano wire Make method,
Annealed in the main degeneration stove using oxygen atmosphere, silicon germanium material is aoxidized, then using dilution Acid is corroded, and nano thread structure is refined, and the present invention is simple to operate, compatible with conventional silicon technology.The present invention is proposed Preparation method meet the making of the later SiGe nano-wire devices of 10 nm technology nodes.
A kind of preparation method of SiGe nano wire that the present invention is provided, it is comprised the following steps that：
(1) prepare a silicon semiconductor material as substrate, and carry out conventional organic washing and RCA cleanings；
(2) the cleaned silicon chip is put in high vacuum chemical vapor deposition system, grows 30 nanometer thickness Si0.8Ge0.2Semiconductor material layer；
(3) and then in Si0.8Ge0.2Using the method growth SiO of PECVD on semiconductor material layer230 nanometers of dielectric layer；
(4) method etched using beamwriter lithography and ICP etches 30 nanometers wide of SiO2 nano wires；
(5) with SiO2 as mask etching Si0.8Ge0.2Material layer and silicon substrate；
(6) in the degeneration stove of oxygen atmosphere, under 450 degree of annealing temperatures, sample is annealed, the time is 1 minute；
(7) 1 is adopted：The hydrofluoric acid aqueous solution corrosion sample of 50 dilution, erodes silica, and the time of corrosion is 2 points Clock；
(8) circulation carries out step (6) and (7) 5-6 time；
(9) using hydrochloric acid and ammoniacal liquor cleaning sample, Si is made0.8Ge0.2Nano wire.
Beneficial effect
This SiGe nano wire preparation method proposed by the present invention, it is long by the fin structure control device grid for making germanium, By carrying out anneal oxidation to SiGe nano wire in the annealing furnace of oxygen atmosphere, the corrosion of oxide on surface is then carried out, reached To the effect of raceway groove refinement.The present invention can be obviously improved silicon on silicon Ge nanoline device architecture after 15 nm technology nodes The technical barrier applied in CMOS technology.
Specific implementation method
Elaboration is carried out to the present invention by specific embodiment：
A kind of preparation method of SiGe nano wire that the present embodiment is proposed, it is comprised the following steps that：
(1) prepare a silicon semiconductor material as substrate, and carry out conventional organic washing and RCA cleanings；
(2) the cleaned silicon chip is put in high vacuum chemical vapor deposition system, grows 30 nanometer thickness Si0.8Ge0.2Semiconductor material layer；
(3) and then in Si0.8Ge0.2Using the method growth SiO of PECVD on semiconductor material layer230 nanometers of dielectric layer；
(4) method etched using beamwriter lithography and ICP etches 30 nanometers of wide SiO2Nano wire；
(5) with SiO2 as mask etching Si0.8Ge0.2Material layer and silicon substrate；
(6) in the degeneration stove of oxygen atmosphere, under 450 degree of annealing temperatures, sample is annealed, the time is 1 minute；
(7) 1 is adopted：The hydrofluoric acid aqueous solution corrosion sample of 50 dilution, erodes silica, and the time of corrosion is 2 points Clock；
(8) circulation carries out step (6) and (7) 5-6 time；
(9) using hydrochloric acid and ammoniacal liquor cleaning sample, Si is made0.8Ge0.2Nano wire.

Claims (3)

1. a kind of preparation method of SiGe nano wire, its step is as follows：
(1) silicon semiconductor material is prepared as substrate；
(2) method using high vacuum chemical gas deposition on the silicon chip grows the silicon germanium semiconductor material of 30 nanometer thickness Layer；
(3) using the method growth SiO of PECVD in silicon germanium semiconductor material layer230 nanometers of dielectric layer；
(4) method etched using beamwriter lithography and ICP etches 30 nanometers of wide SiO2Nano wire；
(5) with SiO2For mask etching silicon germanium material layer and silicon substrate；
(6) in the degeneration stove of oxygen atmosphere, under 450 degree of annealing temperatures, sample is annealed, the time is 1 minute；
(7) 1 is adopted：The hydrofluoric acid aqueous solution corrosion sample of 50 dilution, erodes silica, and the time of corrosion is 2 minutes；
(8) circulation carries out step (6) and (7) 5-6 time；
(9) using hydrochloric acid and ammoniacal liquor cleaning sample, SiGe nano wire is made.
2. the preparation method of a kind of SiGe nano wire according to claim 1, it is characterised in that silicon germanium semiconductor material Atomic ratio is 8：2, as Si0.8Ge0.2。
3. a kind of preparation method of SiGe nano wire according to claim 1, it is characterised in that the degeneration stove of oxygen atmosphere Interior annealing can cause 2 nanometers of germanium material surface to carry out oxidation and form oxidation germanium material.
CN201611072423.XA 2016-11-29 2016-11-29 SiGe nanowire making method Pending CN106653566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611072423.XA CN106653566A (en) 2016-11-29 2016-11-29 SiGe nanowire making method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611072423.XA CN106653566A (en) 2016-11-29 2016-11-29 SiGe nanowire making method

Publications (1)

Publication Number Publication Date
CN106653566A true CN106653566A (en) 2017-05-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611072423.XA Pending CN106653566A (en) 2016-11-29 2016-11-29 SiGe nanowire making method

Country Status (1)

Country Link
CN (1) CN106653566A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331611A (en) * 2017-06-23 2017-11-07 江苏鲁汶仪器有限公司 It is a kind of three-dimensional from the method for limiting accurate manufacture silicon nanowires post
CN107331614A (en) * 2017-06-23 2017-11-07 江苏鲁汶仪器有限公司 A kind of method and its special purpose device from limitation accurate etching silicon

Citations (7)

* Cited by examiner, † Cited by third party
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KR20090012475A (en) * 2007-07-30 2009-02-04 연세대학교 산학협력단 Method of fabricating ge nanowire
CN102751232A (en) * 2012-07-02 2012-10-24 中国科学院上海微系统与信息技术研究所 Method for preparing SiGe or Ge nanowire by using germanium concentration technology
CN103928297A (en) * 2013-12-28 2014-07-16 华中科技大学 Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure
CN104752200A (en) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 Transistor and manufacturing method thereof
CN104979211A (en) * 2014-04-10 2015-10-14 中芯国际集成电路制造(上海)有限公司 Nano wire device and manufacturing method thereof
CN105374679A (en) * 2014-08-26 2016-03-02 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof
US9431483B1 (en) * 2015-03-16 2016-08-30 United Microelectronics Corp. Nanowire and method of fabricating the same

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Publication number Priority date Publication date Assignee Title
KR20090012475A (en) * 2007-07-30 2009-02-04 연세대학교 산학협력단 Method of fabricating ge nanowire
CN102751232A (en) * 2012-07-02 2012-10-24 中国科学院上海微系统与信息技术研究所 Method for preparing SiGe or Ge nanowire by using germanium concentration technology
CN104752200A (en) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 Transistor and manufacturing method thereof
CN103928297A (en) * 2013-12-28 2014-07-16 华中科技大学 Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure
CN104979211A (en) * 2014-04-10 2015-10-14 中芯国际集成电路制造(上海)有限公司 Nano wire device and manufacturing method thereof
CN105374679A (en) * 2014-08-26 2016-03-02 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof
US9431483B1 (en) * 2015-03-16 2016-08-30 United Microelectronics Corp. Nanowire and method of fabricating the same

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Title
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331611A (en) * 2017-06-23 2017-11-07 江苏鲁汶仪器有限公司 It is a kind of three-dimensional from the method for limiting accurate manufacture silicon nanowires post
CN107331614A (en) * 2017-06-23 2017-11-07 江苏鲁汶仪器有限公司 A kind of method and its special purpose device from limitation accurate etching silicon
CN107331614B (en) * 2017-06-23 2021-05-25 江苏鲁汶仪器有限公司 Method for self-limiting accurate silicon etching and special device thereof
CN107331611B (en) * 2017-06-23 2021-06-04 江苏鲁汶仪器有限公司 Method for three-dimensional self-limiting accurate manufacturing of silicon nanowire column

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