CN106782657A - The high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit - Google Patents
The high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit Download PDFInfo
- Publication number
- CN106782657A CN106782657A CN201611264169.3A CN201611264169A CN106782657A CN 106782657 A CN106782657 A CN 106782657A CN 201611264169 A CN201611264169 A CN 201611264169A CN 106782657 A CN106782657 A CN 106782657A
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- China
- Prior art keywords
- circuit
- strengthens
- flash memory
- instantaneously
- applicable
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- Read Only Memory (AREA)
- Dc-Dc Converters (AREA)
Abstract
Instantaneously strengthen circuit the invention discloses a kind of high pressure for being applicable NOR flash memory chip, it is characterized in that, the high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit includes logic switch controller, internal logic process circuit, coupled capacitor and discharge path, whether logic switch controller is used for selecting chip using this instantaneous enhancing circuit, internal logic process circuit is used for intelligent decision, and this strengthens opportunity and the control discharge path that circuit is opened, coupled capacitor is used to produce instantaneous enhancing voltage, discharge path rushes down the excess charge in coupled capacitor when strengthening idle herein, prevent circuit from leaking electricity.The present invention increased a small area circuit on the basis of conventional charge pump circuit, in the moment for reading line feed a charging pulse is provided to charge pump output, the average power consumption of charge pump is not only reduced, startup time requirement of the high frequency read-write to high voltage electricity pump can be met with relatively small area again.
Description
Technical field
Instantaneously strengthen circuit the present invention relates to a kind of high pressure, more particularly to a kind of high pressure wink for being applicable NOR flash memory chip
Shi Zengqiang circuits.
Background technology
The reading of NOR flash memory (a kind of model of flash memory) unit needs chip internal to produce the voltage higher than power supply.With big
Capacity flash memory chips wordline (word line) it is elongated, the capacitive load of internal high pressure is also being increased rapidly.In the mistake that line feed is read
Cheng Zhong, because the electric charge of charge pump and wordline is shared, internal high pressure has the process that a moment drop is gone up again.In high frequency feelings
Under condition, this process can have a strong impact on the accuracy of reading circuit.Traditional method is that the output capacitance for increasing charge pump mitigates
The voltage step that charge share causes.And big output capacitance can bring another problem, charge pump to need the more time to reach
To voltage design value.Modern high frequency reads frequency and is above 100MHz greatly, stable within 100ns equivalent to charge pump is required.For
Above-mentioned two problems are solved simultaneously, it is necessary to design large area, the charge pump of high power consumption.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit,
The present invention increased a small area circuit on the basis of conventional charge pump circuit, be exported to charge pump in the moment for reading line feed
One charging pulse is provided, the average power consumption of charge pump is not only reduced, can meet high frequency with relatively small area again reads
Write the startup time requirement to high voltage electricity pump.
The present invention is to solve above-mentioned technical problem by following technical proposals：A kind of height for being applicable NOR flash memory chip
The instantaneous enhancing circuit of pressure, it is characterised in that the high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit includes logic switch control
Whether device processed, internal logic process circuit, coupled capacitor and discharge path, logic switch controller are used for selecting chip using this
Instantaneous enhancing circuit, the internal logic process circuit opportunity that this strengthens circuit unlatching for intelligent decision and control electric discharge are led to
Road, coupled capacitor is used to produce instantaneous enhancing voltage, and discharge path rushes down many in coupled capacitor when strengthening idle herein
Remaining electric charge, prevents circuit from leaking electricity.
Preferably, the internal logic process circuit not only can give High voltage output one lifting electricity by coupled capacitor
Pressure, can bleed off electricity unnecessary in coupled capacitor in idle again.
Preferably, the high pressure for being applicable NOR flash memory chip instantaneously strengthen circuit only chip operation need it is specific when
Between work, without influence charge pump high voltage regular path.
Preferably, the coupled capacitor while charge pump normal work as the capacitive load of High voltage output, with this
Reduce the ripple of High voltage output.
Positive effect of the invention is：Compared to conventional high-tension charge pump, the present invention is in conventional charge pump circuit
On the basis of increased a small area circuit, read line feed moment to charge pump output provide a charging pulse, not only drop
The low average power consumption of charge pump, can meet high frequency and read and write startup time to high voltage electricity pump with relatively small area again
It is required that.
Brief description of the drawings
Fig. 1 is that invention is applicable the high pressure of NOR flash memory chip and instantaneously strengthens the circuit diagram of circuit.
Fig. 2 is the circuit diagram of one of which implementation of the present invention.
Specific embodiment
Present pre-ferred embodiments are given below in conjunction with the accompanying drawings, to describe technical scheme in detail.
As shown in figure 1, the present invention be applicable NOR flash memory chip high pressure instantaneously strengthen circuit include logic switch controller,
Whether internal logic process circuit, coupled capacitor and discharge path, logic switch controller are used for selecting chip instantaneous using this
Enhancing circuit, internal logic process circuit is used for intelligent decision, and this strengthens opportunity and the control discharge path that circuit is opened, coupling
Electric capacity is closed to be used to produce instantaneous enhancing voltage, discharge path to rush down the unnecessary electricity in coupled capacitor when strengthening idle herein
Lotus, prevents circuit from leaking electricity.
As shown in Fig. 2 the present invention can also include enabling pin KICK_ENB, the first PMOS M1, the first NMOS tube M2,
Second NMOS tube M3, High voltage output HV_OUT, logic switch controller grid, the first NMOS tube simultaneously with the first PMOS M1
The grid connection of the grid of M2, the second NMOS tube M3；The drain electrode simultaneously with the first NMOS tube M2 of the source electrode of the first PMOS M1, the
The drain electrode of two NMOS tube M3, coupled capacitor C1, supply voltage controller HV_OUT connections.The drain electrode of the second NMOS tube M3 with couple
Capacitance connection；The source electrode of the source electrode of the first NMOS tube M2 and the second NMOS tube M3 is all grounded.
Operation principle of the invention is as follows：
During non-line feed, it is height, the first PMOS M1 shut-offs, the first NMOS tube M2 and the 2nd NMOS to enable pin KICK_ENB
Pipe M3 is turned on, and connecting line a1 ground connection, coupled capacitor plays stable high voltage defeated as a part for the load capacitance of high voltage electricity pump
Go out, reduce the effect of ripple；The moment of line feed, enable pin KICK_ENB and jump low, the first PMOS M1 conductings, the first NMOS tube
M2 and the second NMOS tube M3 is turned off, and connecting line a1 is charged to supply voltage, and supply voltage controller HV_OUT is coupled therewith
About supply voltage of lifting, when reading so as to compensate for line feed, due to the shared caused high pressure moment reduction of electric charge.
In sum, compared to conventional high-tension charge pump, the design increased one on the basis of conventional charge pump circuit
Small area circuit, a charging pulse is provided in the moment for reading line feed to charge pump output, not only reduces the average of charge pump
Power consumption, can meet startup time requirement of the high frequency read-write to high voltage electricity pump with relatively small area again.
Particular embodiments described above, technical problem, technical scheme and beneficial effect to solution of the invention are carried out
Further describe, should be understood that and the foregoing is only specific embodiment of the invention, be not limited to
The present invention, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc., should be included in this
Within the protection domain of invention.
Claims (4)
1. a kind of high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit, it is characterised in that the applicable NOR flash memory chip
High pressure instantaneously strengthens circuit includes logic switch controller, internal logic process circuit, coupled capacitor and discharge path, and logic is opened
Whether gateway controller is used for selecting chip using this instantaneous enhancing circuit, and internal logic process circuit is for this enhancing of intelligent decision
Opportunity and control discharge path that circuit is opened, coupled capacitor is used to produce instantaneously strengthens voltage, and discharge path strengthens herein
Rush down the excess charge in coupled capacitor during idle, prevent circuit from leaking electricity.
2. the high pressure for being applicable NOR flash memory chip as claimed in claim 1 instantaneously strengthens circuit, it is characterised in that the inside
Logic processing circuit not only can give High voltage output one lifting voltage by coupled capacitor, again can be in idle by coupling
Electricity unnecessary on electric capacity is closed to bleed off.
3. the high pressure for being applicable NOR flash memory chip as claimed in claim 1 instantaneously strengthens circuit, it is characterised in that described to be applicable
The high pressure of NOR flash memory chip instantaneously strengthens the special time work that circuit only needs in chip operation, high without influence charge pump
The regular path of pressure.
4. the high pressure for being applicable NOR flash memory chip as claimed in claim 1 instantaneously strengthens circuit, it is characterised in that the coupling
Electric capacity, as the capacitive load of High voltage output, the ripple of High voltage output is reduced with this while charge pump normal work.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611264169.3A CN106782657A (en) | 2016-12-30 | 2016-12-30 | The high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611264169.3A CN106782657A (en) | 2016-12-30 | 2016-12-30 | The high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106782657A true CN106782657A (en) | 2017-05-31 |
Family
ID=58951413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611264169.3A Pending CN106782657A (en) | 2016-12-30 | 2016-12-30 | The high pressure for being applicable NOR flash memory chip instantaneously strengthens circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106782657A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191630B1 (en) * | 1998-06-18 | 2001-02-20 | Fujitsu Limited | Delay circuit and oscillator circuit using same |
| US6980047B1 (en) * | 2002-06-20 | 2005-12-27 | Taiwan Semiconductor Manufacturing Company | Low power high voltage ramp-up control circuit |
| CN102446553A (en) * | 2010-09-30 | 2012-05-09 | 三星电子株式会社 | Flash memory device and wordline voltage generating method thereof |
| CN105304131A (en) * | 2014-07-07 | 2016-02-03 | 力旺电子股份有限公司 | Charge pump system and associated control method for memory cell array |
-
2016
- 2016-12-30 CN CN201611264169.3A patent/CN106782657A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6191630B1 (en) * | 1998-06-18 | 2001-02-20 | Fujitsu Limited | Delay circuit and oscillator circuit using same |
| US6980047B1 (en) * | 2002-06-20 | 2005-12-27 | Taiwan Semiconductor Manufacturing Company | Low power high voltage ramp-up control circuit |
| CN102446553A (en) * | 2010-09-30 | 2012-05-09 | 三星电子株式会社 | Flash memory device and wordline voltage generating method thereof |
| CN105304131A (en) * | 2014-07-07 | 2016-02-03 | 力旺电子股份有限公司 | Charge pump system and associated control method for memory cell array |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170531 |
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| RJ01 | Rejection of invention patent application after publication |