CN202586924U - High-voltage side gate drive circuit resistant to power supply noise interference - Google Patents

Abstract

A high-voltage side gate drive circuit resistant to power supply noise interference comprises a floating power supply VB-VS, a dipulse generation circuit, a high-voltage level shift circuit, a noise filter circuit containing a random detuning noise filter circuit, an RS trigger, and an output drive circuit. The random detuning noise filter circuit is connected with a common-mode noise filter circuit, and a first output end and a second output end of the common-mode noise filter circuit are connected with a first output end and a second output end of the random detuning noise filter circuit; the common-mode noise filter circuit is composed of six NAND gates and four inverters, can effectively filter power supply common-mode noise generated in the floating process of a high-voltage side power supply VB, and prevent a spurious triggering phenomenon caused by common-mode noise interference in the high-voltage side circuit; the common-mode noise filter circuit adopts a pure digital circuit and has no passive device, and the circuit is simple in structure, thus being for suitable for application to chips in a high-voltage side gate drive circuit, a half-bridge drive circuit and an intelligent power module, etc.

Description

The high side gate drive circuit that a kind of anti-power supply noise disturbs

Technical field

The utility model relates to the technical field of power electronic technology mesohigh side gate driver circuit, the particularly application of chips such as high side gate drive circuit, half-bridge drive circuit and SPM.

Background technology

Development along with power electronic technology; High voltage integrated circuit is through being integrated together low-voltage control circuit, various protective circuit, high voltage power device; The integrated level and the stability of complete machine have been significantly improved; Have the integration density height, volume is little, speed is fast, advantage such as low in energy consumption, in national economy, has brought into play important effect.The half-bridge driven chip is the high voltage integrated circuit that adopts advanced floating power supply supply power mode; The monolithic that is the traditional logic circuit used of high voltage electronics and control or analog circuit is integrated, replaces the conditional electronic control system that discrete electronic devices and components are built in recent years gradually.

The half-bridge driven chip integrates low-voltage circuit and high-tension circuit, realizes the transfer of low-voltage control signal to high voltage control signal through the high voltage level shift circuit, thereby realizes the control to high lateral circuit.High lateral circuit adopts the floating power supply power supply; Dual mode is generally arranged; Power supply of bootstrap capacitor formula and charge pump type power supply are because bootstrap capacitor formula electric power-feeding structure is simple, cost is low, system applies is convenient, so most of half-bridge drive circuit adopts bootstrap capacitor formula supply power mode.Lifting along with chip compact, reliability, intelligent requirements; Some half-bridge gate drive chip also is integrated into one with power tube; Such as the IR3103 and the IR3101 product of Int Rectifier Corp, realized complete systemic-function, made things convenient for system engineer's design.

The half-bridge driven chip mainly is used for driving the power tube of external half-bridge topological structure, is divided into high side drive circuit and low side drive circuit.High side drive circuit adopts the floating power supply power supply, in high lateral circuit with on the lead that floating power supply is connected, all the floating power supply noise can be arranged, and wherein outstanding is; Externally in the power tube switching process; The unsteady noise of power supply produces displacement current on high voltage level shift circuit LDMOS pipe, this displacement current passes through the drain terminal resistance of high voltage level shift circuit, thereby on drain terminal resistance, produces pressure drop; If noise ratio is bigger; Late-class circuit is thought the triggering signal when being operate as normal by mistake after with this noise pickup so, will cause the false triggering of external power pipe to cause locking so, and this noise is exactly so-called common-mode noise.Because the deviation in the technology manufacture process; Two-way high voltage level shift circuit will appear and not match; The output signal of high voltage level shift circuit also has the noise of lacking of proper care at random except having bigger common-mode noise, and these noises all might cause the false triggering of external power pipe.The half-bridge driven chip of Fairchild Semiconductor contains anti-common-mode noise and suppresses circuit, is but its common-mode noise suppresses the circuit major defect: 1. be analog circuit, the structure more complicated that circuit is whole, implementation difficulty; 2. passive device is arranged, and chip occupying area is big; 3. when the chip operate as normal, have power supply to arrive the current path on ground, power consumption is bigger.

The utility model content

The utility model disturbs the deficiency of prior art to the anti-common-mode noise of high side gate drive circuit; The high side gate drive circuit that provides a kind of anti-power supply noise simple in structure, that adopt totally digital circuit to disturb has effectively been eliminated the common-mode noise and the interference of noise of lacking of proper care at random that high-pressure side power supply VB floats and brings.

The technical scheme of the utility model is:

The high side gate drive circuit that a kind of anti-power supply noise disturbs; Comprise floating power supply VB-VS, dipulse produces circuit, high voltage level shift circuit; The noise filter circuit that contains the noise filter circuit of lacking of proper care at random; Rest-set flip-flop, output driving circuit, wherein dipulse produces circuit with low-voltage control signal V _InConvert burst pulse V to _OnWith burst pulse V _OffInput as the high voltage level shift circuit; The high voltage level shift circuit is accomplished the conversion of low-voltage control signal to high voltage control signal; High voltage control signal is through the filtering of noise filter circuit then; Pass through rest-set flip-flop again; Rest-set flip-flop is reduced to high side gate drive circuit control signal with narrow pulse signal; Control signal increases its driving force through output driving circuit again; It is characterized in that: on the noise filter circuit of lacking of proper care at random, be connected with the common-mode noise filter circuit; And first, second output of common-mode noise filter circuit is connected with first, second input of the noise filter circuit of lacking of proper care at random; Said common-mode noise filter circuit is made up of first NAND gate, second NAND gate, the 3rd NAND gate, the 4th NAND gate, the 5th NAND gate, the 6th NAND gate and first inverter, second inverter, the 3rd inverter, the 4th inverter; An input of first NAND gate is connected with an input of the 3rd NAND gate and as an input of common-mode noise filter circuit; Another input of first NAND gate is connected with an input of second NAND gate and as another input of common-mode noise filter circuit; The output of first NAND gate is connected with another input of second NAND gate and another input of the 3rd NAND gate respectively, and the output of the output of second NAND gate and the 3rd NAND gate is connected with two inputs of the 4th NAND gate respectively, and the output of the 4th NAND gate is connected and is used for control signal A is transferred to the 5th NAND gate and the 6th NAND gate with an input of the 5th NAND gate and an input of the 6th NAND gate respectively; An input of said first NAND gate is connected with another input of the 6th NAND gate through the 3rd inverter and the 4th inverter successively; Another input of said first NAND gate is connected with another input of the 5th NAND gate through first inverter and second inverter successively, and the output of said the 5th NAND gate is as first output of common-mode noise filter circuit, and the output of said the 6th NAND gate is as second output of common-mode noise filter circuit.

Compared with prior art, the utlity model has following advantage:

1, the utility model can effectively reduce in the chip operation process high side power supply and float the common-mode noise that produced and the noise of lacking of proper care at random to the influence of circuit working state, guarantees that the normal signal of high lateral circuit does not receive noise jamming.

2, the utility model circuit structure is simple, and does not have passive device.Anti-common mode power supply noise interfered circuit only needs six NAND gates and four inverters, is totally digital circuit, and to compare circuit structure simple with other anti-common mode power supply noise circuit, and do not use passive device in the circuit structure, and chip area is little.

3, common-mode noise suppresses the low in energy consumption of circuit.Traditional anti-common-mode noise suppresses circuit, when the chip operate as normal, has power supply to arrive the current path on ground, and power consumption is bigger.The circuit structure that the utility model adopted is a totally digital circuit, and power consumption is very low.

4, the domain way of realization is simple, and in the anti-common-mode noise circuit of conventional analogue, very high for the symmetry and the matching requirement of domain, the circuit of the utility model is a totally digital circuit, and is lower to the requirement of domain symmetry and matching.

Description of drawings

Fig. 1 is the basic topological structure that half-bridge drive circuit drives the external power pipe.

Fig. 2 be the utility model can be anti-the structured flowchart of the high side gate drive circuit that disturbs of power supply noise.

Fig. 3 is the internal structure schematic diagram of noise filter circuit.

Sequential chart when Fig. 4 is high-pressure side circuit operate as normal.

Fig. 5 is the working timing figure of the utility model noise filter circuit.

Embodiment

Like Fig. 1, Fig. 2 and shown in Figure 3, the high side gate drive circuit that a kind of anti-power supply noise disturbs comprises floating power supply VB-VS; Dipulse produces circuit 1; High voltage level shift circuit 2, noise filter circuit 3, rest-set flip-flop 4; Output driving circuit 5, wherein dipulse produces circuit 1 with low-voltage control signal V _InConvert burst pulse V to _OnWith burst pulse V _OffExport to high voltage level shift circuit 2; High voltage level shift circuit 2 is accomplished the conversion of low-voltage control signal to high voltage control signal; Signal is through the filtering of noise filter circuit 3 then, through rest-set flip-flop 4 narrow pulse signal is reduced to the control signal of high side gate driver circuit then, passes through output driving circuit 5 again; Increase the driving force of control signal, wherein the effective trigger of low level formed by two NAND gates of rest-set flip-flop 4.It is characterized in that: noise filter circuit 3 also comprises common-mode noise filter circuit 3-1 and the noise filter circuit 3-2 that lacks of proper care at random.Common-mode noise filter circuit 3-1 is made up of six NAND gate NAND1-NAND6 and four inverter inv1-inv4; They are supplied power by floating power supply VB-VS; Input connects the output of inverter in the high voltage level shift circuit, and output meets the noise filter circuit 3-2 that lacks of proper care at random.Wherein, The input of NAND gate NAND1 meets the output V_set and the V_rst of high voltage level shift circuit; The input of NAND gate NAND2 connects the output of V_set and NAND gate NAND1; The input of NAND gate NAND3 connects the output of V_rst and NAND gate NAND1, and the input of NAND gate NAND4 connects the output of NAND gate NAND2 and the output of NAND gate NAND3, then NAND gate NAND4 output control signal A.The inverter inv1 of set passage, its input meets the output V_set of high voltage level shift circuit, and output meets inverter inv2, the inverter inv3 of reset passages, its input meets the output V_rst of high voltage level shift circuit, and output meets inverter inv4.The input of NAND gate NAND5 meets output and the control signal A of inverter inv2, output asserts signal Vset1, and the input of NAND gate NAND6 meets output and the control signal A of inverter inv4, output reset signal Vrst1.

The noise filter circuit 3-2 that lacks of proper care at random comprises asserts signal V_set imbalance noise filter circuit and reset signal V_rst imbalance noise filter circuit, and input meets the output Vset1 and the Vrst1 of common-mode noise filter circuit respectively, and output is respectively Vset and Vrst.Wherein asserts signal V_set imbalance noise filter circuit is managed M1 by PMOS; NMOS manages M2; Filter resistance R3 and filter capacitor C1 form, the source termination floating power supply VB of PMOS pipe M1, the source termination of the NMOS pipe M2 ground VS that floats; Through resistance R 3 and capacitor C 1 filtered asserts signal, export Vset after the shaping through Schmidt trigger SMT1 again; Reset signal V_rst imbalance noise filter circuit is managed M3 by PMOS; NMOS manages M4; Filter resistance R4 and filter capacitor C2 form, the source termination floating power supply VB of PMOS pipe M3, the source termination of the NMOS pipe M4 ground VS that floats; Through resistance R 4 and capacitor C 2 filtered asserts signal, export Vrst after the shaping through Schmidt trigger SMT2 again.

As shown in Figure 2; The high side gate drive circuit that a kind of anti-power supply noise of the utility model disturbs; Comprise that mainly dipulse produces circuit 1, high voltage level shift circuit 2, noise filter circuit 3, rest-set flip-flop 4 and output driving circuit 5, wherein noise filter circuit comprises common-mode noise circuit 3-1 and the noise filter circuit 3-2 that lacks of proper care at random.In order to reduce the conducting power consumption of LDMOS pipe in the high voltage level shift circuit, the low-pressure side control signal is to the form work of on high-tension side signal transmission employing burst pulse, and dipulse generation circuit converts the switching signal Vin of high side into two burst pulse control signal V _OnAnd V _OffThe effect of high voltage level shift circuit is the burst pulse control signal V with low-pressure side _OnAnd V _OffConvert on high-tension side burst pulse control signal into; Noise filter circuit comprises common-mode noise filter circuit 3-1 and the noise filter circuit 3-2 that lacks of proper care at random, and when high side power supply VB did not fluctuate, the common-mode noise filter circuit was inoperative; Do not influence the transmission of normal signal; The noise filter circuit of lacking of proper care at random falls the imbalance noise filtering that is mingled with in the normal signal, sends signal to rest-set flip-flop then, accomplishes the transmission of signal in high side; When high side power supply VB fluctuates; The fluctuation of power supply VB will produce the dv/dt noise; Drain electrode at LDMOS pipe L1 and L2 forms one displacement current then, and this displacement current flows through the drain resistance R1 and the R2 of LDMOS pipe, on resistance R 1 and R2, produces pressure drop; Drain electrode at LDMOS pipe L1 and L2 all can produce a negative pulse noise with certain pulse duration like this; Through the output of level inverter later, the negative pulse noise has just got into high lateral circuit so then, and wherein zener Z1 and Z2 protection back level inverter is used.The noise filter circuit itself of wherein lacking of proper care at random also has certain common-mode noise filter function, but when the dv/dt noise ratio is big, the duration, it just can not filter this false negative pulse noise when long, causes the false triggering of back level power tube.Increase common-mode noise rate circuit and just can effectively address this problem, circuit structure is simple, and used device is few, and there do not have passive device to take chip area to be little, and logic gates is unified, all is NAND gate and inverter.

In conjunction with Fig. 1 and Fig. 2, introduce the principle that half-bridge driven chip mesohigh lateral circuit power supply noise produces in detail: the high-pressure side circuit is realized floating power supply by floating power supply VB-VS power supply through boostrap circuit, and wherein boostrap circuit is by power supply VCC, bootstrap diode D _B, bootstrap capacitor C _BForm, power supply VCC meets bootstrap diode D _BAnode, diode D _BNegative electrode meet VB and bootstrap capacitor C _BTop crown, C _BBottom crown connect float ground VS.When the external power pipe is managed M down _LTurn-off, on manage M _HDuring unlatching, the high pressure ground VS voltage of floating rises rapidly and produces the dv/dt noise, and high pressure is floated the variation of ground VS voltage through bootstrap capacitor C _BBe coupled on the floating power supply line VB; The variation of floating power supply VB will form one displacement current in the drain electrode of LDMOS pipe; This displacement current flows through the drain resistance of LDMOS pipe; On drain resistance, produce pressure drop, so just the drain electrode at the LDMOS pipe produces a negative pulse noise, and this negative pulse noise enters into high lateral circuit through inverter.Suppose that two branch road high voltage level shift circuits mate symmetry fully, also zero deflection in technology is made, resistance R 1 is just the same with resistance R 2; The variation of floating power supply VB only can produce common-mode noise so; But in actual conditions, because the deviation of technology and the drift of resistance, the variation of floating power supply VB also can produce certain noise of imbalance at random in the drain electrode of LDMOS pipe; This noise of lacking of proper care at random is a differential mode; Promptly when the floating power supply change in voltage, V_set and V_rst signal had both contained the common mode power supply noise, and the power supply noise of lacking of proper care is at random also arranged.

In conjunction with Fig. 3, introduce the operation principle of noise filter circuit in detail:

Noise filter circuit comprises common-mode noise filter circuit 3-1 and the noise filter circuit 3-2 that lacks of proper care at random.When floating power supply VB fluctuates; Power supply VB fluctuation meeting produces noise on holding wire V_set and V_rst, have only common-mode noise on hypothesis V_set and the V_rst signal earlier, and four NAND gate NAND1, NAND2, NAND3, NAND4 realize the XOR function; It can detect the common-mode noise on V_set and the V_rst; When common-mode noise during through four XOR gates of being made up of NAND gate NAND1-NAND4, output signal A is a low level, blocks NAND gate NAND5 and NAND gate NAND6; Make the common-mode noise that is carried on signal V_set and the V_rst can not pass through NAND gate NAND5 and NAND6, so just realized filtering V_set on the holding wire and V_rst common-mode noise.

When floating power supply VB fluctuates; Because the deviation of actual process, making not only has common-mode noise on holding wire V_set and the V_rst, and the noise of lacking of proper care at random in addition; The noise of lacking of proper care at random is a difference mode signal; It is during through four XOR gates of being made up of NAND gate NAND1-NAND4, and output signal line A is a high level, and NAND gate NAND5 and NAND gate NAND6 are opened like this; The effect of four inverter inv1, inv2, inv3, inv4 is the coupling that realizes that high side normal signal transmission postpones, and the letter V_set and the V_rst that contain the noise of lacking of proper care at random like this can be output as V_set1 and V_rst1 through the common-mode noise filter circuit smoothly.If V_set1 is last the noise of lacking of proper care is at random arranged; The pulse duration of general random imbalance noise is very narrow; PMOS pipe M1 is opened in this very narrow pulse; Give capacitor C 1 charging through resistance R 3, the amplitude of charging is less than the threshold voltage of next stage Schmidt trigger SMT1, and the noise of imbalance at random on the V_set1 is just by filtering like this; In like manner; If V_rst1 is last the noise of lacking of proper care is at random arranged; The pulse duration of general random imbalance noise is very narrow, and PMOS pipe M3 is opened in this very narrow pulse, gives capacitor C 2 chargings through resistance R 4; The amplitude of charging is less than the threshold voltage of next stage Schmidt trigger SMT2, and the noise of imbalance at random on the V_rst1 is just by filtering like this.

Sequential chart when Fig. 4 is high-pressure side circuit operate as normal.Vin produces circuit and high voltage level shift circuit output asserts signal V_set and reset signal V_rst through dipulse; The two is a difference mode signal; The same as differential mode noise; The common-mode noise filter circuit that passes through that difference mode signal is also had no effect is exported asserts signal V_set1 and reset signal V_rst1; The pulse duration of difference mode signal compares that the pulse duration of differential mode noise is much bigger, and the noise filter circuit of lacking of proper care at random can not impact difference mode signal, through output asserts signal Vset and reset signal Vrst after the shaping of RC filter circuit and Schmidt trigger; The asserts signal Vset of filter circuit output and reset signal Vrst latch through rest-set flip-flop 4, and narrow pulse signal is reduced to high side drive control signal V _Q, high then side drive control signal V _QExport high side drive signal H through the power amplification of overdrive circuit _O

Explain the process of noise filter circuit in conjunction with the oscillogram of Fig. 5:

When switch transition; High side floating power supply VB can produce bigger dv/dt noise; This noise produces displacement current on the drain terminal parasitic capacitance of LDMOS pipe L1 and L2, displacement current flows through resistance R 1 and produces pressure drop with R2, and warp is picking up of level inverter later; Obtain containing the signal V_set and the V_rst of noise; Suppose that because the drift of the deviation of technology and resistance makes the noise pulse width of set end compare the wideer of reset terminal wide that part of coming out is exactly the so-called noise of lacking of proper care at random, that part that pulsewidth is identical is exactly so-called common-mode noise.The XOR gate that common-mode noise is formed through NAND gate NAND1-NAND4, output signal A is a low level, and NAND gate NAND5 and NAND6 are blocked, and makes common-mode noise can not pass through NAND gate NAND5 and NAND6.Common-mode noise is with regard to filtering like this.Signal V_set and the V_rst that contains noise through the common-mode noise filter circuit after output Vset1 and Vrst1; Vset1 and Vrst1 only contain at random and have lacked of proper care noise so, and through separately imbalance noise filter circuit, the imbalance noise is also by filtering again for Vset1 and Vrst1 then; Vset and Vrst output high level; The back effective rest-set flip-flop of level low level just can not overturn, and can not cause the false triggering of external power pipe, has so just realized the inhibition to power supply noise.

Claims (1)

1. high side gate drive circuit that anti-power supply noise disturbs; Comprise floating power supply VB-VS, dipulse produces circuit (1), high voltage level shift circuit (2); The noise filter circuit (3) that contains the noise filter circuit of lacking of proper care at random (3-2); Rest-set flip-flop (4), output driving circuit (5), wherein dipulse produces circuit (1) with low-voltage control signal V _InConvert burst pulse V to _OnWith burst pulse V _OffInput as high voltage level shift circuit (2); High voltage level shift circuit (2) is accomplished the conversion of low-voltage control signal to high voltage control signal; High voltage control signal is through the filtering of noise filter circuit (3) then; Pass through rest-set flip-flop (4) again; Rest-set flip-flop (4) is reduced to high side gate drive circuit control signal with narrow pulse signal; Control signal is passed through output driving circuit (5) again increases its driving force; It is characterized in that: on the noise filter circuit of lacking of proper care at random (3-2), be connected with common-mode noise filter circuit (3-1); And first, second output of common-mode noise filter circuit (3-1) is connected with first, second input of the noise filter circuit of lacking of proper care at random (3-2); Said common-mode noise filter circuit (3-1) is made up of first NAND gate (NAND1), second NAND gate (NAND2), the 3rd NAND gate (NAND3), the 4th NAND gate (NAND4), the 5th NAND gate (NAND5), the 6th NAND gate (NAND6) and first inverter (inv1), second inverter (inv2), the 3rd inverter (inv3), the 4th inverter (inv4); An input of first NAND gate (NAND1) is connected with an input of the 3rd NAND gate (NAND3) and as an input of common-mode noise filter circuit (3-1); Another input of first NAND gate (NAND1) is connected with an input of second NAND gate (NAND2) and as another input of common-mode noise filter circuit (3-1); The output of first NAND gate (NAND1) is connected with another input of second NAND gate (NAND2) and another input of the 3rd NAND gate (NAND3) respectively; The output of the output of second NAND gate (NAND2) and the 3rd NAND gate (NAND3) is connected with two inputs of the 4th NAND gate (NAND4) respectively; The output of the 4th NAND gate (NAND4) is connected and is used for control signal A is transferred to the 5th NAND gate (NAND5) and the 6th NAND gate (NAND6) with an input of the 5th NAND gate (NAND5) and an input of the 6th NAND gate (NAND6) respectively; An input of said first NAND gate (NAND1) is connected with another input of the 6th NAND gate (NAND6) through the 3rd inverter (inv3) and the 4th inverter (inv4) successively; Another input of said first NAND gate (NAND1) is connected with another input of the 5th NAND gate (NAND5) through first inverter (inv1) and second inverter (inv2) successively; The output of said the 5th NAND gate (NAND5) is as first output of common-mode noise filter circuit (3-1), and the output of said the 6th NAND gate (NAND6) is as second output of common-mode noise filter circuit (3-1).

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