CN106712947A - Driving circuit based on quantum key distribution system - Google Patents
Driving circuit based on quantum key distribution system Download PDFInfo
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- CN106712947A CN106712947A CN201710182896.3A CN201710182896A CN106712947A CN 106712947 A CN106712947 A CN 106712947A CN 201710182896 A CN201710182896 A CN 201710182896A CN 106712947 A CN106712947 A CN 106712947A
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- driver element
- fpga circuitry
- circuit
- drive circuit
- unit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0852—Quantum cryptography
- H04L9/0858—Details about key distillation or coding, e.g. reconciliation, error correction, privacy amplification, polarisation coding or phase coding
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Theoretical Computer Science (AREA)
- Optical Communication System (AREA)
Abstract
The invention discloses a driving circuit based on a quantum key distribution system. A signal laser driving unit and a synchronous laser driving unit included in a transmitting end driving circuit comprises the same first delay circuit; a receiving end of the first delay circuit is connected to a first FPGA circuit unit directly and respectively through two paths of data cables, and one path of the data cable is connected to the first FPGA circuit unit through a level converter; a single-photon detector driving unit of a receiving end driving circuit portion comprises a second delay circuit; and the receiving end of the second delay circuit is connected to a second FPGA circuit unit directly and respectively through two paths of the data cables, and one path of the data cable is connected to the second FPGA circuit unit through the level converter. Compared with the prior art, the driving signal delay due to circuit transmission and components is adjusted by the driving circuit disclosed by the invention through a delay chip; and thus, the ideal synchronization for required signals is achieved; and the efficient production rate for quantum keys is guaranteed.
Description
Technical field
The present invention relates to safety communication technology field, more particularly to a kind of driving electricity based on quantum key dispatching system
Road.
Background technology
Drive circuit adjustable delay precision is not high or adjustable extent is very narrow in traditional secrete key distribution system, in addition, driving electricity
Road can not as the case may be adjust delay precision and scope, be particularly easy to cause the asynchronous response of each drived unit, no
Beneficial to the synchronization alignment of multiple signals so that synchronous unstable, so as to causing key dislocation in key generation process, lacking of losing
Fall into.
The content of the invention
Present invention aim at a kind of drive circuit based on quantum key dispatching system is provided, to solve in the prior art
The asynchronous response of each drived unit in key dispatching system, is unfavorable for the synchronous alignment of multiple signals so that synchronous unstable
It is fixed, so as to cause key dislocation, the technical bug lost in key generation process.
The technical proposal of the invention is realized in this way：
A kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit and receiving terminal drive electricity
Road,
The transmitting terminal drive circuit includes the first FPGA circuitry unit, first phase modulator driver element, the last the first
Degree modulator driver element, the first optical attenuator driver element, the second optical attenuator driver element, signal laser driver element
And synchronous laser driver element, the first phase modulator driver element with the first FPGA circuitry unit including connecting successively
The high-speed A/D converter and operational amplifier for connecing, wherein, the first intensity modulator driver element includes that RF is modulated and inclined
Voltage modulated is put, the RF modulation includes that the high-speed A/D converter and computing that are connected with the first FPGA circuitry unit successively are put
Big device, the bias voltage modulation includes that the low speed digital analog converter and computing that are connected with the first FPGA circuitry unit successively are put
Big device, the first optical attenuator driver element, the second optical attenuator driver element include respectively successively with the first FPGA circuitry
The low speed digital analog converter and operational amplifier of unit connection, the signal laser driver element and synchronous laser are driven
Moving cell includes same first delay circuit, and the receiving terminal of first delay circuit is directly connected to by two paths of data line respectively
First FPGA circuitry unit and all the way data wire connect the first FPGA circuitry unit, first time delay by level translator
Circuit output end connects No. four level translators, and described No. four level translator connects signal laser, synchronous laser respectively
The high-speed A/D converter of device and first phase modulator driver element part, the first intensity modulator driver element part
High-speed A/D converter；
The receiving terminal drive circuit includes the second FPGA circuitry unit, second phase modulator driver element, third phase
Position modulator driver element, synchroprobe driver element and four road single-photon detector driver elements, the second phase
Modulator driver element, third phase modulator driver element include the high speed being connected with the second FPGA circuitry unit successively respectively
Digital analog converter and operational amplifier, the single-photon detector driver element include the second delay circuit, and described second prolongs
When circuit receiving terminal respectively by two paths of data line be directly connected to the second FPGA circuitry unit and all the way data wire by electricity
Flat turn parallel operation connects the second FPGA circuitry unit, and the output end of second delay circuit connects No. six level translators respectively,
Described No. six level translator connects four road single-photon detectors and second phase modulator driver element, third phase respectively
Position modulator driver element, four road single-photon detector connects the 2nd FPGA by four road single-photon detector input interfaces
Circuit unit, the synchroprobe driver element connects synchroprobe by golden finger, and the synchroprobe connects successively
Connect two-way level translator, all the way the second delay circuit, level translator and the second FPGA circuitry unit；
The drive circuit also includes being respectively used to the transmitting of transmitting terminal drive circuit and receiving terminal drive circuitry
End power supply and receiving terminal power supply.
Preferably, first delay circuit includes the delay chip being made up of 4 AD9500 modulus conversion chips.
Preferably, second delay circuit includes the delay chip being made up of 7 AD9500 modulus conversion chips.
Preferably, the high-speed A/D converter and low speed digital analog converter are respectively adopted AD9740 chips.
Preferably, the operational amplifier uses THS3001 chips.
Compared with prior art, the present invention has following beneficial effect：
Drive circuit based on quantum key dispatching system of the invention, adjusted because of circuit transmission by delay chip and
The drive signal transmission delay that component brings, so as to reach the signal ideal synchronisation of requirement, it is ensured that quantum key is efficient
Production rate.In addition, high-speed DAC and wide output voltage range, the high speed amplifier of high pressure Slew Rate coordinate to rising edge, trailing edge, build
Between immediately, the realization of Width funtion output signal.
Brief description of the drawings
Fig. 1 is the theory diagram of the generation system of true random sequence of the present invention；
Fig. 2 is the flow chart of the generation method of true random sequence of the present invention.
In figure：Transmitting terminal drive circuit 1, the first FPGA circuitry unit 101, first phase modulator driver element 102, the
One intensity modulator driver element 103, the first optical attenuator driver element 104, the second optical attenuator driver element 105, signal
Laser drive unit 106, synchronous laser driver element 107, the first delay circuit 108, receiving terminal drive circuit 2, second
FPGA circuitry unit 201, second phase modulator driver element 202, third phase modulator driver element 203, synchronizing detection
Device driver element 204, single-photon detector driver element 205, the second delay circuit 206, level translator 3, single photon detection
Device 4, single-photon detector input interface 5, synchroprobe 6.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the present invention is clearly and completely described.
As shown in figure 1, a kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit 1 and
Receiving terminal drive circuit 2, the transmitting terminal drive circuit 1 includes that the first FPGA circuitry unit 101, first phase modulator drive
Unit 102, the first intensity modulator driver element 103, the first optical attenuator driver element 104, the second optical attenuator drive single
Unit 105, signal laser driver element 106 and synchronous laser driver element 107, the first phase modulator drive single
Unit 102 includes the high-speed A/D converter and operational amplifier that are connected with the first FPGA circuitry unit 101 successively, wherein, the
One intensity modulator driver element 103 includes that RF is modulated and bias voltage modulation, and the RF modulation is included successively with first
The high-speed A/D converter and operational amplifier of the connection of FPGA circuitry unit 101, bias voltage modulation include successively with
The low speed digital analog converter and operational amplifier of the connection of the first FPGA circuitry unit 101, first optical attenuator drives single
First 104, second optical attenuator driver element 105 includes the low speed digital-to-analogue being connected with the first FPGA circuitry unit 101 successively respectively
Converter and operational amplifier, the signal laser driver element 106 and synchronous laser driver element 107 include same
One first delay circuit 108, the receiving terminal of first delay circuit 108 is directly connected to first by two paths of data line respectively
FPGA circuitry unit 101 and all the way data wire connect the first FPGA circuitry unit 101, described first by level translator 3
The output end of delay circuit 108 connects No. four level translators 3, and described No. four level translator 3 connects signal laser respectively
106th, the high-speed A/D converter of synchronous laser 107 and the part of first phase modulator driver element 102, the first intensity are adjusted
The high-speed A/D converter of the part of device driver element 103 processed；
As shown in Fig. 2 the receiving terminal drive circuit 2 includes that the second FPGA circuitry unit 201, second phase modulator drive
Moving cell 202, third phase modulator driver element 203, the road single-photon detector of synchroprobe driver element 204 and four
Driver element 205, the second phase modulator driver element 201, third phase modulator driver element 203 respectively include according to
The secondary high-speed A/D converter and operational amplifier being connected with the second FPGA circuitry unit 201, the single-photon detector drives
Moving cell 205 includes the second delay circuit 206, and the receiving terminal of second delay circuit 206 is straight by two paths of data line respectively
The second FPGA circuitry unit 201 is connect in succession and data wire connects the second FPGA circuitry unit by level translator 3 all the way
201, the output end of second delay circuit 206 connects No. six level translators 3, described No. six level translator 3 respectively
Four road single-photon detectors 4 and second phase modulator driver element 201, third phase modulator driver element are connected respectively
203, four road single-photon detector 4 connects the second FPGA circuitry unit by four road single-photon detector input interfaces 5
201, the synchroprobe driver element 204 connects synchroprobe 6 by golden finger, and the synchroprobe 6 connects successively
Connect two-way level translator 3, all the way the second delay circuit 206, the FPGA circuitry unit 201 of level translator 3 and second；It is described
Drive circuit also include be respectively used to transmitting terminal drive circuit 1 and receiving terminal drive circuit 2 power supply transmitting terminal power supply 7 and
Receiving terminal power supply 8.First delay circuit 108 includes the delay chip being made up of 4 AD9500 modulus conversion chips.It is described
Second delay circuit 206 includes the delay chip being made up of 7 AD9500 modulus conversion chips.The high-speed A/D converter with
And low speed digital analog converter is respectively adopted AD9740 chips.The operational amplifier uses THS3001 chips.
The course of work of drive circuit each unit of the invention is as follows：
1) signal laser drives：
Receive the start pulse signal that the first FPGA circuitry unit 101 is provided, the start pulse signal enters programmable the
(time delay carries out compiling by fpga to delay circuit for the sometime time delay that one delay circuit 108 carries out in the range of 0~25ns
Journey delay time is set), it is luminous to trigger laser to recently enter signal laser.
2) synchronous laser drives：
3.3V power supplys are done to synchronous laser to power and relevant pins setting, synchronous laser is in emission state,
Then when receiving the start pulse signal that the first FPGA circuitry unit 101 is provided, the start pulse signal enters programmable the
(time delay carries out compiling by fpga to delay circuit for the sometime time delay that one delay circuit 108 carries out in the range of 0~25ns
Journey delay time is set), synchronous laser triggering laser is transferred to after programmable delay chip time delay and sends corresponding light
Pulse.
3) synchroprobe drives：
3.3V power supplys are done to synchroprobe to power and relevant pins setting, synchroprobe is in reception state,
Synchroprobe receive synchronous laser transmission come in synchronization pulse and by interface level conversion send into the 2nd FPGA
Circuit unit 201 is used as receiving terminal synchronizing datum signal.
4) intensity modulator drives：
A, RF modulation drive：The output of first FPGA circuitry unit 101 10bit data change into difference through high-speed A/D converter
Divide current signal output, the direct current signal that high-speed A/D converter is exported then is done into I-V conversions, eventually through operational amplifier
The RF interfaces for amplifying the high-quality signal output driving intensity modulator for reaching -6V~+6V are filtered to signal.This signal pair
The parameter requests such as rising edge, trailing edge, setup time, the slew rate of amplifier are：When rise and fall within time 2.5ns along setting up
Between 15ns；
B, bias voltage modulation drive：Meanwhile, intensity modulator is used for modulating bias voltage comprising low speed signal all the way, adopts
The effect of adjustable bias voltage is realized with the framework of high-speed A/D converter concatenation operation amplifier.
5) phase-modulation circuit drives：
It is defeated that the output of first FPGA circuitry unit 101 10bit data change into differential current signal through high-speed A/D converter
Go out, the direct current signal that high-speed A/D converter is exported then is done into I-V conversions, signal is filtered eventually through operational amplifier
Ripple amplifies the high-quality signal output driving phase-modulator for reaching -6V~+6V.Rising of this drive signal to operational amplifier
The parameter requests such as edge, trailing edge, setup time, slew rate are：Rise and fall are along setup time 15ns within time 2.5ns.
6) optical attenuator drives：
It is defeated that the output of first FPGA circuitry unit 101 10bit data change into differential current signal through low speed digital analog converter
Go out, the direct current signal that low speed digital analog converter is exported then is done into I-V conversions, signal is filtered eventually through operational amplifier
Ripple amplifies the first optical attenuator of high-quality signal output driving driver element 104 and the second optical attenuator drive for reaching -6V~+6V
Moving cell 105.
7) single-photon detector drives：
Receive the start pulse signal that the second FPGA circuitry unit 201 is provided, the start pulse signal enters programmable the
Two delay circuits 206 carry out in the range of 0~25ns sometime time delay (time delay pass through the second FPGA circuitry unit 201 pairs
Second delay circuit 206 carries out programmable delay set of time), single-photon detector 4 is recently entered to trigger detection process.
Drive circuit based on quantum key dispatching system of the invention, adjusted because of circuit transmission by delay chip and
The drive signal transmission delay that component brings, so as to reach the signal ideal synchronisation of requirement, it is ensured that quantum key is efficient
Production rate.In addition, the high speed amplifier of high-speed DAC and wide output voltage range, high pressure Slew Rate in system coordinate to rising edge, under
Drop edge, setup time, the realization of Width funtion output signal.
Claims (5)
1. a kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit and receiving terminal drive electricity
Road, it is characterised in that
The transmitting terminal drive circuit includes that the first FPGA circuitry unit, first phase modulator driver element, the first intensity are adjusted
Device driver element processed, the first optical attenuator driver element, the second optical attenuator driver element, signal laser driver element and
Synchronous laser driver element, the first phase modulator driver element includes what is be connected with the first FPGA circuitry unit successively
High-speed A/D converter and operational amplifier, wherein, the first intensity modulator driver element includes that RF is modulated and biased electrical
Pressure modulation, the RF modulation includes the high-speed A/D converter and operation amplifier that are connected with the first FPGA circuitry unit successively
Device, the bias voltage modulation includes the low speed digital analog converter and operation amplifier that are connected with the first FPGA circuitry unit successively
Device, the first optical attenuator driver element, the second optical attenuator driver element respectively include successively with the first FPGA circuitry list
The low speed digital analog converter and operational amplifier of unit's connection, the signal laser driver element and synchronous laser drive
Unit includes same first delay circuit, and the receiving terminal of first delay circuit is directly connected to the by two paths of data line respectively
One FPGA circuitry unit and all the way data wire connect the first FPGA circuitry unit, the first time delay electricity by level translator
Road output end connects No. four level translators, and described No. four level translator connects signal laser, synchronous laser respectively
And high-speed A/D converter, the height of the first intensity modulator driver element part of first phase modulator driver element part
Fast digital analog converter；
The receiving terminal drive circuit includes that the second FPGA circuitry unit, second phase modulator driver element, third phase are adjusted
Device driver element processed, synchroprobe driver element and four road single-photon detector driver elements, the second phase modulation
Device driver element, third phase modulator driver element include the high-speed digital-analog being connected with the second FPGA circuitry unit successively respectively
Converter and operational amplifier, the single-photon detector driver element include the second delay circuit, the second time delay electricity
The receiving terminal on road is directly connected to the second FPGA circuitry unit by two paths of data line respectively and data wire is turned by level all the way
Parallel operation connects the second FPGA circuitry unit, and the output end of second delay circuit connects No. six level translators respectively, described
No. six level translator connects four road single-photon detectors respectively and second phase modulator driver element, third phase are adjusted
Device driver element processed, four road single-photon detector connects the second FPGA circuitry by four road single-photon detector input interfaces
Unit, the synchroprobe driver element connects synchroprobe by golden finger, and the synchroprobe is sequentially connected two
Road level translator, all the way the second delay circuit, level translator and the second FPGA circuitry unit；
The drive circuit also includes being respectively used to the transmitting terminal electricity of transmitting terminal drive circuit and receiving terminal drive circuitry
Source and receiving terminal power supply.
2. the drive circuit of quantum key dispatching system is based on as claimed in claim 1, it is characterised in that first time delay
Circuit includes the delay chip being made up of 4 AD9500 modulus conversion chips.
3. the drive circuit of quantum key dispatching system is based on as claimed in claim 1, it is characterised in that second time delay
Circuit includes the delay chip being made up of 7 AD9500 modulus conversion chips.
4. the drive circuit of quantum key dispatching system is based on as claimed in claim 1, it is characterised in that the high-speed digital-analog
Converter and low speed digital analog converter are respectively adopted AD9740 chips.
5. the drive circuit of quantum key dispatching system is based on as claimed in claim 1, it is characterised in that the operation amplifier
Device uses THS3001 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710182896.3A CN106712947B (en) | 2017-03-24 | 2017-03-24 | Driving circuit based on quantum key distribution system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710182896.3A CN106712947B (en) | 2017-03-24 | 2017-03-24 | Driving circuit based on quantum key distribution system |
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| CN106712947A true CN106712947A (en) | 2017-05-24 |
| CN106712947B CN106712947B (en) | 2023-08-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505056A (en) * | 2017-08-30 | 2017-12-22 | 浙江九州量子信息技术股份有限公司 | A kind of GHz near-infrared single photon detectors avalanche signal extraction system |
| CN112350781A (en) * | 2019-08-06 | 2021-02-09 | 科大国盾量子技术股份有限公司 | Low-voltage-driven high-speed photon quantum state preparation device and method |
| CN113541807A (en) * | 2020-12-30 | 2021-10-22 | 广东国腾量子科技有限公司 | Light source coding driving system for quantum key distribution |
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| EP1848128A1 (en) * | 2006-04-20 | 2007-10-24 | NEC Corporation | Optical communication device and quantum key distribution system using the same |
| CN206585574U (en) * | 2017-03-24 | 2017-10-24 | 浙江九州量子信息技术股份有限公司 | A kind of drive circuit based on quantum key dispatching system |
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2017
- 2017-03-24 CN CN201710182896.3A patent/CN106712947B/en active Active
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| EP1848128A1 (en) * | 2006-04-20 | 2007-10-24 | NEC Corporation | Optical communication device and quantum key distribution system using the same |
| CN206585574U (en) * | 2017-03-24 | 2017-10-24 | 浙江九州量子信息技术股份有限公司 | A kind of drive circuit based on quantum key dispatching system |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505056A (en) * | 2017-08-30 | 2017-12-22 | 浙江九州量子信息技术股份有限公司 | A kind of GHz near-infrared single photon detectors avalanche signal extraction system |
| CN112350781A (en) * | 2019-08-06 | 2021-02-09 | 科大国盾量子技术股份有限公司 | Low-voltage-driven high-speed photon quantum state preparation device and method |
| CN112350781B (en) * | 2019-08-06 | 2022-02-11 | 科大国盾量子技术股份有限公司 | Low-voltage-driven high-speed photon quantum state preparation device and method |
| CN113541807A (en) * | 2020-12-30 | 2021-10-22 | 广东国腾量子科技有限公司 | Light source coding driving system for quantum key distribution |
| CN113541807B (en) * | 2020-12-30 | 2024-03-01 | 广东国腾量子科技有限公司 | Light source coding driving system for quantum key distribution |
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