CN206585574U - A kind of drive circuit based on quantum key dispatching system - Google Patents
A kind of drive circuit based on quantum key dispatching system Download PDFInfo
- Publication number
- CN206585574U CN206585574U CN201720295800.XU CN201720295800U CN206585574U CN 206585574 U CN206585574 U CN 206585574U CN 201720295800 U CN201720295800 U CN 201720295800U CN 206585574 U CN206585574 U CN 206585574U
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- driver element
- fpga circuitry
- drive circuit
- circuitry unit
- delay
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Abstract
A kind of drive circuit based on quantum key dispatching system, the signal laser driver element and synchronous laser driver element that transmitting terminal drive circuit includes include same first delay circuit, and the receiving terminal of first delay circuit is directly connected to the first FPGA circuitry unit by two paths of data line respectively and data wire connects the first FPGA circuitry unit by level translator all the way；The single-photon detector driver element of receiving terminal driving circuit section includes the second delay circuit, and the receiving terminal of second delay circuit is directly connected to the second FPGA circuitry unit by two paths of data line respectively and data wire connects the second FPGA circuitry unit by level translator all the way.Compared with prior art, the utility model adjusts the drive signal brought by circuit transmission and component by delay chip and is delayed, so as to reach the signal ideal synchronisation of requirement, it is ensured that the efficient production rate of quantum key.
Description
Technical field
The utility model is related to safety communication technology field, more particularly to a kind of driving based on quantum key dispatching system
Circuit.
Background technology
Drive circuit adjustable delay precision is not high in traditional secrete key distribution system or adjustable extent is very narrow, in addition, driving electricity
Road can not adjust delay precision and scope as the case may be, be particularly easy to cause the asynchronous response of each drived unit, no
Beneficial to the synchronization alignment of multiple signals so that synchronous unstable, thus cause key dislocation in key generation process, lacking of losing
Fall into.
Utility model content
The utility model purpose is to provide a kind of drive circuit based on quantum key dispatching system, to solve existing skill
The asynchronous response of the drived unit of each in key dispatching system in art, is unfavorable for the synchronous alignment of multiple signals so that synchronous
It is unstable, so as to cause key dislocation, the technical bug lost in key generation process.
What the technical solution of the utility model was realized in：
A kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit and receiving terminal driving electricity
Road,
The transmitting terminal drive circuit includes the first FPGA circuitry unit, first phase modulator driver element, the last the first
Spend modulator driver element, the first optical attenuator driver element, the second optical attenuator driver element, signal laser driver element
And synchronous laser driver element, the first phase modulator driver element include successively with the first FPGA circuitry unit
The high-speed A/D converter and operational amplifier of connection, wherein, the first intensity modulator driver element include RF modulate and
Bias voltage is modulated, and the RF modulation includes high-speed A/D converter and the computing being connected successively with the first FPGA circuitry unit
Amplifier, the bias voltage modulation includes low speed digital analog converter and the computing being connected successively with the first FPGA circuitry unit
Amplifier, the first optical attenuator driver element, the second optical attenuator driver element include electric with the first FPGA successively respectively
The low speed digital analog converter and operational amplifier of road unit connection, the signal laser driver element and synchronous laser
Driver element includes same first delay circuit, and the receiving terminal of first delay circuit is directly connected by two paths of data line respectively
Connect the first FPGA circuitry unit and data wire connects the first FPGA circuitry unit by level translator all the way, described first prolongs
When circuit output end connect No. four level translators, described No. four level translator connects signal laser, synchronous swashed respectively
Light device and the high-speed A/D converter of first phase modulator driver element part, the first intensity modulator driver element part
High-speed A/D converter；
The receiving terminal drive circuit includes the second FPGA circuitry unit, second phase modulator driver element, third phase
Position modulator driver element, synchroprobe driver element and four road single-photon detector driver elements, the second phase
Modulator driver element, third phase modulator driver element include the high speed being connected successively with the second FPGA circuitry unit respectively
Digital analog converter and operational amplifier, the single-photon detector driver element include the second delay circuit, and described second prolongs
When circuit receiving terminal the second FPGA circuitry unit is directly connected to by two paths of data line respectively and data wire passes through electricity all the way
Flat turn parallel operation connects the second FPGA circuitry unit, and the output end of second delay circuit connects No. six level translators respectively,
Described No. six level translator connects four road single-photon detectors and second phase modulator driver element, third phase respectively
Position modulator driver element, four road single-photon detector connects the 2nd FPGA by four road single-photon detector input interfaces
Circuit unit, the synchroprobe driver element connects synchroprobe by golden finger, and the synchroprobe connects successively
Connect two-way level translator, all the way the second delay circuit, level translator and the second FPGA circuitry unit；
The drive circuit also includes the transmitting for being respectively used to transmitting terminal drive circuit and receiving terminal drive circuitry
Hold power supply and receiving terminal power supply.
Preferably, first delay circuit includes the delay chip being made up of 4 AD9500 modulus conversion chips.
Preferably, second delay circuit includes the delay chip being made up of 7 AD9500 modulus conversion chips.
Preferably, AD9740 chips are respectively adopted in high-speed A/D converter and the low speed digital analog converter.
Preferably, the operational amplifier uses THS3001 chips.
Compared with prior art, the utility model has following beneficial effect：
Drive circuit of the present utility model based on quantum key dispatching system, by delay chip adjustment because of circuit transmission
And the drive signal transmission delay that component is brought, so as to reach the signal ideal synchronisation of requirement, it is ensured that quantum key is high
The production rate of effect.In addition, high-speed DAC and wide output voltage range, the high speed amplifier of high pressure Slew Rate coordinate to rising edge, declined
Edge, setup time, the realization of Width funtion output signal.
Brief description of the drawings
Fig. 1 is transmitting terminal drive circuit figure of the utility model based on quantum key dispatching system；
Fig. 2 is receiving terminal drive circuit figure of the utility model based on quantum key dispatching system.
In figure：Transmitting terminal drive circuit 1, the first FPGA circuitry unit 101, first phase modulator driver element 102, the
One intensity modulator driver element 103, the first optical attenuator driver element 104, the second optical attenuator driver element 105, signal
Laser drive unit 106, synchronous laser driver element 107, the first delay circuit 108, receiving terminal drive circuit 2, second
FPGA circuitry unit 201, second phase modulator driver element 202, third phase modulator driver element 203, synchronizing detection
Device driver element 204, single-photon detector driver element 205, the second delay circuit 206, level translator 3, single photon detection
Device 4, single-photon detector input interface 5, synchroprobe 6.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the utility model is clearly and completely described.
As shown in figure 1, a kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit 1 and
Receiving terminal drive circuit 2, the transmitting terminal drive circuit 1 includes the first FPGA circuitry unit 101, first phase modulator and driven
Unit 102, the first intensity modulator driver element 103, the first optical attenuator driver element 104, the driving of the second optical attenuator are single
Member 105, signal laser driver element 106 and synchronous laser driver element 107, the first phase modulator driving are single
Member 102 includes the high-speed A/D converter and operational amplifier being connected successively with the first FPGA circuitry unit 101, wherein, the
One intensity modulator driver element 103 includes RF and modulated and bias voltage modulation, and RF modulation is included successively with first
High-speed A/D converter and operational amplifier that FPGA circuitry unit 101 is connected, bias voltage modulation include successively with
The low speed digital analog converter and operational amplifier of first FPGA circuitry unit 101 connection, the first optical attenuator driving are single
First 104, second optical attenuator driver element 105 includes the low speed digital-to-analogue being connected successively with the first FPGA circuitry unit 101 respectively
Converter and operational amplifier, the signal laser driver element 106 and synchronous laser driver element 107 include same
One first delay circuit 108, the receiving terminal of first delay circuit 108 is directly connected to first by two paths of data line respectively
FPGA circuitry unit 101 and all the way data wire connect the first FPGA circuitry unit 101, described first by level translator 3
The output end of delay circuit 108 connects No. four level translators 3, and described No. four level translator 3 connects signal laser respectively
106th, the high-speed A/D converter of synchronous laser 107 and the part of first phase modulator driver element 102, the first intensity are adjusted
The high-speed A/D converter of the part of device driver element 103 processed；
Driven as shown in Fig. 2 the receiving terminal drive circuit 2 includes the second FPGA circuitry unit 201, second phase modulator
Moving cell 202, third phase modulator driver element 203, the road single photon detection of synchroprobe driver element 204 and four
Device driver element 205, the second phase modulator driver element 201, third phase modulator driver element 203 include respectively
The high-speed A/D converter and operational amplifier being connected successively with the second FPGA circuitry unit 201, the single-photon detector
Driver element 205 includes the second delay circuit 206, and the receiving terminal of second delay circuit 206 passes through two paths of data line respectively
It is directly connected to the second FPGA circuitry unit 201 and data wire connects the second FPGA circuitry unit by level translator 3 all the way
201, the output end of second delay circuit 206 connects No. six level translators 3, described No. six level translator 3 respectively
Four road single-photon detectors 4 and second phase modulator driver element 201, third phase modulator driver element are connected respectively
203, four road single-photon detector 4 connects the second FPGA circuitry unit by four road single-photon detector input interfaces 5
201, the synchroprobe driver element 204 connects synchroprobe 6 by golden finger, and the synchroprobe 6 connects successively
Connect two-way level translator 3, all the way the second delay circuit 206, the FPGA circuitry unit 201 of level translator 3 and second；It is described
Drive circuit also include being respectively used to the transmitting terminal power supply 7 that transmitting terminal drive circuit 1 and receiving terminal drive circuit 2 power and
Receiving terminal power supply 8.First delay circuit 108 includes the delay chip being made up of 4 AD9500 modulus conversion chips.It is described
Second delay circuit 206 includes the delay chip being made up of 7 AD9500 modulus conversion chips.The high-speed A/D converter with
And AD9740 chips are respectively adopted in low speed digital analog converter.The operational amplifier uses THS3001 chips.
The course of work of drive circuit each unit of the present utility model is as follows：
1) signal laser drives：
Receive the start pulse signal that the first FPGA circuitry unit 101 is provided, the start pulse signal enters programmable the
(delay carries out compiling by fpga to delay circuit for sometime delay in the range of one delay circuit 108 progress, 0~25ns
Journey delay time is set), recently enter signal laser and lighted to trigger laser.
2) synchronous laser drives：
3.3V power supplys are done to synchronous laser to power and relevant pins setting, synchronous laser is in emission state,
Then when receiving the start pulse signal that the first FPGA circuitry unit 101 is provided, the start pulse signal enters programmable the
(delay carries out compiling by fpga to delay circuit for sometime delay in the range of one delay circuit 108 progress, 0~25ns
Journey delay time is set), synchronous laser triggering laser is transferred to after being delayed through programmable delay chip and sends corresponding light
Pulse.
3) synchroprobe drives：
3.3V power supplys are done to synchroprobe to power and relevant pins setting, synchroprobe is in reception state,
Synchroprobe receives synchronous laser and transmits the synchronization pulse come in and send into the 2nd FPGA by interface level conversion
Circuit unit 201 is used as receiving terminal synchronizing datum signal.
4) intensity modulator drives：
A, RF modulation driving：First FPGA circuitry unit 101 output 10bit data change into difference through high-speed A/D converter
Divide current signal output, the direct current signal that high-speed A/D converter is exported then is done into I-V conversions, eventually through operational amplifier
The RF interfaces that amplification reaches -6V~+6V high-quality signal output driving intensity modulator are filtered to signal.This signal pair
The parameter requests such as rising edge, trailing edge, setup time, the slew rate of amplifier are：When rise and fall are set up along within time 2.5ns
Between 15ns；
B, bias voltage modulation driving：Meanwhile, intensity modulator is used for modulating bias voltage comprising low speed signal all the way, adopts
The effect of adjustable bias voltage is realized with the framework of high-speed A/D converter concatenation operation amplifier.
5) phase-modulation circuit drives：
It is defeated that first FPGA circuitry unit 101 output 10bit data change into differential current signal through high-speed A/D converter
Go out, the direct current signal that high-speed A/D converter is exported then is done into I-V conversions, signal filtered eventually through operational amplifier
Ripple amplifies the high-quality signal output driving phase-modulator for reaching -6V~+6V.Rising of this drive signal to operational amplifier
The parameter requests such as edge, trailing edge, setup time, slew rate are：Rise and fall are along setup time 15ns within time 2.5ns.
6) optical attenuator drives：
It is defeated that first FPGA circuitry unit 101 output 10bit data change into differential current signal through low speed digital analog converter
Go out, the direct current signal for then exporting low speed digital analog converter does I-V conversions, and signal is filtered eventually through operational amplifier
Ripple amplification reaches that -6V~+6V the first optical attenuator of high-quality signal output driving driver element 104 and the second optical attenuator drives
Moving cell 105.
7) single-photon detector drives：
Receive the start pulse signal that the second FPGA circuitry unit 201 is provided, the start pulse signal enters programmable the
(delay passes through 201 pairs of the second FPGA circuitry unit for the sometime delay that two delay circuits 206 carry out in the range of 0~25ns
Second delay circuit 206 carries out programmable delay set of time), single-photon detector 4 is recently entered to trigger detection process.
Drive circuit of the present utility model based on quantum key dispatching system, by delay chip adjustment because of circuit transmission
And the drive signal transmission delay that component is brought, so as to reach the signal ideal synchronisation of requirement, it is ensured that quantum key is high
The production rate of effect.In addition, the high speed amplifier of the high-speed DAC and wide output voltage range, high pressure Slew Rate in system coordinates to rising
Edge, trailing edge, setup time, the realization of Width funtion output signal.
Claims (5)
1. a kind of drive circuit based on quantum key dispatching system, including transmitting terminal drive circuit and receiving terminal driving electricity
Road, it is characterised in that
The transmitting terminal drive circuit includes the first FPGA circuitry unit, first phase modulator driver element, the first intensity and adjusted
Device driver element processed, the first optical attenuator driver element, the second optical attenuator driver element, signal laser driver element and
Synchronous laser driver element, the first phase modulator driver element includes what is be connected successively with the first FPGA circuitry unit
High-speed A/D converter and operational amplifier, wherein, the first intensity modulator driver element includes RF and modulated and biased electrical
Pressure modulation, the RF modulation includes the high-speed A/D converter and operation amplifier being connected successively with the first FPGA circuitry unit
Device, the bias voltage modulation includes the low speed digital analog converter and operation amplifier being connected successively with the first FPGA circuitry unit
Device, the first optical attenuator driver element, the second optical attenuator driver element respectively include successively with the first FPGA circuitry list
The low speed digital analog converter and operational amplifier of member connection, the signal laser driver element and synchronous laser driving
Unit includes same first delay circuit, and the receiving terminal of first delay circuit is directly connected to the by two paths of data line respectively
One FPGA circuitry unit and all the way data wire connect the first FPGA circuitry unit, the first delay electricity by level translator
Road output end connects No. four level translators, and described No. four level translator connects signal laser, synchronous laser respectively
And high-speed A/D converter, the height of the first intensity modulator driver element part of first phase modulator driver element part
Fast digital analog converter；
The receiving terminal drive circuit includes the second FPGA circuitry unit, second phase modulator driver element, third phase and adjusted
Device driver element processed, synchroprobe driver element and four road single-photon detector driver elements, the second phase modulation
Device driver element, third phase modulator driver element include the high-speed digital-analog being connected successively with the second FPGA circuitry unit respectively
Converter and operational amplifier, the single-photon detector driver element include the second delay circuit, the second delay electricity
The receiving terminal on road is directly connected to the second FPGA circuitry unit by two paths of data line respectively and data wire is turned by level all the way
Parallel operation connects the second FPGA circuitry unit, and the output end of second delay circuit connects No. six level translators respectively, described
No. six level translator connects four road single-photon detectors respectively and second phase modulator driver element, third phase are adjusted
Device driver element processed, four road single-photon detector connects the second FPGA circuitry by four road single-photon detector input interfaces
Unit, the synchroprobe driver element connects synchroprobe by golden finger, and the synchroprobe is sequentially connected two
Road level translator, all the way the second delay circuit, level translator and the second FPGA circuitry unit；
The drive circuit also includes being respectively used to transmitting terminal drive circuit and the transmitting terminal electricity of receiving terminal drive circuitry
Source and receiving terminal power supply.
2. the drive circuit as claimed in claim 1 based on quantum key dispatching system, it is characterised in that first delay
Circuit includes the delay chip being made up of 4 AD9500 modulus conversion chips.
3. the drive circuit as claimed in claim 1 based on quantum key dispatching system, it is characterised in that second delay
Circuit includes the delay chip being made up of 7 AD9500 modulus conversion chips.
4. the drive circuit as claimed in claim 1 based on quantum key dispatching system, it is characterised in that the high-speed digital-analog
AD9740 chips are respectively adopted in converter and low speed digital analog converter.
5. the drive circuit as claimed in claim 1 based on quantum key dispatching system, it is characterised in that the operation amplifier
Device uses THS3001 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720295800.XU CN206585574U (en) | 2017-03-24 | 2017-03-24 | A kind of drive circuit based on quantum key dispatching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720295800.XU CN206585574U (en) | 2017-03-24 | 2017-03-24 | A kind of drive circuit based on quantum key dispatching system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206585574U true CN206585574U (en) | 2017-10-24 |
Family
ID=60114917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720295800.XU Withdrawn - After Issue CN206585574U (en) | 2017-03-24 | 2017-03-24 | A kind of drive circuit based on quantum key dispatching system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206585574U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712947A (en) * | 2017-03-24 | 2017-05-24 | 浙江九州量子信息技术股份有限公司 | Driving circuit based on quantum key distribution system |
-
2017
- 2017-03-24 CN CN201720295800.XU patent/CN206585574U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712947A (en) * | 2017-03-24 | 2017-05-24 | 浙江九州量子信息技术股份有限公司 | Driving circuit based on quantum key distribution system |
| CN106712947B (en) * | 2017-03-24 | 2023-08-18 | 浙江九州量子信息技术股份有限公司 | Driving circuit based on quantum key distribution system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20171024 Effective date of abandoning: 20230818 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20171024 Effective date of abandoning: 20230818 |