CN106712516A - Two-stage voltage stabilization regulating circuit and voltage stabilization method and design method thereof - Google Patents
Two-stage voltage stabilization regulating circuit and voltage stabilization method and design method thereof Download PDFInfo
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- CN106712516A CN106712516A CN201710086592.7A CN201710086592A CN106712516A CN 106712516 A CN106712516 A CN 106712516A CN 201710086592 A CN201710086592 A CN 201710086592A CN 106712516 A CN106712516 A CN 106712516A
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- 238000005070 sampling Methods 0.000 claims abstract description 67
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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Abstract
The invention discloses a two-stage voltage stabilization regulating circuit and a voltage stabilization method and a design method thereof. The two-stage voltage stabilization regulating circuit comprises a pre-stage preliminary voltage stabilization circuit and a secondary LDO circuit. The pre-stage preliminary voltage stabilization circuit comprises a switch circuit and a switch control circuit. The voltage input end of the switch circuit is connected with a pre-stage input voltage sampling circuit. The output end of the switch circuit is connected with a pre-stage output filtering and energy storage circuit. The input end of the pre-stage output filtering and energy storage circuit is connected with a pre-stage output voltage sampling circuit. The secondary LDO circuit comprises a voltage regulating circuit, a secondary output voltage sampling circuit and an error amplification circuit which are connected in turn. The voltage stabilization method comprises the steps that firstly, the pre-stage preliminary voltage stabilization circuit performs preliminary voltage stabilization on half sine wave voltage outputted by commercial power through a rectification circuit by rectification; and secondly, the secondary LDO circuit performs further voltage stabilization on the voltage outputted by the pre-stage preliminary voltage stabilization circuit. The two-stage voltage stabilization regulating circuit is simple in structure, low in power consumption, low in cost, low in ripple, high in stability and high in reliability.
Description
Technical field
The invention belongs to power technique fields, and in particular to a kind of steady voltage regulator circuit of two-stage and its method for stabilizing voltage and design
Method.
Background technology
In the message area of high speed development, the status that power technology is occupied is more and more important, either advanced calculating
Machine, wireless telecommunications system, or automobile electronics, all embody the superiority of power technology, and it has turned into current integrated electricity
A focus in the industry development of road.Nowadays, the electronic product based on power technology design has spread to people's work, life
Various aspects living, its ratio of performance to price is more and more high, and function is more and more strong, and market competition is more and more fierce.
Electronic equipment of today, power supply has turned into an indispensable part, with the raising of power supply efficiency optimization, power supply
Administrative skill has had been extricated from often being incorporated into mode within application processor in the past, and as important technology
Research and development, gradually generate all kinds of power supply products.Traditional power supply product can not meet device requirement, power supply product just towards
High efficiency, miniaturization, the direction of high stability are developed.
With the arrival in electronic information epoch, new technology, new technology constantly advance the development of integrated circuit, especially VLSI
Technology, it drastically increases the application in electronic product such as analog circuit, digital circuit, Digital Analog Hybrid Circuits, not only drops
The low manufacturing cost of electronic product, and promote the popularization of electronics applications.Single-chip microcomputer is because of high, the volume with reliability
It is small, the advantages of control function is strong, it is widely applied in the control system in the fields such as Industry Control, household electrical appliances, communication equipment.
To the power supply that single-chip microcomputer is powered, the system design scheme for generally using has two kinds：The first scheme is using isolation
Switch converters.Voltage range required for civil power to be transformed to electronic circuit using Industrial Frequency Transformer, then by rectification circuit
Alternating voltage after transformer is converted is changed into unidirectional pulsating dc voltage, straight to the pulsation that rectification is exported using filter circuit
Stream is smoothed, and obtains a DC voltage containing ripple component very little, realizes that AC-DC is changed, and becomes eventually through DC-DC
Parallel operation powering load；Another scheme is to use switch power supply topological structure.This scheme first completes AC-DC conversions, hands over
Stream electricity is transformed into the DC voltage with certain voltage ripple by rectification circuit, recycles filter circuit to filter ripple, finally
By switch converters powering load.Industrial Frequency Transformer volume is big, high cost；And switch converters peripheral cell is more, make
It is big into power volume.Therefore, using above mains-supplied scheme, power supply product volume is often larger.
D.C. regulated power supply is broadly divided into Switching Power Supply and linear power supply according to the working method of power tube.Switching mode is steady
Depressor is a kind of discrete system, and its internal power tube is operated in HF switch state, and conducting resistance is small, when flowing through larger current
When, the power very little on power tube is consumed, power-efficient is very high, can reach more than 85%, and sometimes referred to as it is " energy-efficient
Type power supply ", the main product as voltage-stablizer.But switching noise is its fatal defects greatly, be greatly limit low
Noise, the simulation of low ripple and the application of RF application.And linear voltage regulator contrast, it is continuous system, efficiency is low,
It is its shortcoming less than input that power tube caloric value is big, output is total, but it has good line regulation, load regulation, height
PSRR, low noise and other advantages, can just make up the deficiency of Switching regulator.Additionally, linear voltage regulator is because having
Low ripple voltage and be widely used in in noise, the exigent electronic equipment of ripple.
Compared with other power supplys, linear stabilized power supply has the advantages that following some protrusions：When output current is smaller, line
The cost of property voltage-stablizer is relatively low；The encapsulation of linear voltage regulator is especially suitable for applying in mancarried electronic aid, such as radio telephone, the palm
Upper computer etc.；Peripheral circuit is simple, it is only necessary to which the electric capacity of 2-3 very little is that may make up whole power source design；Ultralow output electricity
Pressure noise, is highly suitable for the power supply circuit to the voicefrequency circuit of noise-sensitive；Because of big electricity when being turned off without switch conduction simultaneously
The electromagnetic interference (EMI) that rheology is triggered, institute is in order to design.Just because of this, linear voltage regulator is widely used in hand
In the portable electric appts such as machine.For example, mobile phone may contain up to 10 LDO (low dropout regulator,
Low pressure difference linear voltage regulator) as internal each numeral and the power supply of analog module, thus LDO is in great demand.
Abroad, the technology of LDO low pressure difference linear voltage regulators is quite ripe.Such as some well-known state's outer semiconductors
Manufacturer such as TI, Infineon's semiconductor, U.S. letter, international rectifier (IR) and Intersil etc. have a series of than more complete LDO
Product.Using triode NPN, PNP as the market also progressively atrophy of the LDO low pressure difference linear voltage regulators of power adjustment pipe；Take and
Instead of be using PMOS FETs as power adjustment pipe LDO low pressure difference linear voltage regulators gradually captured market.And it is right
For this two classes linear power supply chip, they main difference is that the difference of voltage drop Vdropout, voltage drop is done herein
Description below, LDO linear voltage regulator chip output voltages gradually increase with the increase of input voltage, when input voltage increase
Maintain essentially in an invariable value to output voltage, this invariable output voltage values Vout with obtain the value institute
The difference of corresponding minimum input voltage value Vin is just voltage drop Vdropout.Under normal circumstances, we to design a performance good
LDO chips, wherein its internal electricity when a critically important index request for weighing its performance is just so that system worked well
Power attenuation on road is as few as possible, and the efficiency of chip is higher therewith.Using NPN, PNP as the linear voltage stabilization electricity of power adjustment pipe
Pressure drop ratio needed for source is larger, and operating efficiency is than relatively low.And using PMOS FETs as the LDO linear voltage stabilizations of adjustment power tube
Utensil has low voltage drop Vdropout and relatively low power consumption, thus to p-type field-effect product body pipe as power adjustment pipe
Using in occupation of very big market, and the linear voltage regulator chip that some other such as BCD techniques are realized is also in development.With
The fast development of LDO linear voltage regulator chips, to its performance requirement also more and more higher, at present for LDO linear voltage regulators
The market demand of chip and its development trend can be summarized as it is following some：(1) reduces cost and diminution volume；(2) drop
Low power supply power consumption；(3) diversified output voltage is provided；(4) design cycle is shortened.
Low pressure difference linear voltage regulator (LDO) is because with small volume, PSRR is high, low in energy consumption, noise is low and applies
The features such as circuit is simple, and it is subject to the common concern of people.Further, since LDO also has preferable transient response performance, make it
Occupy critical role in fields such as portable, industrialization, automobile industries, such as in PDA, MP3 player, radio telephone, DDR etc.
It is widely used in electronic equipment.Therefore, the study hotspot for being designed to current power technical field of LDO, with important reason
By meaning and actual application value.Especially as transformerless integrated regulator can save occupancy system face relative to Switching Power Supply
The larger inductance class component of product, peripheral circuit is simple, additionally, integrated regulator also has small volume, low cost, ripple small and steady
Qualitative high the advantages of.
Because traditional integrated regulator needs the larger Industrial Frequency Transformer of circumscribed volume in practical application, because of inductance and
Transformer is not easy of integration in power supply chip, and chip occupying area is larger, causes integrated regulator application to be affected；Traditional
Linear voltage regulator all realizes that especially adjustment is managed, and bipolar device belongs to current control device using bipolar device mostly,
In driving load, it is necessary to big base stage control electric current, result in circuit power consumption increase；And, current LDO circuit is also present
Efficiency is low, and the voltage difference of input and output can not be too big, if pressure drop is too big, consumption energy on LDO is too big, and inefficient grade lacks
Point.
The content of the invention
The technical problems to be solved by the invention are for above-mentioned deficiency of the prior art, there is provided a kind of circuit structure
Simply, low in energy consumption, low cost, ripple are small, stability is high, reliability is high, practical, using effect is good, with preferably pushing away
The steady voltage regulator circuit of two-stage of wide application value.
In order to solve the above technical problems, the technical solution adopted by the present invention is：A kind of steady voltage regulator circuit of two-stage, its feature
It is：Including the pre- mu balanced circuit of prime and secondary LDO circuit, the pre- mu balanced circuit of prime includes that on-off circuit and switch are controlled
Circuit, the voltage input end of the on-off circuit is the input VIN of the steady voltage regulator circuit of the two-stage, the on-off circuit
Control source is terminated with prime input voltage sample circuit, and the output of the on-off circuit is terminated with prime output filtering and energy storage
Circuit, the prime output filtering and the input of accumulator are terminated with prime output voltage sampling circuit, the prime input
The output end of voltage sampling circuit and the output end of prime output voltage sampling circuit connect with the input of ON-OFF control circuit
Connect, the switch controlling signal input of the on-off circuit is connected with the output end of ON-OFF control circuit；The secondary LDO circuit
Including the voltage-regulating circuit, secondary output voltage sample circuit and the error amplifying circuit that are sequentially connected, the voltage adjustment electricity
The voltage input end on road is connected with the output end of on-off circuit, and control signal input and the error of the voltage-regulating circuit are put
The output end connection of big circuit, the output end of the voltage-regulating circuit is the output end of the steady voltage regulator circuit of the two-stage
VOUT。
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The on-off circuit includes NMOS tube Q3 and resistance
R9, the drain electrode of the NMOS tube Q3 is connected with one end of resistance R9 and is the voltage input end of on-off circuit, the NMOS tube Q3
Grid be connected with the other end of resistance R9 and be the switch controlling signal input of on-off circuit, the source electrode of the NMOS tube Q3
It is the output end of on-off circuit.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The model IRF431 of the NMOS tube Q3.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The ON-OFF control circuit includes comparator U1, ratio
Compared with device U2, two input nand gate U3, reference voltage source V1, reference voltage source V2 and NMOS tube Q2, the same phase of the comparator U1
Input is connected with the cathode output end of reference voltage source V1, the cathode output end ground connection of the reference voltage source V1, the ratio
Inverting input compared with device U1 for ON-OFF control circuit first input end and with the output end of prime input voltage sample circuit
Connection；The in-phase input end of the comparator U2 is connected with the cathode output end of reference voltage source V2, the reference voltage source V2
Cathode output end ground connection, the inverting input of the comparator U2 is the second input of ON-OFF control circuit and defeated with prime
Go out the output end connection of voltage sampling circuit；Two inputs of the two input nand gates U3 respectively with the output of comparator U1
The output end of end and comparator U2 is connected, and the output end of the two input nand gates U3 is connected with the grid of NMOS tube Q2, described
The drain electrode of NMOS tube Q2 is the output end of ON-OFF control circuit, the source ground of the NMOS tube Q2.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The model of the comparator U1 and comparator U2 is equal
It is LM393, the model IRF720A of the model CD4011, the NMOS tube Q2 of the two input nand gates U3, the reference
The model of voltage source V1 and reference voltage source V2 is LM4140.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The prime input voltage sample circuit includes string
The resistance R1 and resistance R2 of connection, resistance R1 and one end of resistance R2 after series connection are connected with the voltage input end of on-off circuit, string
The other end ground connection of resistance R1 and resistance R2 after connection, the connection end of the resistance R1 and resistance R2 is the sampling of prime input voltage
The output end of circuit；The prime output voltage sampling circuit includes the resistance R6 and resistance R7 of series connection, the resistance R6 after series connection
The input for exporting filtering and accumulator with prime with one end of resistance R7 is connected, and the resistance R6's and resistance R7 after series connection is another
One end is grounded, and the connection end of the resistance R6 and resistance R7 is the output end of prime output voltage sampling circuit；The prime is defeated
Go out one end of filtering and accumulator including electric capacity C1, the electric capacity C1 for prime export the input of filtering and accumulator and
It is connected with the output end of on-off circuit, the other end ground connection of the electric capacity C1.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The voltage-regulating circuit includes PMOS Q1, institute
The drain electrode for stating PMOS Q1 is the voltage input end of voltage-regulating circuit, and the grid of the PMOS Q1 is voltage-regulating circuit
Control signal input, the drain electrode of the PMOS Q1 is the output end of voltage-regulating circuit；The secondary output voltage sampling
Circuit includes the resistance R4 and resistance R5 of series connection, one end of resistance R4 and resistance R5 after series connection and the output of voltage-regulating circuit
End connection, the other end ground connection of resistance R6 and resistance R7 after series connection, the connection end of the resistance R4 and resistance R5 is secondary defeated
Go out the output end of voltage sampling circuit；The error amplifying circuit includes error amplifier X1 and reference voltage source V3, the mistake
The in-phase input end of difference amplifier X1 is connected with the output end of secondary output voltage sample circuit, and the error amplifier X1's is anti-
Phase input is connected with the cathode output end of reference voltage source V3, the cathode output end ground connection of the reference voltage source V3, described
The output end of error amplifier X1 is the output end of error amplifying circuit and connects with the control signal input of voltage-regulating circuit
Connect.
A kind of above-mentioned steady voltage regulator circuit of two-stage, it is characterised in that：The model IRF720A of the PMOS Q1, institute
State the model LM358, the model LM385 of the reference voltage source V3 of error amplifier X1.
Present invention also offers a kind of method and step it is simple, reasonable in design, realize the steady voltage regulator circuit of convenient two-stage
Method for stabilizing voltage, it is characterised in that the method is comprised the following steps：
The pre- mu balanced circuit of step A, prime is exported by rectifier circuit rectifies to civil power and carried out to its half sine wave voltage
Pre- voltage stabilizing：The half-sine wave ascent stage of Output Voltage in Rectified Circuits, voltage is started from scratch and gradually increase, when the voltage of on-off circuit
Input terminal voltage is increased to when can turn on on-off circuit, and on-off circuit conducting, prime output filtering and accumulator start
Energy storage；Meanwhile, prime input voltage sample circuit carries out real-time detection to the control source terminal voltage of on-off circuit and will detect
The voltage output for arriving to ON-OFF control circuit, the voltage that ON-OFF control circuit detects prime input voltage sample circuit with it is pre-
If NMOS tube Q3 first shut-off threshold voltage be compared, the control source terminal voltage with on-off circuit further increases
Greatly, when the voltage that prime input voltage sample circuit is detected turns off threshold voltage more than the first of default NMOS tube Q3,
ON-OFF control circuit controlling switch circuit is turned off, and prime output filtering and accumulator discharge, and output voltage gives secondary LDO electricity
Road；Output Voltage in Rectified Circuits enters half-sine wave descending branch after increasing to peak value, and voltage is gradually reduced since peak value, preceding
When the voltage that level input voltage sample circuit is detected turns off threshold voltage more than the first of default NMOS tube Q3, on-off circuit
Have been at off state, meanwhile, prime output voltage sampling circuit to prime export filtering and accumulator enter out end electricity
Pressure carries out real-time detection and the voltage output that will detect is to ON-OFF control circuit, and ON-OFF control circuit adopts prime output voltage
Sample electric circuit inspection to the second shut-off threshold voltage of voltage and default NMOS tube Q3 be compared；With the electricity of on-off circuit
Pressure input terminal voltage further reduces, when the voltage that prime input voltage sample circuit is detected is less than default NMOS tube Q3's
First shut-off threshold voltage, and second pass of the voltage more than default NMOS tube Q3 that prime output voltage sampling circuit is detected
During disconnected threshold voltage, on-off circuit is still off, and prime output filtering and accumulator continue to discharge, and output voltage is to secondary
LDO circuit；Control source terminal voltage with on-off circuit further reduces, when prime output voltage sampling circuit is detected
When voltage turns off threshold voltage less than the second of default NMOS tube Q3, ON-OFF control circuit controlling switch circuit turn-on, prime
Output filtering and accumulator start again at energy storage, while output voltage gives secondary LDO circuit；When the control source of on-off circuit
Terminal voltage is reduced to when being insufficient to allow on-off circuit to turn on, and on-off circuit shut-off, prime output filtering and accumulator discharge, defeated
Go out voltage to secondary LDO circuit, until the half-sine wave ascent stage of the next cycle of Output Voltage in Rectified Circuits；Wherein, institute
The the first shut-off threshold voltage for stating NMOS tube Q3 is ON-OFF control circuit according to prime input voltage sampling circuit samples voltage control
The shut-off threshold voltage of NMOS tube Q3 shut-offs processed；The NMOS tube Q3 second shut-off threshold voltage be ON-OFF control circuit according to
The shut-off threshold voltage of prime output voltage sampling circuit sampled voltage control NMOS tube Q3 shut-offs；
Step B, secondary LDO circuit are exported to the pre- mu balanced circuit of prime and carry out further voltage stabilizing to its voltage：Work as prime
The voltage of pre- mu balanced circuit output has the trend of reduction, secondary when the voltage for causing secondary LDO circuit to export has the trend of reduction
The voltage that output voltage sampling circuit is detected reduces, and the voltage of error amplifying circuit output also reduces, voltage-regulating circuit inspection
When the voltage for measuring error amplifying circuit output reduces, the electric current increase of voltage-regulating circuit is flowed through in adjustment, makes secondary LDO circuit
The voltage increase of output, it is ensured that secondary LDO circuit output voltage stabilization；When the voltage of the pre- mu balanced circuit output of prime has increase
Trend, when the voltage for causing secondary LDO circuit to export has the trend of increase, the voltage that secondary output voltage sample circuit is detected
Increase, the voltage of error amplifying circuit output also increases, and the voltage that voltage-regulating circuit detects error amplifying circuit output increases
When big, the electric current that voltage-regulating circuit is flowed through in adjustment reduces, and reduces the voltage of secondary LDO circuit output, it is ensured that secondary LDO electricity
Road output voltage stabilization.
The invention also discloses a kind of method and step it is simple, reasonable in design, realize it is convenient, can design it is reliable and stable
The method for designing of the steady voltage regulator circuit of two-stage of the steady voltage regulator circuit of two-stage, it is characterised in that the method is comprised the following steps：
The NMOS tube Q3 and resistance R9 of step one, the suitable parameters of selection composition on-off circuit, its detailed process are as follows：
Step 101, NMOS tube Q3 is chosen, detailed process is：
Step 1011, according to formula VQ3,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q3 is subjected toQ3,max, its
In, Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
Step 1012, selection pressure voltage are more than VQ3,maxNMOS tube model as NMOS tube Q3；
Step 102, the resistance that resistance R9 is chosen according to 1k Ω ＜ R9 ＜ 100k Ω；
Step 2, the comparator U1 of suitable parameters of selection composition on-off circuit, comparator U2, two input nand gate U3,
Reference voltage source V1, reference voltage source V2 and NMOS tube Q2, its detailed process are as follows：
Step 201, selection single supply are powered and supply voltage is the comparator model of 5V and propagation delay time no more than 250ns
As comparator U1 and comparator U2；
Step 202, two input nand gates of selection disposable type are used as two input nand gate U3；
Step 203, NMOS tube Q2 is chosen, detailed process is：
Step 2031, according to formula VQ2,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q2 is subjected toQ2,max, its
In, Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
Step 2032, selection pressure voltage are more than VQ2,maxNMOS tube model as NMOS tube Q2；
Step 204, selection can export the reference voltage source model of 2V reference voltages source V1 as the reference voltage；
Step 205, selection can export the reference voltage source model of 2V reference voltages source V2 as the reference voltage；
Step 3, according to formulaChoose composition prime input voltage sample circuit resistance R1 and
The resistance of resistance R2；Wherein, V1 is the output voltage of reference voltage source V1, VQ3It is ON-OFF control circuit according to prime input voltage
The shut-off threshold voltage of sampling circuit samples voltage control NMOS tube Q3 shut-offs；
Step 4, according to formulaChoose composition prime output voltage sampling circuit resistance R6 and
The resistance of resistance R7；Wherein, V2 is the output voltage of reference voltage source V2, VC1It is ON-OFF control circuit according to prime output voltage
The shut-off threshold voltage of sampling circuit samples voltage control NMOS tube Q3 shut-offs；
Step 5, according to formulaChoose the appearance of the electric capacity C1 for constituting prime output filtering and accumulator
Value；Wherein, IloadIt is the rated current of load, T is the cycle of AC power, and Δ V is the pre- stabilized circuit outputting voltage of prime
Ripple；
Step 6, connecting valve circuit, ON-OFF control circuit, prime input voltage sample circuit, prime output voltage are adopted
Sample circuit and prime output filtering and accumulator, constitute the pre- mu balanced circuit of prime, and its detailed process is as follows：
Step 601, connecting valve circuit：The drain electrode of NMOS tube Q3 is connected with one end of resistance R9, and extraction wire, make
It is the voltage input end of on-off circuit；The grid of NMOS tube Q3 is connected with the other end of resistance R9, and extraction wire, as opening
The switch controlling signal input on powered-down road, by the source electrode extraction wire of NMOS tube Q3, as the output end of on-off circuit；
Step 602, connection prime input voltage sample circuit：Resistance R1 and resistance R2 are connected, and by the electricity after series connection
Resistance R1 and one end of resistance R2 are connected with the voltage input end of on-off circuit, by resistance R1 and the other end of resistance R2 after series connection
Ground connection, by the connection end extraction wire of resistance R1 and resistance R2, as the output end of prime input voltage sample circuit；
Step 603, connection prime output voltage sampling circuit：Resistance R6 and resistance R7 are connected, and by the electricity after series connection
The input that the one end for hindering R6 and resistance R7 exports filtering and accumulator with prime is connected, by resistance R6 and resistance after series connection
The other end ground connection of R7, by the connection end extraction wire of resistance R6 and resistance R7, as the defeated of prime output voltage sampling circuit
Go out end；
Step 604, connecting valve control circuit：The in-phase input end of comparator U1 is defeated with the positive pole of reference voltage source V2
Go out end connection, the cathode output end of reference voltage source V2 is grounded, by the inverting input of comparator U1 and prime input voltage
The output end connection of sample circuit；The in-phase input end of comparator U2 is connected with the cathode output end of reference voltage source V3, will
The cathode output end ground connection of reference voltage source V3 is defeated with prime output voltage sampling circuit by the inverting input of comparator U2
Go out end connection；By two inputs of two input nand gate U3 respectively with the output end and the output end of comparator U2 of comparator U1
Connection, the output end of two input nand gate U3 is connected with the grid of NMOS tube Q2, and the drain electrode extraction wire of NMOS tube Q2 is made
It is the output end of ON-OFF control circuit, by the source ground of NMOS tube Q2；
Step 605, connection prime output filtering and accumulator：The output end of one end of electric capacity C1 and on-off circuit is connected
Connect, the other end of electric capacity C1 is grounded；
The PMOS Q1 of step 7, the suitable parameters of selection composition voltage-regulating circuit：Choose pressure voltage and be more than VD, max's
PMOS model as PMOS Q1, wherein, VD, maxIt is the maximum output voltage of the pre- mu balanced circuit of prime；
The error amplifier X1 and reference voltage source V3 of step 8, the suitable parameters of selection composition error amplifying circuit, its
Detailed process is as follows：
Step 801, selection open-loop voltage gain are not less than 70dB, and error amplifier model of the bandwidth not less than 100kHz is made
It is error amplifier X1；
Step 802, selection can export the reference voltage source model of 1.235V reference voltages source V3 as the reference voltage；
Step 9, according to formulaChoose composition prime output voltage sampling circuit resistance R4 and
The resistance of resistance R5；Wherein, V3 is the output voltage of reference voltage source V3；
Step 10, connection voltage-regulating circuit, secondary output voltage sample circuit and error amplifying circuit, composition are secondary
LDO circuit, its detailed process is as follows：
Step 1001, connection voltage-regulating circuit：By the drain electrode extraction wire of PMOS Q1, as voltage-regulating circuit
Voltage input end；By the grid extraction wire of PMOS Q1, as the control signal input of voltage-regulating circuit；By PMOS
The drain electrode extraction wire of Q1, as the output end of voltage-regulating circuit；
Step 1002, connection secondary output voltage sample circuit：Resistance R4 and resistance R5 are connected, and by the electricity after series connection
Resistance R4 and one end of resistance R5 are connected with the output end of voltage-regulating circuit, by resistance R6 and the other end of resistance R7 after series connection
Ground connection, by the connection end extraction wire of resistance R4 and resistance R5, as the output end of secondary output voltage sample circuit；
Step 1003, connection error amplifying circuit：The in-phase input end of error amplifier X1 and secondary output voltage are adopted
The output end connection of sample circuit, the inverting input of error amplifier X1 is connected with the cathode output end of reference voltage source V4,
The cathode output end of reference voltage source V4 is grounded, by the output end of error amplifier X1 and the control signal of voltage-regulating circuit
Input is connected；
Step 11, the connection pre- mu balanced circuit of prime and secondary LDO circuit, constitute the steady voltage regulator circuit of two-stage, and its is specific
Process is：The voltage input end of voltage-regulating circuit is connected with the output end of on-off circuit.
The technology of the present invention has advantages below compared with prior art：
1st, the circuit structure of the steady voltage regulator circuit of two-stage of the present invention is simple, reasonable in design, realize convenient and low cost.
2nd, when the steady voltage regulator circuit of two-stage of the present invention is used, without that can be directly accessed by whole using transformer and inductance
The civil power of stream, is easy to integrated.
3rd, the steady voltage regulator circuit of two-stage of the invention, employs NMOS tube and PMOS, for being made during integrated regulator,
The low-power consumption of integrated regulator can be realized.
4th, the steady voltage regulator circuit of two-stage of the invention, a DC voltage with ripple is exported by pre- mu balanced circuit,
Again by secondary LDO circuit regulation output voltage, enable to output voltage more reliable, more stable.
5th, the method and step of the method for stabilizing voltage of the steady voltage regulator circuit of two-stage of the present invention is simple, reasonable in design, and it is convenient to realize.
6th, the method and step of the method for designing of the steady voltage regulator circuit of two-stage of the present invention is simple, reasonable in design, and it is convenient to realize, energy
Enough design reliable and stable two-stage LDO circuit.
7th, of the invention practical, using effect is good, with more preferable application value.
In sum, circuit structure of the invention is simple, and low in energy consumption, low cost, ripple is small, and stability is high, and reliability is high,
Practical, using effect is good, with more preferable application value.
Below by drawings and Examples, technical scheme is described in further detail.
Brief description of the drawings
Fig. 1 is the schematic block circuit diagram of the steady voltage regulator circuit of two-stage of the present invention.
Fig. 2 is the circuit theory diagrams of the steady voltage regulator circuit of two-stage of the present invention.
Fig. 3 is the method flow block diagram of the method for stabilizing voltage of the steady voltage regulator circuit of two-stage of the present invention.
Fig. 4 is the method flow block diagram of the method for designing of the steady voltage regulator circuit of two-stage of the present invention.
Description of reference numerals:
The pre- mu balanced circuit of 1-prime；2-on-off circuit；3-prime output filtering and accumulator；
4-prime input voltage sample circuit；5-prime output voltage sampling circuit；
6-ON-OFF control circuit；7-secondary output voltage sample circuit；
8-error amplifying circuit；9-voltage-regulating circuit；10-secondary LDO circuit.
Specific embodiment
As shown in figure 1, the steady voltage regulator circuit of two-stage of the invention, including the pre- mu balanced circuit 1 of prime and secondary LDO circuit
10, the pre- mu balanced circuit 1 of prime includes on-off circuit 2 and ON-OFF control circuit 6, the voltage input end of the on-off circuit 2
It is the input VIN of the steady voltage regulator circuit of the two-stage, the control source of the on-off circuit 2 is terminated with prime input voltage and adopts
Sample circuit 4, the output of the on-off circuit 2 is terminated with prime output filtering and accumulator 3, the prime output filtering and storage
Can the input of circuit 3 be terminated with prime output voltage sampling circuit 5, the output end of the prime input voltage sample circuit 4 and
Input of the output end of prime output voltage sampling circuit 5 with ON-OFF control circuit 6 be connected, and the on-off circuit 2 is opened
Control signal input is closed to be connected with the output end of ON-OFF control circuit 6；The secondary LDO circuit 10 includes the electricity being sequentially connected
Pressure adjustment circuit 9, secondary output voltage sample circuit 7 and error amplifying circuit 8, the control source of the voltage-regulating circuit 9
End is connected with the output end of on-off circuit 2, control signal input and the error amplifying circuit 8 of the voltage-regulating circuit 9
Output end is connected, and the output end of the voltage-regulating circuit 9 is the output end VOUT of the steady voltage regulator circuit of the two-stage.
During specific implementation, input voltage (being obtained by rectifier circuit rectifies by civil power) is obtained by the pre- mu balanced circuit 1 of prime
Arrive compared with burning voltage, then the high stable of output voltage has been realized by secondary LDO circuit 10.
As shown in Fig. 2 in the present embodiment, the on-off circuit 2 includes NMOS tube Q3 and resistance R9, the NMOS tube Q3's
Drain electrode is connected with one end of resistance R9 and is the voltage input end of on-off circuit 2, and the grid of the NMOS tube Q3 is with resistance R9's
The other end connects and is the switch controlling signal input of on-off circuit 2, and the source electrode of the NMOS tube Q3 is the defeated of on-off circuit 2
Go out end.
In the present embodiment, the model IRF431 of the NMOS tube Q3.
As shown in Fig. 2 in the present embodiment, the ON-OFF control circuit 6 include comparator U1, comparator U2, two inputs with
Not gate U3, reference voltage source V1, reference voltage source V2 and NMOS tube Q2, the in-phase input end and reference voltage of the comparator U1
The cathode output end connection of source V1, the cathode output end ground connection of the reference voltage source V1, the anti-phase input of the comparator U1
Hold the first input end for ON-OFF control circuit 6 and be connected with the output end of prime input voltage sample circuit 4；The comparator
The in-phase input end of U2 is connected with the cathode output end of reference voltage source V2, and the cathode output end of the reference voltage source V2 connects
Ground, the inverting input of the comparator U2 is the second input of ON-OFF control circuit 6 and is sampled with prime output voltage electric
The output end connection on road 5；Two inputs of the two input nand gates U3 respectively with the output end and comparator of comparator U1
The output end connection of U2, the output end of the two input nand gates U3 is connected with the grid of NMOS tube Q2, the NMOS tube Q2's
It is the output end of ON-OFF control circuit 6 to drain, the source ground of the NMOS tube Q2.
In the present embodiment, the model of the comparator U1 and comparator U2 is LM393, the two input nand gates U3's
The model IRF720A of model CD4011, the NMOS tube Q2, the model of the reference voltage source V1 and reference voltage source V2
It is LM4140.
As shown in Fig. 2 in the present embodiment, the prime input voltage sample circuit 4 includes the resistance R1 and resistance of series connection
R2, one end of resistance R1 and resistance R2 after series connection is connected with the voltage input end of on-off circuit 2, resistance R1 and electricity after series connection
The other end ground connection of R2 is hindered, the connection end of the resistance R1 and resistance R2 is the output end of prime input voltage sample circuit 4.Institute
Stating prime output voltage sampling circuit 5 includes the resistance R6 and resistance R7 of series connection, one end of resistance R6 and resistance R7 after series connection
The input for exporting filtering and accumulator 3 with prime is connected, the other end ground connection of resistance R6 and resistance R7 after series connection, described
The connection end of resistance R6 and resistance R7 is the output end of prime output voltage sampling circuit 5.The prime output filtering and energy storage
Circuit 3 includes that one end of electric capacity C1, the electric capacity C1 export the input and and on-off circuit of filtering and accumulator 3 for prime
2 output end connection, the other end ground connection of the electric capacity C1.
As shown in Fig. 2 in the present embodiment, the voltage-regulating circuit 9 includes PMOS Q1, the drain electrode of the PMOS Q1
It is the voltage input end of voltage-regulating circuit 9, the grid of the PMOS Q1 is the control signal input of voltage-regulating circuit 9
End, the drain electrode of the PMOS Q1 is the output end of voltage-regulating circuit 9.The secondary output voltage sample circuit 7 includes string
The resistance R4 and resistance R5 of connection, one end of resistance R4 and resistance R5 after series connection are connected with the output end of voltage-regulating circuit 9, string
The other end ground connection of resistance R6 and resistance R7 after connection, the connection end of the resistance R4 and resistance R5 is secondary output voltage sampling
The output end of circuit 7.The error amplifying circuit 8 includes error amplifier X1 and reference voltage source V3, the error amplifier
The in-phase input end of X1 is connected with the output end of secondary output voltage sample circuit 7, the anti-phase input of the error amplifier X1
End is connected with the cathode output end of reference voltage source V3, and the cathode output end ground connection of the reference voltage source V3, the error is put
The output end of big device X1 is the output end of error amplifying circuit 8 and is connected with the control signal input of voltage-regulating circuit 9.
In the present embodiment, model IRF720A, the model LM358 of the error amplifier X1 of the PMOS Q1,
The model LM385 of the reference voltage source V3.
As shown in figure 3, the method for stabilizing voltage of the steady voltage regulator circuit of two-stage of the invention, comprises the following steps：
The pre- mu balanced circuit 1 of step A, prime is exported by rectifier circuit rectifies to civil power and carried out to its half sine wave voltage
Pre- voltage stabilizing：The half-sine wave ascent stage of Output Voltage in Rectified Circuits, voltage is started from scratch and gradually increase, when the electricity of on-off circuit 2
Pressure input terminal voltage is increased to when can turn on on-off circuit 2, and on-off circuit 2 is turned on, and prime output is filtered and accumulator 3
Start energy storage；Meanwhile, prime input voltage sample circuit 4 carries out real-time detection simultaneously to the control source terminal voltage of on-off circuit 2
The voltage output that will be detected detects prime input voltage sample circuit 4 to ON-OFF control circuit 6, ON-OFF control circuit 6
The first shut-off threshold voltage of voltage and default NMOS tube Q3 be compared, with the voltage input end electricity of on-off circuit 2
Pressure further increase, when first shut-off of the voltage more than default NMOS tube Q3 that prime input voltage sample circuit 4 is detected
During threshold voltage, the controlling switch circuit 2 of ON-OFF control circuit 6 is turned off, and prime output filtering and accumulator 3 discharge, output electricity
Press to secondary LDO circuit 10；Output Voltage in Rectified Circuits enters half-sine wave descending branch after increasing to peak value, and voltage is opened from peak value
Beginning is gradually reduced, in first shut-off threshold of the voltage more than default NMOS tube Q3 that prime input voltage sample circuit 4 is detected
During threshold voltage, on-off circuit 2 has been at off state, meanwhile, prime output voltage sampling circuit 5 to prime export filtering and
Accumulator 3 enters out that terminal voltage carries out real-time detection and the voltage output that will detect is to ON-OFF control circuit 6, switch control
The voltage that circuit 6 detects prime output voltage sampling circuit 5 enters with the second shut-off threshold voltage of default NMOS tube Q3
Row compares；Control source terminal voltage with on-off circuit 2 further reduces, when prime input voltage sample circuit 4 is detected
First shut-off threshold voltage of the voltage less than default NMOS tube Q3, and the electricity that prime output voltage sampling circuit 5 is detected
When pressure turns off threshold voltage more than the second of default NMOS tube Q3, on-off circuit 2 is still off, and prime output is filtered and energy storage
Circuit 3 continues to discharge, and output voltage gives secondary LDO circuit 10；Control source terminal voltage with on-off circuit 2 further subtracts
It is small, when the voltage that prime output voltage sampling circuit 5 is detected turns off threshold voltage less than the second of default NMOS tube Q3,
The controlling switch circuit 2 of ON-OFF control circuit 6 is turned on, and prime output filtering and accumulator 3 start again at energy storage, while exporting electricity
Press to secondary LDO circuit 10；When the control source terminal voltage of on-off circuit 2 is reduced to is insufficient to allow on-off circuit 2 to turn on, open
Powered-down road 2 turns off, and prime output filtering and accumulator 3 discharge, and output voltage gives secondary LDO circuit 10, until rectification circuit
The half-sine wave ascent stage of the next cycle of output voltage；Wherein, the first shut-off threshold voltage of the NMOS tube Q3 is to open
Close the shut-off threshold voltage that control circuit 6 controls NMOS tube Q3 to turn off according to the sampled voltage of prime input voltage sample circuit 4；Institute
The the second shut-off threshold voltage for stating NMOS tube Q3 is ON-OFF control circuit 6 according to the sampled voltage of prime output voltage sampling circuit 5
The shut-off threshold voltage of control NMOS tube Q3 shut-offs；
With reference to physical circuit, the detailed process of step A is：The half-sine wave ascent stage of Output Voltage in Rectified Circuits, voltage
Start from scratch and gradually increase, the gate source voltage of NMOS tube Q3 is more than when the control source terminal voltage of on-off circuit 2 is increased to
During the on state threshold voltage of NMOS tube Q3, NMOS tube Q3 conductings, electric capacity C1 starts energy storage；Meanwhile, prime input voltage sampling electricity
The voltage output that road 4 carries out real-time detection and will detect to the control source terminal voltage of on-off circuit 2 is to ON-OFF control circuit
6, voltage and reference voltage source V1 that the comparator U1 in ON-OFF control circuit 6 detects prime input voltage sample circuit 4
It is supplied to its reference voltage to be compared, the control source terminal voltage with on-off circuit 2 further increases, when prime input
When the voltage that voltage sampling circuit 4 is detected is more than the reference voltage that reference voltage source V1 is provided, comparator U1 output low levels,
Two input nand gate U3 export high level, and NMOS tube Q2 conductings, NMOS tube Q3 shut-offs, electric capacity C1 electric discharges, output voltage gives secondary
LDO circuit 10；Output Voltage in Rectified Circuits enters half-sine wave descending branch after increasing to peak value, and voltage gradually subtracts since peak value
It is small, when the voltage that prime input voltage sample circuit 4 is detected is more than the reference voltage that reference voltage source V1 is provided, NMOS tube
Q3 has been at off state, meanwhile, prime output voltage sampling circuit 5 exports filtering to prime and accumulator 3 enters out
Terminal voltage carries out real-time detection and the voltage output that will detect is to ON-OFF control circuit 6, the comparator in ON-OFF control circuit 6
The voltage that U2 detects prime output voltage sampling circuit 5 is supplied to its reference voltage to be compared with reference voltage source V2
Compared with；Control source terminal voltage with on-off circuit 2 further reduces, when the electricity that prime input voltage sample circuit 4 is detected
Pressure is less than the reference voltage that reference voltage source V1 is provided, and the voltage that prime output voltage sampling circuit 5 is detected is more than reference
During the reference voltage that voltage source V2 is provided, comparator U1 output high level, comparator U2 output low levels, two input nand gate U3
Output high level, NMOS tube Q2 conductings, NMOS tube Q3 is still off, and electric capacity C1 continues to discharge, and output voltage gives secondary LDO circuit
10；Control source terminal voltage with on-off circuit 2 further reduces, when the electricity that prime output voltage sampling circuit 5 is detected
When pressure is less than the reference voltage that reference voltage source V2 is provided, comparator U2 output high level, two input nand gate U3 export low electricity
Flat, NMOS tube Q2 shut-offs, NMOS tube Q3 conductings, electric capacity C1 starts again at energy storage, while output voltage gives secondary LDO circuit 10；
When the control source terminal voltage of on-off circuit 2 is reduced to the conduction threshold electricity for making the gate source voltage of NMOS tube Q3 less than NMOS tube Q3
During pressure, NMOS tube Q3 shut-offs, electric capacity C1 electric discharges, output voltage gives secondary LDO circuit 10, until under Output Voltage in Rectified Circuits
The half-sine wave ascent stage of a cycle；
The pre- mu balanced circuit 1 of prime is constantly sampled more than, control, makes switching tube Q3 on or off, electric capacity C1 weeks
The discharge and recharge of phase property, finally makes the voltage stabilization of the pre- output of mu balanced circuit 1 of prime by reference to voltage source V1 and reference voltage source
In the range of V2 settings.
Step B, secondary LDO circuit 10 are exported to the pre- mu balanced circuit 1 of prime and carry out further voltage stabilizing to its voltage：Currently
The voltage of the pre- output of mu balanced circuit 1 of level has the trend of reduction, and the voltage for causing secondary LDO circuit 10 to export has the trend of reduction
When, the voltage that secondary output voltage sample circuit 7 is detected reduces, and the voltage of the output of error amplifying circuit 8 also reduces, and voltage is adjusted
When the voltage that whole circuit 9 detects the output of error amplifying circuit 8 reduces, the electric current increase of voltage-regulating circuit 9 is flowed through in adjustment, makes
The voltage increase of the output of secondary LDO circuit 10, it is ensured that the output voltage stabilization of secondary LDO circuit 10；When the pre- mu balanced circuit 1 of prime is defeated
The voltage for going out has the trend of increase, and when the voltage for causing secondary LDO circuit 10 to export has the trend of increase, secondary output voltage is adopted
The voltage increase that sample circuit 7 is detected, the voltage of the output of error amplifying circuit 8 also increases, and voltage-regulating circuit 9 detects error
When the voltage of the output of amplifying circuit 8 increases, the electric current that voltage-regulating circuit 9 is flowed through in adjustment reduces, and exports secondary LDO circuit 10
Voltage reduce, it is ensured that the output voltage stabilization of secondary LDO circuit 10.
With reference to physical circuit, the detailed process of step B is：When the voltage of the pre- output of mu balanced circuit 1 of prime has becoming for reduction
Gesture, when the voltage for causing secondary LDO circuit 10 to export has the trend of reduction, the electricity that secondary output voltage sample circuit 7 is detected
Pressure reduce, error amplifier X1 output voltage also reduce (i.e. voltage-regulating circuit 9 detect error amplifier X1 output
Voltage reduces), the increase of PMOS Q1 electric currents, the electricity for exporting secondary LDO circuit 10 are flowed through in the gate source voltage increase of PMOS Q1
Pressure increase, it is ensured that the output voltage stabilization of secondary LDO circuit 10；When the voltage of the pre- output of mu balanced circuit 1 of prime has the trend of increase,
When the voltage for causing secondary LDO circuit 10 to export has the trend of increase, the voltage that secondary output voltage sample circuit 7 is detected increases
Greatly, error amplifier X1 output voltage also increase (i.e. voltage-regulating circuit 9 detect error amplifier X1 output voltage
Increase), the gate source voltage of PMOS Q1 reduces, and flows through the reduction of PMOS Q1 electric currents, and the voltage for exporting secondary LDO circuit 10 subtracts
It is small, it is ensured that the output voltage stabilization of secondary LDO circuit 10.
As shown in figure 4, the method for designing of the steady voltage regulator circuit of two-stage of the invention, comprises the following steps：
The NMOS tube Q3 and resistance R9 of step one, the suitable parameters of selection composition on-off circuit 2, its detailed process are as follows：
Step 101, NMOS tube Q3 is chosen, detailed process is：
Step 1011, according to formula VQ3,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q3 is subjected toQ3,max, its
In, Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
In the present embodiment, Vin,max=375V, VQ3,max=375V；
Step 1012, selection pressure voltage are more than VQ3,maxNMOS tube model as NMOS tube Q3；
In the present embodiment, the model IRF431 of the NMOS tube Q3；
Step 102, the resistance that resistance R9 is chosen according to 1k Ω ＜ R9 ＜ 100k Ω；
In the present embodiment, the resistance of resistance R9 is chosen for 10k Ω；Resistance R9 provides driving voltage for NMOS tube Q3 grids；
Step 2, the comparator U1 of suitable parameters of selection composition on-off circuit 2, comparator U2, two input nand gate U3,
Reference voltage source V1, reference voltage source V2 and NMOS tube Q2, its detailed process are as follows：
Step 201, selection single supply are powered and supply voltage is the comparator model of 5V and propagation delay time no more than 250ns
As comparator U1 and comparator U2；
In the present embodiment, the model of the comparator U1 and comparator U2 is LM393；
Step 202, two input nand gates of selection disposable type are used as two input nand gate U3；
In the present embodiment, the model CD4011 of the two input nand gates U3；
Step 203, NMOS tube Q2 is chosen, detailed process is：
Step 2031, according to formula VQ2,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q2 is subjected toQ2,max, its
In, Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
In the present embodiment, Vin,max=375V, VQ2,max=375V；
Step 2032, selection pressure voltage are more than VQ2,maxNMOS tube model as NMOS tube Q2；
In the present embodiment, the model IRF720A of the NMOS tube Q2；
Step 204, selection can export the reference voltage source model of 2V reference voltages source V1 as the reference voltage；
In the present embodiment, the model LM4140 of the reference voltage source V1；
Step 205, selection can export the reference voltage source model of 2V reference voltages source V2 as the reference voltage；
In the present embodiment, the model LM4140 of the reference voltage source V2；
Step 3, according to formulaChoose the resistance R1 of composition prime input voltage sample circuit 4
With the resistance of resistance R2；Wherein, V1 is the output voltage of reference voltage source V1, VQ3For ON-OFF control circuit 6 is input into according to prime
The shut-off threshold voltage of the sampled voltage of voltage sampling circuit 4 control NMOS tube Q3 shut-offs；
In the present embodiment, V1=2V, VQ3=35V, the resistance for choosing resistance R1 is 15k Ω, and the resistance of resistance R2 is 1k Ω；
During specific implementation, after NMOS tube Q3 is selected, its on state threshold voltage VQ3Determine that；The resistance of resistance R1 and resistance R2
Value is tried one's best and takes the big power consumption to reduce resistance R1 and resistance R2；
Step 4, according to formulaChoose the resistance R6 of composition prime output voltage sampling circuit 5
With the resistance of resistance R7；Wherein, V2 is the output voltage of reference voltage source V2, VC1For ON-OFF control circuit 6 is exported according to prime
The shut-off threshold voltage of the sampled voltage of voltage sampling circuit 5 control NMOS tube Q3 shut-offs is also the voltage at electric capacity C1 two ends；
In the present embodiment, V2=2V, VC1=14V, the resistance for choosing resistance R6 is 12k Ω, and the resistance of resistance R7 is 2k Ω；
During specific implementation, the setting value being actually needed according to the threshold voltage of control NMOS tube Q3 shut-offs；Resistance R6 and
The resistance of resistance R7 is tried one's best and takes the big power consumption to reduce resistance R6 and resistance R7；
Step 5, according to formulaChoose the appearance of the electric capacity C1 for constituting prime output filtering and accumulator 3
Value；Wherein, IloadIt is the rated current of load, T is the cycle of AC power, and Δ V is the pre- output voltage of mu balanced circuit 1 of prime
Ripple；
In the present embodiment, Iload=50mA, T=20ms, the capacitance of Δ V=1.5V, electric capacity C1 is 330 μ f；
During specific implementation, the rated current I of loadloadAccording to the ripple Δ V of the pre- output voltage of mu balanced circuit 1 of prime
The setting value being actually needed；The value of Δ V is general between 1V~2V；
Step 6, connecting valve circuit 2, ON-OFF control circuit 6, prime input voltage sample circuit 4, prime output voltage
Sample circuit 5 and prime output filtering and accumulator 3, constitute the pre- mu balanced circuit 1 of prime, and its detailed process is as follows：
Step 601, connecting valve circuit 2：The drain electrode of NMOS tube Q3 is connected with one end of resistance R9, and extraction wire,
As the voltage input end of on-off circuit 2；The grid of NMOS tube Q3 is connected with the other end of resistance R9, and extraction wire, make
It is the switch controlling signal input of on-off circuit 2, by the source electrode extraction wire of NMOS tube Q3, as the output of on-off circuit 2
End；
Step 602, connection prime input voltage sample circuit 4：Resistance R1 and resistance R2 are connected, and by the electricity after series connection
The one end for hindering R1 and resistance R2 is connected with the voltage input end of on-off circuit 2, by the another of the resistance R1 after series connection and resistance R2
End ground connection, by the connection end extraction wire of resistance R1 and resistance R2, as the output end of prime input voltage sample circuit 4；
Step 603, connection prime output voltage sampling circuit 5：Resistance R6 and resistance R7 are connected, and by the electricity after series connection
The input that the one end for hindering R6 and resistance R7 exports filtering and accumulator 3 with prime is connected, by resistance R6 and electricity after series connection
The other end ground connection of R7 is hindered, by the connection end extraction wire of resistance R6 and resistance R7, as prime output voltage sampling circuit 5
Output end；
Step 604, connecting valve control circuit 6：By the in-phase input end of comparator U1 and the positive pole of reference voltage source V2
Output end is connected, and the cathode output end of reference voltage source V2 is grounded, and the inverting input of comparator U1 and prime are input into electricity
Press the output end connection of sample circuit 4；The in-phase input end of comparator U2 is connected with the cathode output end of reference voltage source V3,
The cathode output end of reference voltage source V3 is grounded, by the inverting input of comparator U2 and prime output voltage sampling circuit 5
Output end connection；Two inputs of two input nand gate U3 are defeated with the output end of comparator U1 and comparator U2 respectively
Go out end connection, the output end of two input nand gate U3 is connected with the grid of NMOS tube Q2, the drain electrode of NMOS tube Q2 is drawn and is led
Line, as the output end of ON-OFF control circuit 6, by the source ground of NMOS tube Q2；
Step 605, connection prime output filtering and accumulator 3：By one end of electric capacity C1 and the output end of on-off circuit 2
Connection, the other end of electric capacity C1 is grounded；
The PMOS Q1 of step 7, the suitable parameters of selection composition voltage-regulating circuit 9：Choose pressure voltage and be more than VD, max's
PMOS model as PMOS Q1, wherein, VD, maxIt is the maximum output voltage of the pre- mu balanced circuit 1 of prime；
In the present embodiment, VD, max=14V；The model 2N7002 of the PMOS Q1；
During specific implementation, the output voltage V of the pre- mu balanced circuit 1 of primeDOutput electricity with the steady voltage regulator circuit of the two-stage
Pressure VOUTAccording to the setting value that is actually needed；
The error amplifier X1 and reference voltage source V3 of step 8, the suitable parameters of selection composition error amplifying circuit 8, its
Detailed process is as follows：
Step 801, selection open-loop voltage gain are not less than 70dB, and error amplifier model of the bandwidth not less than 100kHz is made
It is error amplifier X1；
In the present embodiment, the model LM358 of the error amplifier X1；
Step 802, selection can export the reference voltage source model of 1.235V reference voltages source V3 as the reference voltage；
In the present embodiment, the model LM385 of the reference voltage source V3；
Step 9, according to formulaChoose the resistance R4 of composition prime output voltage sampling circuit 5
With the resistance of resistance R5；Wherein, V3 is the output voltage of reference voltage source V3；
In the present embodiment, V3=1.235V, VOUT=12V, the resistance for choosing resistance R4 is 9.1k Ω, the resistance of resistance R5
It is 1k Ω；
During specific implementation, the resistance of resistance R4 and resistance R5 is tried one's best and takes the big power consumption to reduce resistance R4 and resistance R5；
Step 10, connection voltage-regulating circuit 9, secondary output voltage sample circuit 7 and error amplifying circuit 8, composition
Level LDO circuit 10, its detailed process is as follows：
Step 1001, connection voltage-regulating circuit 9：By the drain electrode extraction wire of PMOS Q1, as voltage-regulating circuit 9
Voltage input end；By the grid extraction wire of PMOS Q1, as the control signal input of voltage-regulating circuit 9；Will
The drain electrode extraction wire of PMOS Q1, as the output end of voltage-regulating circuit 9；
Step 1002, connection secondary output voltage sample circuit 7：Resistance R4 and resistance R5 is connected, and by after series connection
One end of resistance R4 and resistance R5 are connected with the output end of voltage-regulating circuit 9, by the another of the resistance R6 after series connection and resistance R7
One end is grounded, by the connection end extraction wire of resistance R4 and resistance R5, as the output end of secondary output voltage sample circuit 7；
Step 1003, connection error amplifying circuit 8：The in-phase input end of error amplifier X1 and secondary output voltage are adopted
The output end connection of sample circuit 7, the inverting input of error amplifier X1 is connected with the cathode output end of reference voltage source V4,
The cathode output end of reference voltage source V4 is grounded, the control of the output end of error amplifier X1 and voltage-regulating circuit 9 is believed
The connection of number input；
Step 11, the connection pre- mu balanced circuit 1 of prime and secondary LDO circuit 10, constitute the steady voltage regulator circuit of two-stage, its tool
Body process is：The voltage input end of voltage-regulating circuit 9 is connected with the output end of on-off circuit 2.
The above, is only presently preferred embodiments of the present invention, and not the present invention is imposed any restrictions, every according to the present invention
Any simple modification, change and equivalent structure change that technical spirit is made to above example, still fall within skill of the present invention
In the protection domain of art scheme.
Claims (10)
1. the steady voltage regulator circuit of a kind of two-stage, it is characterised in that：Including the pre- mu balanced circuit of prime (1) and secondary LDO circuit (10),
The pre- mu balanced circuit of prime (1) includes on-off circuit (2) and ON-OFF control circuit (6), and the voltage of the on-off circuit (2) is defeated
It is the input VIN of the steady voltage regulator circuit of the two-stage to enter end, and the control source of the on-off circuit (2) is terminated with prime input
Voltage sampling circuit (4), the output of the on-off circuit (2) is terminated with prime output filtering and accumulator (3), the prime
Output filtering and the input of accumulator (3) are terminated with prime output voltage sampling circuit (5), the prime input voltage sampling
The output end of circuit (4) and the output end of prime output voltage sampling circuit (5) connect with the input of ON-OFF control circuit (6)
Connect, the switch controlling signal input of the on-off circuit (2) is connected with the output end of ON-OFF control circuit (6)；The secondary
LDO circuit (10) amplifies electricity including voltage-regulating circuit (9), secondary output voltage sample circuit (7) and the error being sequentially connected
Road (8), the voltage input end of the voltage-regulating circuit (9) is connected with the output end of on-off circuit (2), the voltage adjustment electricity
The control signal input on road (9) is connected with the output end of error amplifying circuit (8), the output of the voltage-regulating circuit (9)
It is the output end VOUT of the steady voltage regulator circuit of the two-stage to hold.
2. according to the steady voltage regulator circuit of a kind of two-stage described in claim 1, it is characterised in that：The on-off circuit (2) includes
NMOS tube Q3 and resistance R9, the drain electrode of the NMOS tube Q3 is connected and with one end of resistance R9 for the voltage of on-off circuit (2) is defeated
Enter end, the grid of the NMOS tube Q3 is connected and with the other end of resistance R9 for the switch controlling signal of on-off circuit (2) is input into
End, the source electrode of the NMOS tube Q3 is the output end of on-off circuit (2).
3. according to the steady voltage regulator circuit of a kind of two-stage described in claim 2, it is characterised in that：The model of the NMOS tube Q3
IRF431。
4. according to the steady voltage regulator circuit of a kind of two-stage described in claim 2, it is characterised in that：The ON-OFF control circuit (6)
It is described including comparator U1, comparator U2, two input nand gate U3, reference voltage source V1, reference voltage source V2 and NMOS tube Q2
The in-phase input end of comparator U1 is connected with the cathode output end of reference voltage source V1, the negative pole output of the reference voltage source V1
End ground connection, the inverting input of the comparator U1 for ON-OFF control circuit (6) first input end and with prime input voltage
The output end connection of sample circuit (4)；The in-phase input end of the comparator U2 connects with the cathode output end of reference voltage source V2
Connect, the cathode output end ground connection of the reference voltage source V2, the inverting input of the comparator U2 is ON-OFF control circuit (6)
The second input and be connected with the output end of prime output voltage sampling circuit (5)；Two of the two input nand gates U3
Input is connected with the output end of comparator U1 and the output end of comparator U2 respectively, the output end of the two input nand gates U3
Grid with NMOS tube Q2 is connected, and the drain electrode of the NMOS tube Q2 is the output end of ON-OFF control circuit (6), the NMOS tube Q2
Source ground.
5. according to the steady voltage regulator circuit of a kind of two-stage described in claim 4, it is characterised in that：The comparator U1 and comparator
The model of U2 is LM393, the model CD4011 of the two input nand gates U3, the model of the NMOS tube Q2
IRF720A, the model of the reference voltage source V1 and reference voltage source V2 is LM4140.
6. according to the steady voltage regulator circuit of a kind of two-stage described in claim 4, it is characterised in that：The prime input voltage sampling
Resistance R1 and resistance R2 of the circuit (4) including series connection, one end of resistance R1 and resistance R2 after series connection and the electricity of on-off circuit (2)
Pressure input connection, the other end ground connection of resistance R1 and resistance R2 after series connection, the connection end of the resistance R1 and resistance R2 is
The output end of prime input voltage sample circuit (4)；The prime output voltage sampling circuit (5) including connect resistance R6 and
The input that one end of resistance R7, resistance R6 and resistance R7 after series connection export filtering and accumulator (3) with prime is connected, and goes here and there
The other end ground connection of resistance R6 and resistance R7 after connection, the connection end of the resistance R6 and resistance R7 is the sampling of prime output voltage
The output end of circuit (5)；The prime output filtering and accumulator (3) include electric capacity C1, and one end of the electric capacity C1 is preceding
Level exports the input of filtering and accumulator (3) and is connected with the output end of on-off circuit (2), the other end of the electric capacity C1
Ground connection.
7. according to the steady voltage regulator circuit of a kind of two-stage described in claim 6, it is characterised in that：The voltage-regulating circuit (9)
Including PMOS Q1, the drain electrode of the PMOS Q1 is the voltage input end of voltage-regulating circuit (9), the grid of the PMOS Q1
The extremely control signal input of voltage-regulating circuit (9), the drain electrode of the PMOS Q1 is the output of voltage-regulating circuit (9)
End；The secondary output voltage sample circuit (7) including connect resistance R4 and resistance R5, resistance R4 and resistance R5 after series connection
One end be connected with the output end of voltage-regulating circuit (9), the other end of resistance R6 and resistance R7 after series connection ground connection, the electricity
The connection end for hindering R4 and resistance R5 is the output end of secondary output voltage sample circuit (7)；The error amplifying circuit (8) includes
The in-phase input end of error amplifier X1 and reference voltage source V3, the error amplifier X1 and secondary output voltage sample circuit
(7) output end connection, the inverting input of the error amplifier X1 is connected with the cathode output end of reference voltage source V3, institute
The cathode output end ground connection of reference voltage source V3 is stated, the output end of the error amplifier X1 is the defeated of error amplifying circuit (8)
Go out end and be connected with the control signal input of voltage-regulating circuit (9).
8. according to the steady voltage regulator circuit of a kind of two-stage described in claim 7, it is characterised in that：The model of the PMOS Q1
The model LM358, the model LM385 of the reference voltage source V3 of IRF720A, the error amplifier X1.
9. a kind of method for stabilizing voltage of the steady voltage regulator circuit of two-stage as claimed in claim 1, it is characterised in that the method includes following
Step：
Step A, prime pre- mu balanced circuit (1) civil power is exported by rectifier circuit rectifies carried out to its half sine wave voltage it is pre-
Voltage stabilizing：The half-sine wave ascent stage of Output Voltage in Rectified Circuits, voltage is started from scratch and gradually increase, when the electricity of on-off circuit (2)
Pressure input terminal voltage is increased to when can turn on on-off circuit (2), and on-off circuit (2) conducting, prime output is filtered and energy storage
Circuit (3) starts energy storage；Meanwhile, prime input voltage sample circuit (4) is carried out to the control source terminal voltage of on-off circuit (2)
The real-time detection and voltage output that will be detected adopts prime input voltage to ON-OFF control circuit (6), ON-OFF control circuit (6)
The voltage that sample circuit (4) is detected is compared with the first shut-off threshold voltage of default NMOS tube Q3, with on-off circuit
(2) control source terminal voltage further increases, and the voltage detected when prime input voltage sample circuit (4) is more than default
During the first shut-off threshold voltage of NMOS tube Q3, ON-OFF control circuit (6) controlling switch circuit (2) shut-off, prime output filtering
And accumulator (3) discharges, Output Voltage in Rectified Circuits enters half-sine wave descending branch after increasing to peak value, and voltage is opened from peak value
Beginning is gradually reduced, in first shut-off of the voltage more than default NMOS tube Q3 that prime input voltage sample circuit (4) is detected
During threshold voltage, on-off circuit (2) has been at off state, meanwhile, prime output voltage sampling circuit (5) is exported to prime
Filtering and accumulator (3) enter out that terminal voltage carries out real-time detection and the voltage output that will detect is to ON-OFF control circuit
(6) voltage that, ON-OFF control circuit (6) detects prime output voltage sampling circuit (5) and the of default NMOS tube Q3
Two shut-off threshold voltages are compared；Control source terminal voltage with on-off circuit (2) further reduces, when prime is input into electricity
First shut-off threshold voltage of the voltage that pressure sample circuit (4) is detected less than default NMOS tube Q3, and prime output voltage
When the voltage that sample circuit (5) is detected turns off threshold voltage more than the second of default NMOS tube Q3, on-off circuit (2) is still
Shut-off, prime output filtering and accumulator (3) continue to discharge, and output voltage gives secondary LDO circuit (10)；With on-off circuit
(2) control source terminal voltage further reduces, and the voltage detected when prime output voltage sampling circuit (5) is less than default
During the second shut-off threshold voltage of NMOS tube Q3, ON-OFF control circuit (6) controlling switch circuit (2) conducting, prime output filtering
And accumulator (3) starts again at energy storage, while output voltage gives secondary LDO circuit (10)；When the voltage of on-off circuit (2) is defeated
Enter terminal voltage be reduced to be insufficient to allow on-off circuit (2) turn on when, on-off circuit (2) shut-off, prime output filtering and energy storage electricity
Road (3) is discharged, and output voltage gives secondary LDO circuit (10), until the semisinusoidal of the next cycle of Output Voltage in Rectified Circuits
The ripple ascent stage；Wherein, the first shut-off threshold voltage of the NMOS tube Q3 is ON-OFF control circuit (6) according to prime input voltage
The shut-off threshold voltage of sample circuit (4) sampled voltage control NMOS tube Q3 shut-offs；The second shut-off threshold value of the NMOS tube Q3
Voltage is the pass that ON-OFF control circuit (6) controls NMOS tube Q3 shut-offs according to prime output voltage sampling circuit (5) sampled voltage
Disconnected threshold voltage；
Step B, secondary LDO circuit (10) export to the pre- mu balanced circuit of prime (1) and carry out further voltage stabilizing to its voltage：Currently
The voltage of pre- mu balanced circuit (1) output of level has the trend of reduction, and the voltage for causing secondary LDO circuit (10) to export has becoming for reduction
During gesture, the voltage that secondary output voltage sample circuit (7) is detected reduces, and the voltage of error amplifying circuit (8) output also reduces,
When the voltage that voltage-regulating circuit (9) detects error amplifying circuit (8) output reduces, voltage-regulating circuit (9) is flowed through in adjustment
Electric current increase, make secondary LDO circuit (10) export voltage increase, it is ensured that secondary LDO circuit (10) output voltage stabilization；When
The voltage of the pre- mu balanced circuit of prime (1) output has the trend of increase, and the voltage for causing secondary LDO circuit (10) to export has increase
During trend, the voltage increase that secondary output voltage sample circuit (7) is detected, the voltage of error amplifying circuit (8) output also increases
Greatly, when voltage-regulating circuit (9) detects the voltage increase of error amplifying circuit (8) output, voltage-regulating circuit is flowed through in adjustment
(9) electric current reduces, and the voltage for exporting secondary LDO circuit (10) reduces, it is ensured that secondary LDO circuit (10) output voltage is steady
It is fixed.
10. a kind of method for designing of the steady voltage regulator circuit of two-stage as claimed in claim 7, it is characterised in that the method include with
Lower step：
The NMOS tube Q3 and resistance R9 of step one, the suitable parameters of selection composition on-off circuit (2), its detailed process are as follows：
Step 101, NMOS tube Q3 is chosen, detailed process is：
Step 1011, according to formula VQ3,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q3 is subjected toQ3,max, wherein,
Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
Step 1012, selection pressure voltage are more than VQ3,maxNMOS tube model as NMOS tube Q3；
Step 102, the resistance that resistance R9 is chosen according to 1k Ω ＜ R9 ＜ 100k Ω；
Step 2, the comparator U1 of the suitable parameters of selection composition on-off circuit (2), comparator U2, two input nand gate U3, ginseng
Voltage source V1, reference voltage source V2 and NMOS tube Q2 are examined, its detailed process is as follows：
Step 201, selection single supply are powered and supply voltage is the comparator model conduct of 5V and propagation delay time no more than 250ns
Comparator U1 and comparator U2；
Step 202, two input nand gates of selection disposable type are used as two input nand gate U3；
Step 203, NMOS tube Q2 is chosen, detailed process is：
Step 2031, according to formula VQ2,max=Vin,maxCalculate the maximum voltage V that NMOS tube Q2 is subjected toQ2,max, wherein,
Vin,maxIt is the maximum input voltage of the steady voltage regulator circuit of the two-stage；
Step 2032, selection pressure voltage are more than VQ2,maxNMOS tube model as NMOS tube Q2；
Step 204, selection can export the reference voltage source model of 2V reference voltages source V1 as the reference voltage；
Step 205, selection can export the reference voltage source model of 2V reference voltages source V2 as the reference voltage；
Step 3, according to formulaChoose the resistance R1 and electricity of composition prime input voltage sample circuit (4)
Hinder the resistance of R2；Wherein, V1 is the output voltage of reference voltage source V1, VQ3For ON-OFF control circuit (6) is input into electricity according to prime
The shut-off threshold voltage of pressure sample circuit (4) sampled voltage control NMOS tube Q3 shut-offs；
Step 4, according to formulaChoose composition prime output voltage sampling circuit (5) resistance R6 and
The resistance of resistance R7；Wherein, V2 is the output voltage of reference voltage source V2, VC1For ON-OFF control circuit (6) is exported according to prime
The shut-off threshold voltage of voltage sampling circuit (5) sampled voltage control NMOS tube Q3 shut-offs；
Step 5, according to formulaChoose the capacitance of the electric capacity C1 for constituting prime output filtering and accumulator (3)；
Wherein, IloadIt is the rated current of load, T is the cycle of AC power, and Δ V is prime pre- mu balanced circuit (1) output voltage
Ripple；
Step 6, connecting valve circuit (2), ON-OFF control circuit (6), prime input voltage sample circuit (4), prime output electricity
Pressure sample circuit (5) and prime output filtering and accumulator (3), the composition pre- mu balanced circuit of prime (1), its detailed process is such as
Under：
Step 601, connecting valve circuit (2)：The drain electrode of NMOS tube Q3 is connected with one end of resistance R9, and extraction wire, make
It is the voltage input end of on-off circuit (2)；The grid of NMOS tube Q3 is connected with the other end of resistance R9, and extraction wire, make
It is the switch controlling signal input of on-off circuit (2), by the source electrode extraction wire of NMOS tube Q3, as on-off circuit (2)
Output end；
Step 602, connection prime input voltage sample circuit (4)：Resistance R1 and resistance R2 are connected, and by the resistance after series connection
One end of R1 and resistance R2 are connected with the voltage input end of on-off circuit (2), by the another of the resistance R1 after series connection and resistance R2
End ground connection, by the connection end extraction wire of resistance R1 and resistance R2, as the output end of prime input voltage sample circuit (4)；
Step 603, connection prime output voltage sampling circuit (5)：Resistance R6 and resistance R7 are connected, and by the resistance after series connection
The input that one end of R6 and resistance R7 export filtering and accumulator (3) with prime is connected, by resistance R6 and electricity after series connection
The other end ground connection of R7 is hindered, by the connection end extraction wire of resistance R6 and resistance R7, as prime output voltage sampling circuit (5)
Output end；
Step 604, connecting valve control circuit (6)：The in-phase input end of comparator U1 is defeated with the positive pole of reference voltage source V2
Go out end connection, the cathode output end of reference voltage source V2 is grounded, by the inverting input of comparator U1 and prime input voltage
The output end connection of sample circuit (4)；The in-phase input end of comparator U2 is connected with the cathode output end of reference voltage source V3,
The cathode output end of reference voltage source V3 is grounded, by the inverting input of comparator U2 and prime output voltage sampling circuit
(5) output end connection；By two inputs of two input nand gate U3 respectively with the output end and comparator U2 of comparator U1
Output end connection, the output end of two input nand gate U3 is connected with the grid of NMOS tube Q2, the drain electrode of NMOS tube Q2 is drawn
Go out wire, as the output end of ON-OFF control circuit (6), by the source ground of NMOS tube Q2；
Step 605, connection prime output filtering and accumulator (3)：By one end of electric capacity C1 and the output end of on-off circuit (2)
Connection, the other end of electric capacity C1 is grounded；
The PMOS Q1 of step 7, the suitable parameters of selection composition voltage-regulating circuit (9)：Choose pressure voltage and be more than VD, max's
PMOS model as PMOS Q1, wherein, VD, maxIt is the maximum output voltage of the pre- mu balanced circuit of prime (1)；
The error amplifier X1 and reference voltage source V3 of step 8, the suitable parameters of selection composition error amplifying circuit (8), its tool
Body process is as follows：
Step 801, selection open-loop voltage gain are not less than 70dB, and error amplifier model of the bandwidth not less than 100kHz is used as by mistake
Difference amplifier X1；
Step 802, selection can export the reference voltage source model of 1.235V reference voltages source V3 as the reference voltage；
Step 9, according to formulaChoose composition prime output voltage sampling circuit (5) resistance R4 and
The resistance of resistance R5；Wherein, V3 is the output voltage of reference voltage source V3；
Step 10, connection voltage-regulating circuit (9), secondary output voltage sample circuit (7) and error amplifying circuit (8), composition
Secondary LDO circuit (10), its detailed process is as follows：
Step 1001, connection voltage-regulating circuit (9)：By the drain electrode extraction wire of PMOS Q1, as voltage-regulating circuit (9)
Voltage input end；By the grid extraction wire of PMOS Q1, as the control signal input of voltage-regulating circuit (9)；Will
The drain electrode extraction wire of PMOS Q1, as the output end of voltage-regulating circuit (9)；
Step 1002, connection secondary output voltage sample circuit (7)：Resistance R4 and resistance R5 are connected, and by the electricity after series connection
The one end for hindering R4 and resistance R5 is connected with the output end of voltage-regulating circuit (9), by the another of the resistance R6 after series connection and resistance R7
One end is grounded, by the connection end extraction wire of resistance R4 and resistance R5, as the output of secondary output voltage sample circuit (7)
End；
Step 1003, connection error amplifying circuit (8)：The in-phase input end of error amplifier X1 and secondary output voltage are sampled
The output end connection of circuit (7), the inverting input of error amplifier X1 is connected with the cathode output end of reference voltage source V4,
The cathode output end of reference voltage source V4 is grounded, by the control of the output end of error amplifier X1 and voltage-regulating circuit (9)
Signal input part is connected；
Step 11, the connection pre- mu balanced circuit of prime (1) and secondary LDO circuit (10), constitute the steady voltage regulator circuit of two-stage, its tool
Body process is：The voltage input end of voltage-regulating circuit (9) is connected with the output end of on-off circuit (2).
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| CN106712516B (en) | 2023-12-19 |
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