CN106712516B - Two-stage voltage stabilizing and regulating circuit, voltage stabilizing method and design method thereof - Google Patents
Two-stage voltage stabilizing and regulating circuit, voltage stabilizing method and design method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Abstract
The invention discloses a two-stage voltage stabilizing and regulating circuit, a voltage stabilizing method and a design method thereof, wherein the two-stage voltage stabilizing and regulating circuit comprises a front-stage pre-stabilizing circuit and a secondary LDO circuit, the front-stage pre-stabilizing circuit comprises a switch circuit and a switch control circuit, the voltage input end of the switch circuit is connected with a front-stage input voltage sampling circuit, the output end of the switch circuit is connected with a front-stage output filtering and energy storage circuit, and the input end of the front-stage output filtering and energy storage circuit is connected with a front-stage output voltage sampling circuit; the secondary LDO circuit comprises a voltage adjusting circuit, a secondary output voltage sampling circuit and an error amplifying circuit which are connected in sequence; the voltage stabilizing method comprises the following steps: 1. the pre-voltage stabilizing circuit of the front stage pre-voltage stabilizes the half sine wave voltage of the mains supply which is rectified by the rectifying circuit and output to the pre-voltage stabilizing circuit; 2. the secondary LDO circuit further stabilizes the voltage output by the pre-stage pre-stabilizing circuit. The circuit has the advantages of simple structure, low power consumption, low cost, small ripple, high stability and high reliability.
Description
Technical Field
The invention belongs to the technical field of power supplies, and particularly relates to a two-stage voltage stabilizing and regulating circuit, a voltage stabilizing method and a design method thereof.
Background
In the field of information with high development speed, the power supply technology occupies more and more important positions, and the power supply technology is superior to the advanced computer, wireless communication equipment and automobile electronic products, so that the power supply technology has become a hot spot in the development of the current integrated circuit industry. Nowadays, electronic products designed based on power supply technology are popularized in all aspects of people's work and life, the cost performance is higher and more, the functions are stronger and the market competition is stronger and more.
Power supplies for electronic devices today have become an integral part, and with the increasing optimization of power supply performance, power management techniques have escaped the approach that has been often integrated into application processors in the past, and as an important technical development, various types of power supply products have gradually been produced. The conventional power supply products cannot meet the equipment requirements, and the power supply products are developing towards high efficiency, miniaturization and high stability.
With the advent of the electronic information age, new technology and technology have continuously advanced the development of integrated circuits, especially VLSI technology, which greatly improves the application of analog circuits, digital-analog hybrid circuits and the like in electronic products, not only reduces the manufacturing cost of electronic products, but also promotes the popularization of the application of electronic products. The single chip microcomputer has the advantages of high reliability, small volume, strong control function and the like, and is widely applied to control systems in the fields of industrial control, household appliances, communication equipment and the like.
The power supply for supplying power to the singlechip adopts two general system design schemes: the first solution is to use an isolating switch converter. Converting mains supply into a voltage range required by an electronic circuit by using a power frequency transformer, converting alternating voltage converted by the transformer into unidirectional pulsating direct current voltage by using a rectifying circuit, smoothing pulsating direct current output by the rectifying circuit by using a filtering circuit to obtain direct current voltage with small ripple components, realizing AC-DC conversion, and finally supplying power to a load by using a DC-DC converter; another solution is to use a switching power supply topology. The scheme firstly completes AC-DC conversion, alternating current is converted into direct current voltage with certain voltage ripple through a rectifying circuit, then the ripple is filtered by a filtering circuit, and finally the load is supplied with power through a switching converter. The power frequency transformer has large volume and high cost; and the switch converter has more peripheral elements, so that the power supply is large in size. Therefore, with the above mains supply scheme, the power supply product tends to be bulky.
The direct current stabilized power supply is mainly divided into a switching power supply and a linear power supply according to the working mode of a power tube. The switching regulator is a discrete system, the power tube in the switching regulator works in a high-frequency switching state, the on-resistance is small, when a larger current flows, the power consumed on the power tube is small, the power efficiency is high and can reach more than 85 percent, and the switching regulator is also called as a high-efficiency energy-saving power supply in some cases, and is a main stream product of the regulator. However, the large switching noise is a fatal disadvantage, and greatly limits the application in the fields of low noise, low ripple analog and radio frequency. The linear voltage stabilizer is a continuous system with low efficiency, large heat productivity of the power tube and smaller output than input, but has the advantages of good linear adjustment rate, load adjustment rate, high power supply rejection ratio, low noise and the like, and can just make up the defects of the switch-type voltage stabilizer. In addition, linear voltage regulators are widely used in electronic devices with high noise and ripple requirements because of their low ripple voltage.
Linear regulated power supplies have the following outstanding advantages over other power supplies: when the output current is smaller, the cost of the linear voltage stabilizer is lower; the linear voltage stabilizer is packaged very suitable for being applied to portable electronic equipment, such as wireless telephones, palm computers and the like; the peripheral circuit is simple, and the whole power supply scheme can be formed by only 2-3 small capacitors; the ultra-low output voltage noise is very suitable for a power supply circuit of an audio circuit sensitive to noise; meanwhile, no electromagnetic interference (EMI) caused by large current change when the switch is turned on or off is generated, so that the design is convenient. As such, linear regulators are widely used in portable electronic devices such as mobile phones. For example, a cell phone may contain up to 10 LDOs (low dropout regulator, low dropout linear regulators) as power sources for internal digital and analog modules, and thus the demand for LDOs is high.
The technology of LDO low dropout linear regulators is already quite mature in abroad. For example, some well known foreign semiconductor manufacturers such as TI, infram semiconductor, messaging, international Rectifier (IR), intersil, etc. have a range of relatively complete LDO products. The market of LDO low-dropout linear voltage regulator which uses triode NPN and PNP as power regulator is gradually shrinking; instead, the LDO low dropout linear voltage regulator using a PMOS field effect transistor as a power regulator gradually occupies the market. For these two types of linear power supply chips, the main difference is the voltage drop Vdropout, where the voltage drop is explained as follows, the output voltage of the LDO linear regulator chip gradually increases with the increase of the input voltage, and when the input voltage increases to a value where the output voltage is basically maintained at a constant value, the difference between the constant output voltage Vout and the minimum input voltage Vin corresponding to the value is the voltage drop Vdropout. In general, we design an LDO chip with good performance, where an important index for measuring the performance is to make the power loss on the internal circuit of the system less possible during normal operation, and the efficiency of the chip is higher. The voltage drop required by the linear stabilized power supply taking NPN and PNP as the power adjusting tube is relatively large, and the working efficiency is relatively low. The LDO linear voltage regulator using PMOS field effect transistor as the power regulator has low voltage drop Vdropout and low power consumption, so that the application of P-type field effect transistor as the power regulator occupies a large market, and other linear voltage regulator chips such as BCD technology are also under development. Along with the rapid development of the LDO linear voltage regulator chip, the performance requirement on the LDO linear voltage regulator chip is higher and higher, and the current market demand and development trend of the LDO linear voltage regulator chip can be summarized as the following points: (1) reducing cost and volume; (2) reducing power consumption; (3) providing a diversified output voltage; (4) shortening the design cycle.
Low dropout linear voltage regulator (LDO) is receiving general attention of people because of its small size, high power supply rejection ratio, low power consumption, low noise, and simple application circuit. In addition, the LDO has better transient response performance, so that the LDO has important roles in the fields of portability, industrialization, automobile industry and the like, and is widely applied to electronic equipment such as PDAs, MP3 players, wireless phones, DDRs and the like. Therefore, the design of the LDO becomes a research hotspot in the technical field of the current power supply, and has important theoretical significance and practical application value. In particular, the integrated voltage stabilizer without a transformer can save inductance components occupying larger system area relative to a switching power supply, has simple peripheral circuits, and has the advantages of small volume, low cost, small ripple, high stability and the like.
Because the traditional integrated voltage stabilizer needs to be externally connected with a power frequency transformer with larger volume in practical application, the inductor and the transformer are not easy to integrate in a power chip, and the occupied chip area is larger, so that the application of the integrated voltage stabilizer is influenced; most of the traditional linear voltage regulators are realized by adopting bipolar devices, in particular to an adjusting tube, the bipolar devices belong to current control devices, and when a load is driven, large base electrode control current is required, so that the power consumption of a circuit is increased; in addition, the existing LDO circuit has the defects of low efficiency, incapability of too large input-output voltage difference, too large energy consumption on the LDO if voltage drop is too large, low efficiency and the like.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the two-stage voltage stabilizing and regulating circuit which has the advantages of simple circuit structure, low power consumption, low cost, small ripple, high stability, high reliability, strong practicability, good using effect and better popularization and application value.
In order to solve the technical problems, the invention adopts the following technical scheme: a two-stage voltage stabilizing and regulating circuit is characterized in that: the switching circuit comprises a pre-stage pre-voltage stabilizing circuit and a secondary LDO circuit, wherein the pre-stage pre-voltage stabilizing circuit comprises a switching circuit and a switching control circuit, the voltage input end of the switching circuit is the input end VIN of the two-stage voltage stabilizing and regulating circuit, the voltage input end of the switching circuit is connected with a pre-stage input voltage sampling circuit, the output end of the switching circuit is connected with a pre-stage output filtering and energy storage circuit, the input end of the pre-stage output filtering and energy storage circuit is connected with a pre-stage output voltage sampling circuit, the output end of the pre-stage input voltage sampling circuit and the output end of the pre-stage output voltage sampling circuit are both connected with the input end of the switching control circuit, and the switching control signal input end of the switching circuit is connected with the output end of the switching control circuit; the secondary LDO circuit comprises a voltage adjusting circuit, a secondary output voltage sampling circuit and an error amplifying circuit which are sequentially connected, wherein the voltage input end of the voltage adjusting circuit is connected with the output end of the switching circuit, the control signal input end of the voltage adjusting circuit is connected with the output end of the error amplifying circuit, and the output end of the voltage adjusting circuit is the output end VOUT of the two-stage voltage stabilizing adjusting circuit.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the switching circuit comprises an NMOS tube Q3 and a resistor R9, wherein the drain electrode of the NMOS tube Q3 is connected with one end of the resistor R9 and is a voltage input end of the switching circuit, the grid electrode of the NMOS tube Q3 is connected with the other end of the resistor R9 and is a switching control signal input end of the switching circuit, and the source electrode of the NMOS tube Q3 is an output end of the switching circuit.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the model of the NMOS tube Q3 is IRF431.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the switch control circuit comprises a comparator U1, a comparator U2, a two-input NAND gate U3, a reference voltage source V1, a reference voltage source V2 and an NMOS tube Q2, wherein the non-inverting input end of the comparator U1 is connected with the positive output end of the reference voltage source V1, the negative output end of the reference voltage source V1 is grounded, and the inverting input end of the comparator U1 is a first input end of the switch control circuit and is connected with the output end of the front-stage input voltage sampling circuit; the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U2 is a second input end of the switch control circuit and is connected with the output end of the front-stage output voltage sampling circuit; two input ends of the two-input NAND gate U3 are respectively connected with the output end of the comparator U1 and the output end of the comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of the NMOS tube Q2, the drain electrode of the NMOS tube Q2 is the output end of the switch control circuit, and the source electrode of the NMOS tube Q2 is grounded.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the model of the comparator U1 and the model of the comparator U2 are both LM393, the model of the two-input NAND gate U3 is CD4011, the model of the NMOS tube Q2 is IRF720A, and the model of the reference voltage source V1 and the model of the reference voltage source V2 are both LM4140.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the front-stage input voltage sampling circuit comprises a resistor R1 and a resistor R2 which are connected in series, one ends of the resistor R1 and the resistor R2 which are connected in series are connected with the voltage input end of the switch circuit, the other ends of the resistor R1 and the resistor R2 which are connected in series are grounded, and the connecting end of the resistor R1 and the resistor R2 is the output end of the front-stage input voltage sampling circuit; the front-stage output voltage sampling circuit comprises a resistor R6 and a resistor R7 which are connected in series, one ends of the resistor R6 and the resistor R7 which are connected in series are connected with the input end of the front-stage output filter and energy storage circuit, the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connection end of the resistor R6 and the resistor R7 is the output end of the front-stage output voltage sampling circuit; the front-stage output filter and energy storage circuit comprises a capacitor C1, one end of the capacitor C1 is the input end of the front-stage output filter and energy storage circuit and is connected with the output end of the switch circuit, and the other end of the capacitor C1 is grounded.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the voltage regulation circuit comprises a PMOS tube Q1, wherein the source electrode of the PMOS tube Q1 is a voltage input end of the voltage regulation circuit, the grid electrode of the PMOS tube Q1 is a control signal input end of the voltage regulation circuit, and the drain electrode of the PMOS tube Q1 is an output end of the voltage regulation circuit; the secondary output voltage sampling circuit comprises a resistor R4 and a resistor R5 which are connected in series, one ends of the resistor R4 and the resistor R5 which are connected in series are connected with the output end of the voltage regulating circuit, the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connection end of the resistor R4 and the resistor R5 is the output end of the secondary output voltage sampling circuit; the error amplifying circuit comprises an error amplifier X1 and a reference voltage source V3, wherein the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit, the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V3, the negative output end of the reference voltage source V3 is grounded, and the output end of the error amplifier X1 is the output end of the error amplifying circuit and is connected with the control signal input end of the voltage regulating circuit.
The two-stage voltage stabilizing and adjusting circuit is characterized in that: the model of the PMOS tube Q1 is IRF720A, the model of the error amplifier X1 is LM358, and the model of the reference voltage source V3 is LM385.
The invention also provides a voltage stabilizing method of the two-stage voltage stabilizing and regulating circuit, which has the advantages of simple steps, reasonable design and convenient realization, and is characterized by comprising the following steps:
step A, a pre-stabilizing circuit pre-stabilizes half sine wave voltage of the mains supply, which is rectified by a rectifying circuit and is output to the pre-stabilizing circuit: the half sine wave rising section of the output voltage of the rectifying circuit is gradually increased from zero, and when the voltage of the voltage input end of the switching circuit is increased to enable the switching circuit to be conducted, the switching circuit is conducted, and the front-stage output filtering and energy storage circuit starts to store energy; meanwhile, the front-stage input voltage sampling circuit detects the voltage of the voltage input end of the switching circuit in real time and outputs the detected voltage to the switching control circuit, the switching control circuit compares the voltage detected by the front-stage input voltage sampling circuit with the first turn-off threshold voltage of the preset NMOS tube Q3, when the voltage detected by the front-stage input voltage sampling circuit is larger than the first turn-off threshold voltage of the preset NMOS tube Q3 along with the further increase of the voltage input end of the switching circuit, the switching control circuit controls the switching circuit to be turned off, the front-stage output filter and energy storage circuit discharges, and the output voltage is supplied to the secondary LDO circuit; the output voltage of the rectifying circuit is increased to a peak value and then enters a half sine wave falling section, the voltage is gradually reduced from the peak value, when the voltage detected by the front-stage input voltage sampling circuit is larger than a first turn-off threshold voltage of a preset NMOS tube Q3, the switching circuit is always in a turn-off state, meanwhile, the front-stage output voltage sampling circuit detects the input and output end voltages of the front-stage output filter and the energy storage circuit in real time and outputs the detected voltage to the switching control circuit, and the switching control circuit compares the voltage detected by the front-stage output voltage sampling circuit with a second turn-off threshold voltage of the preset NMOS tube Q3; along with the further reduction of the voltage input end of the switching circuit, when the voltage detected by the front-stage input voltage sampling circuit is smaller than the first turn-off threshold voltage of the preset NMOS tube Q3 and the voltage detected by the front-stage output voltage sampling circuit is larger than the second turn-off threshold voltage of the preset NMOS tube Q3, the switching circuit is still turned off, the front-stage output filtering and energy storage circuit continues to discharge, and the output voltage is supplied to the secondary LDO circuit; along with the further reduction of the voltage input end of the switching circuit, when the voltage detected by the front-stage output voltage sampling circuit is smaller than the second turn-off threshold voltage of the preset NMOS tube Q3, the switching control circuit controls the switching circuit to be turned on, the front-stage output filtering and energy storage circuit starts energy storage again, and meanwhile, the voltage is output to the secondary LDO circuit; when the voltage of the voltage input end of the switching circuit is reduced to be insufficient for the switching circuit to be conducted, the switching circuit is turned off, the front-stage output filter and the energy storage circuit discharge, and the output voltage is supplied to the secondary LDO circuit until a half sine wave rising section of the next period of the output voltage of the rectifying circuit; the first turn-off threshold voltage of the NMOS tube Q3 is the turn-off threshold voltage of the switch control circuit for controlling the turn-off of the NMOS tube Q3 according to the sampling voltage of the previous stage input voltage sampling circuit; the second turn-off threshold voltage of the NMOS tube Q3 is the turn-off threshold voltage of the switch control circuit for controlling the turn-off of the NMOS tube Q3 according to the sampling voltage of the front-stage output voltage sampling circuit;
Step B, the secondary LDO circuit further stabilizes the voltage output by the pre-stage pre-stabilizing circuit to the secondary LDO circuit: when the voltage output by the pre-voltage stabilizing circuit of the front stage has a trend of reducing, so that the voltage output by the secondary LDO circuit has a trend of reducing, the voltage detected by the secondary output voltage sampling circuit is reduced, the voltage output by the error amplifying circuit is also reduced, and when the voltage output by the error amplifying circuit is detected by the voltage adjusting circuit to be reduced, the current flowing through the voltage adjusting circuit is adjusted to be increased, so that the voltage output by the secondary LDO circuit is increased, and the stability of the voltage output by the secondary LDO circuit is ensured; when the voltage output by the pre-voltage stabilizing circuit of the front stage has an increasing trend, and the voltage output by the secondary LDO circuit has an increasing trend, the voltage detected by the secondary output voltage sampling circuit is increased, the voltage output by the error amplifying circuit is also increased, and when the voltage output by the error amplifying circuit is detected by the voltage adjusting circuit, the current flowing through the voltage adjusting circuit is adjusted to be reduced, so that the voltage output by the secondary LDO circuit is reduced, and the stability of the voltage output by the secondary LDO circuit is ensured.
The invention also discloses a design method of the two-stage voltage-stabilizing regulating circuit, which has the advantages of simple steps, reasonable design, convenient implementation and capability of designing the two-stage voltage-stabilizing regulating circuit stably and reliably, and is characterized by comprising the following steps:
Step one, selecting an NMOS tube Q3 and a resistor R9 which form proper parameters of a switching circuit, wherein the specific process is as follows:
step 101, selecting an NMOS tube Q3, which specifically comprises the following steps:
step 1011, according to formula V Q3,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q3 Q3,max Wherein V is in,max The maximum input voltage of the two-stage voltage stabilizing and regulating circuit is obtained;
step 1012, selecting a withstand voltage value greater than V Q3,max The NMOS tube model of (2) is used as an NMOS tube Q3;
102, selecting the resistance value of the resistor R9 according to 1k omega < R9 < 100k omega;
step two, a comparator U1, a comparator U2, a two-input NAND gate U3, a reference voltage source V1, a reference voltage source V2 and an NMOS tube Q2 which form proper parameters of the switching circuit are selected, and the specific process is as follows:
step 201, selecting a comparator model with a single power supply, a power supply voltage of 5V and a transmission delay of not more than 250ns as a comparator U1 and a comparator U2;
step 202, selecting any type of two-input NAND gate as a two-input NAND gate U3;
step 203, selecting an NMOS transistor Q2, which specifically includes:
step 2031, according to formula V Q2,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q2 Q2,max Wherein V is in,max The maximum input voltage of the two-stage voltage stabilizing and regulating circuit is obtained;
step 2032, selecting a withstand voltage value greater than V Q2,max The NMOS tube model of (2) is used as an NMOS tube Q2;
step 204, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V1;
step 205, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V2;
step three, according to the formulaSelecting resistance values of a resistor R1 and a resistor R2 forming a front-stage input voltage sampling circuit; wherein V1 is the output voltage of the reference voltage source V1, V Q3 The switching control circuit is used for controlling the turn-off threshold voltage of the turn-off of the NMOS tube Q3 according to the sampling voltage of the previous stage input voltage sampling circuit;
step four, according to the formulaSelecting resistance values of a resistor R6 and a resistor R7 forming a front-stage output voltage sampling circuit; wherein V2 is the output voltage of the reference voltage source V2, V C1 The switching control circuit is used for controlling the turn-off threshold voltage of the turn-off of the NMOS tube Q3 according to the sampling voltage of the front-stage output voltage sampling circuit;
step five, according to the formulaSelecting the capacitance value of a capacitor C1 forming a front-stage output filter and an energy storage circuit; wherein I is load The current is the rated current of the load, T is the period of an alternating current power supply, and DeltaV is the ripple wave of the output voltage of the pre-stage pre-stabilizing circuit;
step six, connecting a switching circuit, a switching control circuit, a front-stage input voltage sampling circuit, a front-stage output voltage sampling circuit and a front-stage output filtering and energy storage circuit to form a front-stage pre-voltage stabilizing circuit, wherein the specific process is as follows:
Step 601, connecting a switching circuit: the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R9, and a lead is led out and used as a voltage input end of a switch circuit; the grid electrode of the NMOS tube Q3 is connected with the other end of the resistor R9, a lead is led out and used as a switch control signal input end of the switch circuit, and the source electrode of the NMOS tube Q3 is led out and used as an output end of the switch circuit;
step 602, connecting a front-stage input voltage sampling circuit: the method comprises the steps of connecting a resistor R1 and a resistor R2 in series, connecting one ends of the resistor R1 and the resistor R2 which are connected in series with a voltage input end of a switching circuit, grounding the other ends of the resistor R1 and the resistor R2 which are connected in series, and leading out a lead from the connecting end of the resistor R1 and the resistor R2 to serve as an output end of a front-stage input voltage sampling circuit;
step 603, connecting a front stage output voltage sampling circuit: the resistor R6 and the resistor R7 are connected in series, one end of the resistor R6 and one end of the resistor R7 which are connected in series are connected with the input end of the front-stage output filter and energy storage circuit, the other end of the resistor R6 and the other end of the resistor R7 which are connected in series are grounded, and the connecting end of the resistor R6 and the connecting end of the resistor R7 are led out of a wire to serve as the output end of the front-stage output voltage sampling circuit;
step 604, connect the switch control circuit: the non-inverting input end of the comparator U1 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U1 is connected with the output end of the front-stage input voltage sampling circuit; the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V3, the negative electrode output end of the reference voltage source V3 is grounded, and the inverting input end of the comparator U2 is connected with the output end of the front-stage output voltage sampling circuit; two input ends of a two-input NAND gate U3 are respectively connected with the output end of a comparator U1 and the output end of a comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of an NMOS tube Q2, a lead is led out from the drain electrode of the NMOS tube Q2 and used as the output end of a switch control circuit, and the source electrode of the NMOS tube Q2 is grounded;
Step 605, connect the output filter and the energy storage circuit of the front stage: one end of a capacitor C1 is connected with the output end of the switch circuit, and the other end of the capacitor C1 is grounded;
step seven, selecting a PMOS tube Q1 with proper parameters for forming a voltage regulating circuit: selecting the voltage withstand value to be larger than V D，max The PMOS tube model is taken as a PMOS tube Q1, wherein V D，max The maximum output voltage of the pre-voltage stabilizing circuit at the front stage is obtained;
step eight, selecting an error amplifier X1 and a reference voltage source V3 which form proper parameters of the error amplifying circuit, wherein the specific process is as follows:
step 801, selecting an error amplifier model with open-loop voltage gain not smaller than 70dB and bandwidth not smaller than 100kHz as an error amplifier X1;
step 802, selecting a reference voltage source model capable of outputting 1.235V reference voltage as a reference voltage source V3;
step nine, according to the formulaSelecting resistance values of a resistor R4 and a resistor R5 which form a front-stage output voltage sampling circuit; wherein V3 is the output voltage of the reference voltage source V3;
step ten, connect voltage regulation circuit, secondary output voltage sampling circuit and error amplification circuit, form the secondary LDO circuit, its concrete process is as follows:
step 1001, a connection voltage adjustment circuit: the drain electrode of the PMOS tube Q1 is led out of a lead and used as a voltage input end of a voltage regulating circuit; the grid electrode of the PMOS tube Q1 is led out of a wire and used as a control signal input end of a voltage adjusting circuit; the drain electrode of the PMOS tube Q1 is led out of a lead and used as the output end of the voltage regulating circuit;
Step 1002, connecting a secondary output voltage sampling circuit: connecting a resistor R4 and a resistor R5 in series, connecting one ends of the resistor R4 and the resistor R5 which are connected in series with the output end of the voltage regulating circuit, grounding the other ends of the resistor R6 and the resistor R7 which are connected in series, and leading out a lead from the connecting end of the resistor R4 and the resistor R5 to serve as the output end of the secondary output voltage sampling circuit;
step 1003, connect error amplification circuit: the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit, the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V4, the negative output end of the reference voltage source V4 is grounded, and the output end of the error amplifier X1 is connected with the control signal input end of the voltage regulating circuit;
step eleven, connect the pre-stage pre-voltage stabilizing circuit and secondary LDO circuit, form the two-stage voltage stabilizing regulating circuit, its concrete process is: the voltage input end of the voltage regulating circuit is connected with the output end of the switching circuit.
Compared with the prior art, the technology of the invention has the following advantages:
1. the two-stage voltage stabilizing and regulating circuit has the advantages of simple circuit structure, reasonable design, convenient realization and low cost.
2. When the two-stage voltage stabilizing and regulating circuit is used, the rectified mains supply can be directly connected without a transformer and an inductor, and the circuit is convenient to integrate.
3. The two-stage voltage-stabilizing regulating circuit adopts the NMOS tube and the PMOS tube, and can realize low power consumption of the integrated voltage stabilizer when the integrated voltage stabilizer is manufactured.
4. According to the two-stage voltage stabilizing and regulating circuit, a direct-current voltage with ripple waves is output through the pre-voltage stabilizing circuit, and the output voltage is regulated through the secondary LDO circuit, so that the output voltage is more reliable and stable.
5. The voltage stabilizing method of the two-stage voltage stabilizing and regulating circuit has the advantages of simple steps, reasonable design and convenient realization.
6. The design method of the two-stage voltage stabilizing and regulating circuit has the advantages of simple steps, reasonable design and convenient realization, and can design a stable and reliable two-stage LDO circuit.
7. The invention has strong practicability, good use effect and better popularization and application value.
In conclusion, the circuit disclosed by the invention has the advantages of simple structure, low power consumption, low cost, small ripple, high stability, high reliability, strong practicability, good use effect and better popularization and application values.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
Fig. 1 is a schematic block diagram of a two-stage voltage regulator circuit of the present invention.
Fig. 2 is a schematic circuit diagram of a two-stage voltage regulation circuit according to the present invention.
FIG. 3 is a flow chart of a voltage stabilizing method of the two-stage voltage stabilizing and regulating circuit.
FIG. 4 is a flow chart of a method for designing a two-stage voltage stabilizing and regulating circuit according to the present invention.
Reference numerals illustrate:
1-a pre-stage pre-voltage stabilizing circuit; 2-a switching circuit; 3-a front stage output filter and energy storage circuit;
4-a front stage input voltage sampling circuit; 5-a front-stage output voltage sampling circuit;
6-a switch control circuit; 7-a secondary output voltage sampling circuit;
8-an error amplifying circuit; 9-a voltage adjustment circuit; 10-secondary LDO circuit.
Detailed Description
As shown in fig. 1, the two-stage voltage regulation circuit of the present invention comprises a pre-stage pre-voltage regulation circuit 1 and a secondary LDO circuit 10, wherein the pre-stage pre-voltage regulation circuit 1 comprises a switch circuit 2 and a switch control circuit 6, the voltage input end of the switch circuit 2 is the input end VIN of the two-stage voltage regulation circuit, the voltage input end of the switch circuit 2 is connected with a pre-stage input voltage sampling circuit 4, the output end of the switch circuit 2 is connected with a pre-stage output filtering and energy storage circuit 3, the input end of the pre-stage output filtering and energy storage circuit 3 is connected with a pre-stage output voltage sampling circuit 5, the output end of the pre-stage input voltage sampling circuit 4 and the output end of the pre-stage output voltage sampling circuit 5 are both connected with the input end of the switch control circuit 6, and the switch control signal input end of the switch circuit 2 is connected with the output end of the switch control circuit 6; the secondary LDO circuit 10 comprises a voltage adjusting circuit 9, a secondary output voltage sampling circuit 7 and an error amplifying circuit 8 which are sequentially connected, wherein the voltage input end of the voltage adjusting circuit 9 is connected with the output end of the switch circuit 2, the control signal input end of the voltage adjusting circuit 9 is connected with the output end of the error amplifying circuit 8, and the output end of the voltage adjusting circuit 9 is the output end VOUT of the two-stage voltage stabilizing adjusting circuit.
In specific implementation, the input voltage (obtained by rectifying the commercial power through the rectifying circuit) is stabilized by the pre-stage pre-stabilizing circuit 1, and then the output voltage is stabilized by the secondary LDO circuit 10.
As shown in fig. 2, in this embodiment, the switch circuit 2 includes an NMOS transistor Q3 and a resistor R9, a drain of the NMOS transistor Q3 is connected to one end of the resistor R9 and is a voltage input end of the switch circuit 2, a gate of the NMOS transistor Q3 is connected to the other end of the resistor R9 and is a switch control signal input end of the switch circuit 2, and a source of the NMOS transistor Q3 is an output end of the switch circuit 2.
In this embodiment, the model of the NMOS Q3 is IRF431.
As shown in fig. 2, in this embodiment, the switch control circuit 6 includes a comparator U1, a comparator U2, a two-input nand gate U3, a reference voltage source V1, a reference voltage source V2, and an NMOS transistor Q2, where a non-inverting input terminal of the comparator U1 is connected to an positive output terminal of the reference voltage source V1, a negative output terminal of the reference voltage source V1 is grounded, and an inverting input terminal of the comparator U1 is a first input terminal of the switch control circuit 6 and is connected to an output terminal of the preceding-stage input voltage sampling circuit 4; the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U2 is a second input end of the switch control circuit 6 and is connected with the output end of the front-stage output voltage sampling circuit 5; two input ends of the two-input NAND gate U3 are respectively connected with the output end of the comparator U1 and the output end of the comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of the NMOS tube Q2, the drain electrode of the NMOS tube Q2 is the output end of the switch control circuit 6, and the source electrode of the NMOS tube Q2 is grounded.
In this embodiment, the types of the comparator U1 and the comparator U2 are LM393, the type of the two-input nand gate U3 is CD4011, the type of the NMOS Q2 is IRF720A, and the types of the reference voltage source V1 and the reference voltage source V2 are LM4140.
In this embodiment, as shown in fig. 2, the front-stage input voltage sampling circuit 4 includes a resistor R1 and a resistor R2 connected in series, one ends of the resistor R1 and the resistor R2 connected in series are connected to the voltage input end of the switch circuit 2, the other ends of the resistor R1 and the resistor R2 connected in series are grounded, and the connection end of the resistor R1 and the resistor R2 is the output end of the front-stage input voltage sampling circuit 4. The front-stage output voltage sampling circuit 5 comprises a resistor R6 and a resistor R7 which are connected in series, one ends of the resistor R6 and the resistor R7 which are connected in series are connected with the input end of the front-stage output filtering and energy storage circuit 3, the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connecting end of the resistor R6 and the resistor R7 is the output end of the front-stage output voltage sampling circuit 5. The front-stage output filter and energy storage circuit 3 comprises a capacitor C1, one end of the capacitor C1 is the input end of the front-stage output filter and energy storage circuit 3 and is connected with the output end of the switch circuit 2, and the other end of the capacitor C1 is grounded.
As shown in fig. 2, in this embodiment, the voltage adjusting circuit 9 includes a PMOS transistor Q1, a source of the PMOS transistor Q1 is a voltage input terminal of the voltage adjusting circuit 9, a gate of the PMOS transistor Q1 is a control signal input terminal of the voltage adjusting circuit 9, and a drain of the PMOS transistor Q1 is an output terminal of the voltage adjusting circuit 9. The secondary output voltage sampling circuit 7 comprises a resistor R4 and a resistor R5 which are connected in series, one ends of the resistor R4 and the resistor R5 which are connected in series are connected with the output end of the voltage regulating circuit 9, the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connecting end of the resistor R4 and the resistor R5 is the output end of the secondary output voltage sampling circuit 7. The error amplifying circuit 8 comprises an error amplifier X1 and a reference voltage source V3, wherein the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit 7, the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V3, the negative output end of the reference voltage source V3 is grounded, and the output end of the error amplifier X1 is the output end of the error amplifying circuit 8 and is connected with the control signal input end of the voltage regulating circuit 9.
In this embodiment, the PMOS transistor Q1 is IRF720A, the error amplifier X1 is LM358, and the reference voltage source V3 is LM385.
As shown in fig. 3, the voltage stabilizing method of the two-stage voltage stabilizing and adjusting circuit of the invention comprises the following steps:
step A, a pre-stabilizing circuit 1 pre-stabilizes half sine wave voltage of commercial power which is rectified by a rectifying circuit and is output to the commercial power: when the voltage of the voltage input end of the switch circuit 2 is increased to the voltage capable of enabling the switch circuit 2 to be conducted, the switch circuit 2 is conducted, and the front-stage output filtering and energy storage circuit 3 starts to store energy; meanwhile, the front-stage input voltage sampling circuit 4 detects the voltage of the voltage input end of the switch circuit 2 in real time and outputs the detected voltage to the switch control circuit 6, the switch control circuit 6 compares the voltage detected by the front-stage input voltage sampling circuit 4 with the first turn-off threshold voltage of the preset NMOS tube Q3, when the voltage detected by the front-stage input voltage sampling circuit 4 is larger than the first turn-off threshold voltage of the preset NMOS tube Q3 along with further increase of the voltage input end of the switch circuit 2, the switch control circuit 6 controls the switch circuit 2 to turn off, the front-stage output filter and energy storage circuit 3 discharges, and the output voltage is supplied to the secondary LDO circuit 10; the output voltage of the rectifying circuit is increased to a peak value and then enters a half sine wave falling section, the voltage is gradually reduced from the peak value, when the voltage detected by the front-stage input voltage sampling circuit 4 is larger than a first turn-off threshold voltage of a preset NMOS tube Q3, the switching circuit 2 is always in a turn-off state, meanwhile, the front-stage output voltage sampling circuit 5 detects the input and output end voltage of the front-stage output filtering and energy storage circuit 3 in real time and outputs the detected voltage to the switching control circuit 6, and the switching control circuit 6 compares the voltage detected by the front-stage output voltage sampling circuit 5 with a second turn-off threshold voltage of the preset NMOS tube Q3; along with the further decrease of the voltage input end voltage of the switch circuit 2, when the voltage detected by the front-stage input voltage sampling circuit 4 is smaller than the first turn-off threshold voltage of the preset NMOS tube Q3 and the voltage detected by the front-stage output voltage sampling circuit 5 is larger than the second turn-off threshold voltage of the preset NMOS tube Q3, the switch circuit 2 is still turned off, the front-stage output filtering and energy storage circuit 3 continues to discharge, and the output voltage is supplied to the secondary LDO circuit 10; as the voltage at the voltage input end of the switch circuit 2 is further reduced, when the voltage detected by the output voltage sampling circuit 5 at the front stage is smaller than the second turn-off threshold voltage of the preset NMOS Q3, the switch control circuit 6 controls the switch circuit 2 to be turned on, the output filtering and energy storage circuit 3 at the front stage starts energy storage again, and simultaneously outputs the voltage to the secondary LDO circuit 10; when the voltage of the voltage input end of the switching circuit 2 is reduced to be insufficient for the switching circuit 2 to be conducted, the switching circuit 2 is turned off, the front-stage output filter and energy storage circuit 3 discharges, and the output voltage is supplied to the secondary LDO circuit 10 until the half sine wave rising section of the next period of the output voltage of the rectifying circuit; the first turn-off threshold voltage of the NMOS transistor Q3 is a turn-off threshold voltage of the switch control circuit 6 for controlling the turn-off of the NMOS transistor Q3 according to the sampled voltage of the previous stage input voltage sampling circuit 4; the second turn-off threshold voltage of the NMOS transistor Q3 is a turn-off threshold voltage of the switch control circuit 6 for controlling the turn-off of the NMOS transistor Q3 according to the sampled voltage of the previous output voltage sampling circuit 5;
The specific process of the step A is as follows, in combination with specific circuits: when the voltage of the voltage input end of the switching circuit 2 is increased to a value which enables the gate-source voltage of the NMOS tube Q3 to be larger than the conduction threshold voltage of the NMOS tube Q3, the NMOS tube Q3 is conducted, and the capacitor C1 starts to store energy; meanwhile, the front-stage input voltage sampling circuit 4 detects the voltage of the voltage input end of the switch circuit 2 in real time and outputs the detected voltage to the switch control circuit 6, the comparator U1 in the switch control circuit 6 compares the voltage detected by the front-stage input voltage sampling circuit 4 with the reference voltage provided by the reference voltage source V1, when the voltage detected by the front-stage input voltage sampling circuit 4 is larger than the reference voltage provided by the reference voltage source V1 along with further increase of the voltage input end of the switch circuit 2, the comparator U1 outputs a low level, the two-input NAND gate U3 outputs a high level, the NMOS tube Q2 is conducted, the NMOS tube Q3 is turned off, the capacitor C1 discharges, and the output voltage is provided to the secondary LDO circuit 10; the output voltage of the rectifying circuit is increased to a peak value and then enters a half sine wave falling section, the voltage is gradually reduced from the peak value, when the voltage detected by the front-stage input voltage sampling circuit 4 is larger than the reference voltage provided by the reference voltage source V1, the NMOS tube Q3 is always in an off state, meanwhile, the front-stage output voltage sampling circuit 5 detects the input and output end voltage of the front-stage output filter and energy storage circuit 3 in real time and outputs the detected voltage to the switch control circuit 6, and the comparator U2 in the switch control circuit 6 compares the voltage detected by the front-stage output voltage sampling circuit 5 with the reference voltage provided by the reference voltage source V2; along with the further decrease of the voltage at the voltage input end of the switch circuit 2, when the voltage detected by the front-stage input voltage sampling circuit 4 is smaller than the reference voltage provided by the reference voltage source V1 and the voltage detected by the front-stage output voltage sampling circuit 5 is greater than the reference voltage provided by the reference voltage source V2, the comparator U1 outputs a high level, the comparator U2 outputs a low level, the two-input nand gate U3 outputs a high level, the NMOS tube Q2 is turned on, the NMOS tube Q3 is still turned off, the capacitor C1 continues to discharge, and the output voltage is provided to the secondary LDO circuit 10; along with the further decrease of the voltage at the voltage input end of the switch circuit 2, when the voltage detected by the output voltage sampling circuit 5 at the front stage is smaller than the reference voltage provided by the reference voltage source V2, the comparator U2 outputs a high level, the two-input nand gate U3 outputs a low level, the NMOS tube Q2 is turned off, the NMOS tube Q3 is turned on, the capacitor C1 begins to store energy again, and meanwhile, the voltage is output to the secondary LDO circuit 10; when the voltage of the voltage input end of the switching circuit 2 is reduced to enable the gate-source voltage of the NMOS tube Q3 to be smaller than the conduction threshold voltage of the NMOS tube Q3, the NMOS tube Q3 is turned off, the capacitor C1 discharges, and the output voltage is supplied to the secondary LDO circuit 10 until a half sine wave rising section of the next period of the output voltage of the rectifying circuit;
The pre-stage pre-stabilizing circuit 1 continuously samples and controls the switch tube Q3 to be turned on or off, the capacitor C1 is charged and discharged periodically, and finally the voltage output by the pre-stage pre-stabilizing circuit 1 is stabilized in a range set by the reference voltage source V1 and the reference voltage source V2.
Step B, the secondary LDO circuit 10 further stabilizes the voltage output to it by the pre-stage pre-stabilizing circuit 1: when the voltage output by the pre-voltage stabilizing circuit 1 of the front stage has a trend of reducing, so that the voltage output by the secondary LDO circuit 10 has a trend of reducing, the voltage detected by the secondary output voltage sampling circuit 7 is reduced, the voltage output by the error amplifying circuit 8 is also reduced, and when the voltage detected by the voltage adjusting circuit 9 is reduced, the current flowing through the voltage adjusting circuit 9 is adjusted to be increased, so that the voltage output by the secondary LDO circuit 10 is increased, and the stability of the voltage output by the secondary LDO circuit 10 is ensured; when the voltage output by the pre-voltage stabilizing circuit 1 of the front stage has a trend of increasing, so that the voltage output by the secondary LDO circuit 10 has a trend of increasing, the voltage detected by the secondary output voltage sampling circuit 7 increases, the voltage output by the error amplifying circuit 8 also increases, and when the voltage output by the error amplifying circuit 8 is detected by the voltage adjusting circuit 9, the current flowing through the voltage adjusting circuit 9 is adjusted to be reduced, so that the voltage output by the secondary LDO circuit 10 is reduced, and the stability of the voltage output by the secondary LDO circuit 10 is ensured.
The specific process of the step B is as follows, in combination with specific circuits: when the voltage output by the pre-voltage stabilizing circuit 1 at the front stage has a trend of decreasing, so that the voltage output by the secondary LDO circuit 10 has a trend of decreasing, the voltage detected by the secondary output voltage sampling circuit 7 decreases, the voltage output by the error amplifier X1 also decreases (namely, the voltage adjustment circuit 9 detects the decrease of the voltage output by the error amplifier X1), the gate-source voltage of the PMOS tube Q1 increases, the current flowing through the PMOS tube Q1 increases, the voltage output by the secondary LDO circuit 10 increases, and the stability of the voltage output by the secondary LDO circuit 10 is ensured; when the voltage output by the pre-voltage stabilizing circuit 1 of the front stage has a trend of increasing, so that the voltage output by the secondary LDO circuit 10 has a trend of increasing, the voltage detected by the secondary output voltage sampling circuit 7 increases, the voltage output by the error amplifier X1 also increases (namely, the voltage output by the error amplifier X1 is detected by the voltage adjusting circuit 9), the gate-source voltage of the PMOS tube Q1 decreases, the current flowing through the PMOS tube Q1 decreases, the voltage output by the secondary LDO circuit 10 decreases, and the stability of the output voltage of the secondary LDO circuit 10 is ensured.
As shown in fig. 4, the design method of the two-stage voltage stabilizing and regulating circuit of the invention comprises the following steps:
Step one, selecting an NMOS transistor Q3 and a resistor R9 that form appropriate parameters of the switching circuit 2, and specifically includes the following steps:
step 101, selecting an NMOS tube Q3, which specifically comprises the following steps:
step 1011, according to formula V Q3,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q3 Q3,max Wherein V is in,max For the maximum of the two-stage voltage stabilizing and regulating circuitAn input voltage;
in the present embodiment, V in,max ＝375V，V Q3,max ＝375V；
Step 1012, selecting a withstand voltage value greater than V Q3,max The NMOS tube model of (2) is used as an NMOS tube Q3;
in this embodiment, the model of the NMOS transistor Q3 is IRF431;
102, selecting the resistance value of the resistor R9 according to 1k omega < R9 < 100k omega;
in this embodiment, the resistance of the resistor R9 is selected to be 10kΩ; the resistor R9 provides driving voltage for the grid electrode of the NMOS tube Q3;
step two, a comparator U1, a comparator U2, a two-input nand gate U3, a reference voltage source V1, a reference voltage source V2 and an NMOS transistor Q2, which select suitable parameters constituting the switching circuit 2, the specific process is as follows:
step 201, selecting a comparator model with a single power supply, a power supply voltage of 5V and a transmission delay of not more than 250ns as a comparator U1 and a comparator U2;
in this embodiment, the models of the comparator U1 and the comparator U2 are LM393;
step 202, selecting any type of two-input NAND gate as a two-input NAND gate U3;
In this embodiment, the model of the two-input nand gate U3 is CD4011;
step 203, selecting an NMOS transistor Q2, which specifically includes:
step 2031, according to formula V Q2,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q2 Q2,max Wherein V is in,max The maximum input voltage of the two-stage voltage stabilizing and regulating circuit is obtained;
in the present embodiment, V in,max ＝375V，V Q2,max ＝375V；
Step 2032, selecting a withstand voltage value greater than V Q2,max The NMOS tube model of (2) is used as an NMOS tube Q2;
in this embodiment, the model of the NMOS transistor Q2 is IRF720A;
step 204, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V1;
in this embodiment, the model of the reference voltage source V1 is LM4140;
step 205, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V2;
in this embodiment, the model of the reference voltage source V2 is LM4140;
step three, according to the formulaSelecting resistance values of a resistor R1 and a resistor R2 which form a front-stage input voltage sampling circuit 4; wherein V1 is the output voltage of the reference voltage source V1, V Q3 The switch control circuit 6 samples the turn-off threshold voltage of the turn-off of the voltage control NMOS tube Q3 according to the previous stage input voltage sampling circuit 4;
in this embodiment, v1=2v, V Q3 =35v, selecting the resistance of resistor R1 to be 15kΩ, and selecting the resistance of resistor R2 to be 1kΩ;
In particular, after the NMOS transistor Q3 is selected, it is turned on with a threshold voltage V Q3 It is determined; the resistance values of the resistor R1 and the resistor R2 are as large as possible, so that the power consumption of the resistor R1 and the resistor R2 is reduced;
step four, according to the formulaSelecting resistance values of a resistor R6 and a resistor R7 forming the front-stage output voltage sampling circuit 5; wherein V2 is the output voltage of the reference voltage source V2, V C1 The turn-off threshold voltage for the switch control circuit 6 to control the turn-off of the NMOS transistor Q3 according to the sampling voltage of the front-stage output voltage sampling circuit 5 is also the voltage at two ends of the capacitor C1;
in this embodiment, v2=2v, V C1 =14v, the resistance of resistor R6 is selected to be 12kΩ, and the resistance of resistor R7 is selected to be 2kΩ;
in specific implementation, the threshold voltage for controlling the turn-off of the NMOS transistor Q3 is a set value according to actual needs; the resistance values of the resistor R6 and the resistor R7 are as large as possible, so that the power consumption of the resistor R6 and the resistor R7 is reduced;
step five, according to the formulaSelecting the capacitance value of a capacitor C1 forming the front-stage output filter and energy storage circuit 3; wherein I is load The rated current of the load is T is the period of an alternating current power supply, and DeltaV is the ripple wave of the output voltage of the pre-stage pre-stabilizing circuit 1;
in the present embodiment, I load =50ma, t=20ms, Δv=1.5v, and the capacitance value of the capacitor C1 is 330 μf;
In particular implementation, the rated current I of the load load And ripple DeltaV of the output voltage of the pre-stage pre-voltage stabilizing circuit 1 is a set value according to actual needs; the value of DeltaV is generally between 1V and 2V;
step six, connect the switching circuit 2, switch control circuit 6, preceding stage input voltage sampling circuit 4, preceding stage output voltage sampling circuit 5 and preceding stage output filter and energy storage circuit 3, form preceding stage pre-voltage stabilizing circuit 1, its concrete process is as follows:
step 601, connecting the switching circuit 2: the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R9, and a lead is led out and used as a voltage input end of the switch circuit 2; the grid electrode of the NMOS tube Q3 is connected with the other end of the resistor R9, a lead is led out and used as a switch control signal input end of the switch circuit 2, and the source electrode of the NMOS tube Q3 is led out and used as an output end of the switch circuit 2;
step 602, connect the input voltage sampling circuit 4 of the previous stage: the resistor R1 and the resistor R2 are connected in series, one ends of the resistor R1 and the resistor R2 which are connected in series are connected with the voltage input end of the switch circuit 2, the other ends of the resistor R1 and the resistor R2 which are connected in series are grounded, and the connecting ends of the resistor R1 and the resistor R2 are led out of a wire to serve as the output end of the front-stage input voltage sampling circuit 4;
Step 603, connecting the front stage output voltage sampling circuit 5: the resistor R6 and the resistor R7 are connected in series, one end of the resistor R6 and one end of the resistor R7 which are connected in series are connected with the input end of the front-stage output filtering and energy storage circuit 3, the other end of the resistor R6 and the other end of the resistor R7 which are connected in series are grounded, and the connecting end of the resistor R6 and the connecting end of the resistor R7 are led out of a wire to serve as the output end of the front-stage output voltage sampling circuit 5;
step 604, connect switch control circuit 6: the non-inverting input end of the comparator U1 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U1 is connected with the output end of the front-stage input voltage sampling circuit 4; the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V3, the negative electrode output end of the reference voltage source V3 is grounded, and the inverting input end of the comparator U2 is connected with the output end of the front-stage output voltage sampling circuit 5; two input ends of a two-input NAND gate U3 are respectively connected with the output end of a comparator U1 and the output end of a comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of an NMOS tube Q2, a lead is led out from the drain electrode of the NMOS tube Q2 and used as the output end of a switch control circuit 6, and the source electrode of the NMOS tube Q2 is grounded;
Step 605, connect the output filter and the energy storage circuit 3 of the previous stage: one end of a capacitor C1 is connected with the output end of the switch circuit 2, and the other end of the capacitor C1 is grounded;
step seven, selecting a PMOS transistor Q1 with proper parameters for forming the voltage adjusting circuit 9: selecting the voltage withstand value to be larger than V D，max The PMOS tube model is taken as a PMOS tube Q1, wherein V D，max Is the maximum output voltage of the pre-voltage stabilizing circuit 1 of the front stage;
in the present embodiment, V D，max =14v; the model of the PMOS tube Q1 is 2N7002;
in particular, the output voltage V of the pre-stage pre-stabilizing circuit 1 D And the output voltage V of the two-stage voltage stabilizing and regulating circuit OUT Is a set value according to actual needs;
step eight, selecting an error amplifier X1 and a reference voltage source V3 which form appropriate parameters of the error amplifying circuit 8, and specifically comprises the following steps:
step 801, selecting an error amplifier model with open-loop voltage gain not smaller than 70dB and bandwidth not smaller than 100kHz as an error amplifier X1;
in this embodiment, the model of the error amplifier X1 is LM358;
step 802, selecting a reference voltage source model capable of outputting 1.235V reference voltage as a reference voltage source V3;
in this embodiment, the model of the reference voltage source V3 is LM385;
step nine, according to the formula Selecting resistance values of a resistor R4 and a resistor R5 which form a front-stage output voltage sampling circuit 5; wherein V3 is the output voltage of the reference voltage source V3;
in this embodiment, v3=1.235V, V OUT =12v, the resistance of resistor R4 is selected to be 9.1kΩ, and the resistance of resistor R5 is 1kΩ;
in the implementation, the resistance values of the resistor R4 and the resistor R5 are as large as possible, so that the power consumption of the resistor R4 and the resistor R5 is reduced;
step ten, connect voltage regulation circuit 9, secondary output voltage sampling circuit 7 and error amplification circuit 8, form secondary LDO circuit 10, its concrete process is as follows:
step 1001, a connection voltage adjustment circuit 9: the drain electrode of the PMOS tube Q1 is led out of a lead and used as a voltage input end of the voltage regulating circuit 9; the grid of the PMOS tube Q1 is led out of a wire and is used as a control signal input end of the voltage adjusting circuit 9; the drain electrode of the PMOS tube Q1 is led out of a lead and used as the output end of the voltage regulating circuit 9;
step 1002, connecting a secondary output voltage sampling circuit 7: the resistor R4 and the resistor R5 are connected in series, one ends of the resistor R4 and the resistor R5 which are connected in series are connected with the output end of the voltage regulating circuit 9, the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connecting ends of the resistor R4 and the resistor R5 are led out of a wire to serve as the output end of the secondary output voltage sampling circuit 7;
Step 1003, connect error amplification circuit 8: the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit 7, the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V4, the negative output end of the reference voltage source V4 is grounded, and the output end of the error amplifier X1 is connected with the control signal input end of the voltage regulating circuit 9;
step eleven, connect the pre-stage pre-voltage stabilizing circuit 1 and the secondary LDO circuit 10, form the two-stage voltage stabilizing regulating circuit, its concrete process is: the voltage input of the voltage regulating circuit 9 is connected to the output of the switching circuit 2.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any simple modification, variation and equivalent structural changes made to the above embodiment according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (7)
1. A two-stage voltage stabilizing and regulating circuit is characterized in that: the switching circuit comprises a pre-stage pre-voltage stabilizing circuit (1) and a secondary LDO circuit (10), wherein the pre-stage pre-voltage stabilizing circuit (1) comprises a switching circuit (2) and a switching control circuit (6), the voltage input end of the switching circuit (2) is the input end VIN of the two-stage voltage stabilizing and regulating circuit, the voltage input end of the switching circuit (2) is connected with a pre-stage input voltage sampling circuit (4), the output end of the switching circuit (2) is connected with a pre-stage output filtering and energy storage circuit (3), the input end of the pre-stage output filtering and energy storage circuit (3) is connected with a pre-stage output voltage sampling circuit (5), the output end of the pre-stage input voltage sampling circuit (4) and the output end of the pre-stage output voltage sampling circuit (5) are both connected with the input end of the switching control circuit (6), and the switching control signal input end of the switching circuit (2) is connected with the output end of the switching control circuit (6). The secondary LDO circuit (10) comprises a voltage adjusting circuit (9), a secondary output voltage sampling circuit (7) and an error amplifying circuit (8) which are sequentially connected, wherein the voltage input end of the voltage adjusting circuit (9) is connected with the output end of the switch circuit (2), the control signal input end of the voltage adjusting circuit (9) is connected with the output end of the error amplifying circuit (8), and the output end of the voltage adjusting circuit (9) is the output end VOUT of the two-stage voltage stabilizing adjusting circuit;
The switching circuit (2) comprises an NMOS tube Q3 and a resistor R9, wherein the drain electrode of the NMOS tube Q3 is connected with one end of the resistor R9 and is a voltage input end of the switching circuit (2), the grid electrode of the NMOS tube Q3 is connected with the other end of the resistor R9 and is a switching control signal input end of the switching circuit (2), and the source electrode of the NMOS tube Q3 is an output end of the switching circuit (2);
the model of the NMOS tube Q3 is IRF431;
the switch control circuit (6) comprises a comparator U1, a comparator U2, a two-input NAND gate U3, a reference voltage source V1, a reference voltage source V2 and an NMOS tube Q2, wherein the non-inverting input end of the comparator U1 is connected with the positive output end of the reference voltage source V1, the negative output end of the reference voltage source V1 is grounded, and the inverting input end of the comparator U1 is a first input end of the switch control circuit (6) and is connected with the output end of the front-stage input voltage sampling circuit (4); the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U2 is a second input end of the switch control circuit (6) and is connected with the output end of the front-stage output voltage sampling circuit (5); two input ends of the two-input NAND gate U3 are respectively connected with the output end of the comparator U1 and the output end of the comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of the NMOS tube Q2, the drain electrode of the NMOS tube Q2 is the output end of the switch control circuit (6), and the source electrode of the NMOS tube Q2 is grounded.
2. A two-stage regulator circuit according to claim 1, wherein: the model of the comparator U1 and the model of the comparator U2 are both LM393, the model of the two-input NAND gate U3 is CD4011, the model of the NMOS tube Q2 is IRF720A, and the model of the reference voltage source V1 and the model of the reference voltage source V2 are both LM4140.
3. A two-stage regulator circuit according to claim 1, wherein: the front-stage input voltage sampling circuit (4) comprises a resistor R1 and a resistor R2 which are connected in series, one ends of the resistor R1 and the resistor R2 which are connected in series are connected with the voltage input end of the switch circuit (2), the other ends of the resistor R1 and the resistor R2 which are connected in series are grounded, and the connection end of the resistor R1 and the resistor R2 is the output end of the front-stage input voltage sampling circuit (4); the front-stage output voltage sampling circuit (5) comprises a resistor R6 and a resistor R7 which are connected in series, one ends of the resistor R6 and the resistor R7 which are connected in series are connected with the input end of the front-stage output filtering and energy storage circuit (3), the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connection end of the resistor R6 and the resistor R7 is the output end of the front-stage output voltage sampling circuit (5); the front-stage output filter and energy storage circuit (3) comprises a capacitor C1, one end of the capacitor C1 is the input end of the front-stage output filter and energy storage circuit (3) and is connected with the output end of the switch circuit (2), and the other end of the capacitor C1 is grounded.
4. A two-stage regulator circuit according to claim 3, wherein: the voltage regulation circuit (9) comprises a PMOS tube Q1, wherein the source electrode of the PMOS tube Q1 is the voltage input end of the voltage regulation circuit (9), the grid electrode of the PMOS tube Q1 is the control signal input end of the voltage regulation circuit (9), and the drain electrode of the PMOS tube Q1 is the output end of the voltage regulation circuit (9); the secondary output voltage sampling circuit (7) comprises a resistor R4 and a resistor R5 which are connected in series, one ends of the resistor R4 and the resistor R5 which are connected in series are connected with the output end of the voltage regulating circuit (9), the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connection end of the resistor R4 and the resistor R5 is the output end of the secondary output voltage sampling circuit (7); the error amplifying circuit (8) comprises an error amplifier X1 and a reference voltage source V3, wherein the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit (7), the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V3, the negative output end of the reference voltage source V3 is grounded, and the output end of the error amplifier X1 is the output end of the error amplifying circuit (8) and is connected with the control signal input end of the voltage regulating circuit (9).
5. A two-stage regulator circuit according to claim 4, wherein: the model of the PMOS tube Q1 is IRF720A, the model of the error amplifier X1 is LM358, and the model of the reference voltage source V3 is LM385.
6. A voltage stabilizing method of a two-stage voltage stabilizing and regulating circuit according to claim 1, characterized in that the method comprises the steps of:
step A, a pre-stabilizing circuit (1) pre-stabilizes half sine wave voltage of mains supply which is rectified by a rectifying circuit and is output to the pre-stabilizing circuit: when the voltage of the voltage input end of the switching circuit (2) is increased to enable the switching circuit (2) to be conducted, the switching circuit (2) is conducted, and the front-stage output filtering and energy storage circuit (3) starts to store energy; meanwhile, the front-stage input voltage sampling circuit (4) detects the voltage of the voltage input end of the switching circuit (2) in real time and outputs the detected voltage to the switching control circuit (6), the switching control circuit (6) compares the voltage detected by the front-stage input voltage sampling circuit (4) with a first turn-off threshold voltage of a preset NMOS tube Q3, when the voltage of the voltage input end of the switching circuit (2) is further increased, the switching control circuit (6) controls the switching circuit (2) to be turned off, the front-stage output filter and the energy storage circuit (3) to discharge, the rectifying circuit output voltage is increased to a half sine wave falling section after the peak value, the voltage is gradually reduced from the peak value, when the voltage detected by the front-stage input voltage sampling circuit (4) is higher than the first turn-off threshold voltage of the preset NMOS tube Q3, the switching circuit (2) is always in a turn-off state, and simultaneously, the front-stage output voltage sampling circuit (5) controls the front-stage output voltage sampling circuit (4) to be turned off and the voltage detected by the switching control circuit (6) to output the switching control circuit (6) to the second turn-off threshold voltage of the switching circuit (6) after the voltage detected by the front-stage input voltage sampling circuit (4) is increased to the first turn-off threshold voltage of the preset NMOS tube Q3; along with the voltage of the voltage input end of the switch circuit (2) is further reduced, when the voltage detected by the front-stage input voltage sampling circuit (4) is smaller than the first turn-off threshold voltage of the preset NMOS tube Q3 and the voltage detected by the front-stage output voltage sampling circuit (5) is larger than the second turn-off threshold voltage of the preset NMOS tube Q3, the switch circuit (2) is still turned off, the front-stage output filtering and energy storage circuit (3) continues to discharge, and the output voltage is supplied to the secondary LDO circuit (10); along with the voltage of the voltage input end of the switching circuit (2) is further reduced, when the voltage detected by the front-stage output voltage sampling circuit (5) is smaller than the second turn-off threshold voltage of the preset NMOS tube Q3, the switching control circuit (6) controls the switching circuit (2) to be turned on, the front-stage output filtering and energy storage circuit (3) starts energy storage again, and meanwhile, the voltage is output to the secondary LDO circuit (10); when the voltage of the voltage input end of the switching circuit (2) is reduced to be insufficient for the switching circuit (2) to be conducted, the switching circuit (2) is turned off, the front-stage output filter and energy storage circuit (3) discharges, and the output voltage is supplied to the secondary LDO circuit (10) until the half sine wave rising section of the next period of the output voltage of the rectifying circuit; the first turn-off threshold voltage of the NMOS tube Q3 is the turn-off threshold voltage of the switch control circuit (6) for controlling the turn-off of the NMOS tube Q3 according to the sampling voltage of the previous-stage input voltage sampling circuit (4); the second turn-off threshold voltage of the NMOS tube Q3 is the turn-off threshold voltage of the switch control circuit (6) for controlling the turn-off of the NMOS tube Q3 according to the sampling voltage of the front-stage output voltage sampling circuit (5);
Step B, the secondary LDO circuit (10) further stabilizes the voltage output by the pre-stage pre-stabilizing circuit (1): when the voltage output by the pre-voltage stabilizing circuit (1) of the front stage has a trend of reducing, so that the voltage output by the secondary LDO circuit (10) has a trend of reducing, the voltage detected by the secondary output voltage sampling circuit (7) is reduced, the voltage output by the error amplifying circuit (8) is also reduced, and when the voltage regulating circuit (9) detects that the voltage output by the error amplifying circuit (8) is reduced, the current flowing through the voltage regulating circuit (9) is regulated to be increased, so that the voltage output by the secondary LDO circuit (10) is increased, and the stability of the voltage output by the secondary LDO circuit (10) is ensured; when the voltage output by the pre-voltage stabilizing circuit (1) of the front stage has a trend of increasing, so that the voltage output by the secondary LDO circuit (10) has a trend of increasing, the voltage detected by the secondary output voltage sampling circuit (7) also increases, and when the voltage output by the error amplifying circuit (8) is detected by the voltage adjusting circuit (9), the current flowing through the voltage adjusting circuit (9) is adjusted to be reduced, so that the voltage output by the secondary LDO circuit (10) is reduced, and the stability of the output voltage of the secondary LDO circuit (10) is ensured.
7. A method of designing a two-stage regulator circuit according to claim 4, comprising the steps of:
Step one, selecting an NMOS tube Q3 and a resistor R9 which form proper parameters of a switching circuit (2), wherein the specific process is as follows:
step 101, selecting an NMOS tube Q3, which specifically comprises the following steps:
step 1011, according to formula V Q3,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q3 Q3,max Wherein V is in,max The maximum input voltage of the two-stage voltage stabilizing and regulating circuit is obtained;
step 1012, selecting a withstand voltage value greater than V Q3,max The NMOS tube model of (2) is used as an NMOS tube Q3;
102, selecting the resistance value of the resistor R9 according to 1k omega < R9 < 100k omega;
step two, selecting a comparator U1, a comparator U2, a two-input NAND gate U3, a reference voltage source V1, a reference voltage source V2 and an NMOS tube Q2 which form proper parameters of a switching circuit (2), wherein the specific process is as follows:
step 201, selecting a comparator model with a single power supply, a power supply voltage of 5V and a transmission delay of not more than 250ns as a comparator U1 and a comparator U2;
step 202, selecting any type of two-input NAND gate as a two-input NAND gate U3;
step 203, selecting an NMOS transistor Q2, which specifically includes:
step 2031, according to formula V Q2,max ＝V in,max Calculating the maximum voltage V required to be born by the NMOS tube Q2 Q2,max Wherein V is in,max The maximum input voltage of the two-stage voltage stabilizing and regulating circuit is obtained;
step 2032, selecting a withstand voltage value greater than V Q2,max The NMOS tube model of (2) is used as an NMOS tube Q2;
step 204, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V1;
step 205, selecting a reference voltage source model capable of outputting 2V reference voltage as a reference voltage source V2;
step three, according to the formulaSelecting resistance values of a resistor R1 and a resistor R2 which form a front-stage input voltage sampling circuit (4); wherein V1 is the output voltage of the reference voltage source V1, V Q3 The switch control circuit (6) is used for controlling the turn-off threshold voltage of the turn-off of the NMOS tube Q3 according to the sampling voltage of the previous stage input voltage sampling circuit (4);
step four, according to the formulaSelecting resistance values of a resistor R6 and a resistor R7 which form a front-stage output voltage sampling circuit (5); wherein V2 is the output voltage of the reference voltage source V2, V C1 The switch control circuit (6) is used for controlling the turn-off threshold voltage of the turn-off of the NMOS tube Q3 according to the sampling voltage of the front-stage output voltage sampling circuit (5);
step five, according to the formulaSelecting the capacitance value of a capacitor C1 forming a front-stage output filter and energy storage circuit (3); wherein I is load T is the period of an alternating current power supply, and DeltaV is the ripple of the output voltage of the pre-stage pre-stabilizing circuit (1);
step six, connect the switching circuit (2), switch control circuit (6), preceding stage input voltage sampling circuit (4), preceding stage output voltage sampling circuit (5) and preceding stage output filter and energy storage circuit (3), constitute preceding stage pre-stabilizing circuit (1), its concrete process is as follows:
Step 601, connecting a switching circuit (2): the drain electrode of the NMOS tube Q3 is connected with one end of a resistor R9, and a lead is led out and used as a voltage input end of the switch circuit (2); the grid electrode of the NMOS tube Q3 is connected with the other end of the resistor R9, a lead is led out and used as a switch control signal input end of the switch circuit (2), and the source electrode of the NMOS tube Q3 is led out and used as an output end of the switch circuit (2);
step 602, connecting a front stage input voltage sampling circuit (4): the resistor R1 and the resistor R2 are connected in series, one ends of the resistor R1 and the resistor R2 which are connected in series are connected with the voltage input end of the switch circuit (2), the other ends of the resistor R1 and the resistor R2 which are connected in series are grounded, and the connecting ends of the resistor R1 and the resistor R2 are led out of a wire to serve as the output end of the front-stage input voltage sampling circuit (4);
step 603, connecting the front stage output voltage sampling circuit (5): the resistor R6 and the resistor R7 are connected in series, one end of the resistor R6 and one end of the resistor R7 which are connected in series are connected with the input end of the front-stage output filtering and energy storage circuit (3), the other end of the resistor R6 and the other end of the resistor R7 which are connected in series are grounded, and a lead is led out from the connecting end of the resistor R6 and the resistor R7 to serve as the output end of the front-stage output voltage sampling circuit (5);
Step 604, connect the switch control circuit (6): the non-inverting input end of the comparator U1 is connected with the positive electrode output end of the reference voltage source V2, the negative electrode output end of the reference voltage source V2 is grounded, and the inverting input end of the comparator U1 is connected with the output end of the front-stage input voltage sampling circuit (4); the non-inverting input end of the comparator U2 is connected with the positive electrode output end of the reference voltage source V3, the negative electrode output end of the reference voltage source V3 is grounded, and the inverting input end of the comparator U2 is connected with the output end of the front-stage output voltage sampling circuit (5); two input ends of a two-input NAND gate U3 are respectively connected with the output end of a comparator U1 and the output end of a comparator U2, the output end of the two-input NAND gate U3 is connected with the grid electrode of an NMOS tube Q2, a lead is led out from the drain electrode of the NMOS tube Q2 and used as the output end of a switch control circuit (6), and the source electrode of the NMOS tube Q2 is grounded;
step 605, connect the output filter of the front stage and energy storage circuit (3): one end of a capacitor C1 is connected with the output end of the switch circuit (2), and the other end of the capacitor C1 is grounded;
step seven, selecting a PMOS tube Q1 with proper parameters for forming a voltage regulating circuit (9): selecting the voltage withstand value to be larger than V D，max The PMOS tube model is taken as a PMOS tube Q1, wherein V D，max The maximum output voltage of the pre-voltage stabilizing circuit (1) at the front stage is obtained;
step eight, selecting an error amplifier X1 and a reference voltage source V3 which form proper parameters of an error amplifying circuit (8), wherein the specific process is as follows:
step 801, selecting an error amplifier model with open-loop voltage gain not smaller than 70dB and bandwidth not smaller than 100kHz as an error amplifier X1;
step 802, selecting a reference voltage source model capable of outputting 1.235V reference voltage as a reference voltage source V3;
step nine, according to the formulaSelecting resistance values of a resistor R4 and a resistor R5 which form a front-stage output voltage sampling circuit (5); wherein V3 is the output voltage of the reference voltage source V3;
step ten, connect voltage regulation circuit (9), secondary output voltage sampling circuit (7) and error amplification circuit (8), constitute secondary LDO circuit (10), its concrete process is as follows:
step 1001, a connection voltage adjustment circuit (9): the drain electrode of the PMOS tube Q1 is led out of a lead and used as a voltage input end of a voltage regulating circuit (9); the grid of the PMOS tube Q1 is led out of a wire and is used as a control signal input end of a voltage adjusting circuit (9); the drain electrode of the PMOS tube Q1 is led out of a lead and used as the output end of a voltage regulating circuit (9);
step 1002, connecting a secondary output voltage sampling circuit (7): the resistor R4 and the resistor R5 are connected in series, one ends of the resistor R4 and the resistor R5 which are connected in series are connected with the output end of the voltage regulating circuit (9), the other ends of the resistor R6 and the resistor R7 which are connected in series are grounded, and the connecting end of the resistor R4 and the resistor R5 is led out of a wire to serve as the output end of the secondary output voltage sampling circuit (7);
Step 1003, connect error amplification circuit (8): the non-inverting input end of the error amplifier X1 is connected with the output end of the secondary output voltage sampling circuit (7), the inverting input end of the error amplifier X1 is connected with the positive output end of the reference voltage source V4, the negative output end of the reference voltage source V4 is grounded, and the output end of the error amplifier X1 is connected with the control signal input end of the voltage regulating circuit (9);
step eleven, connect the pre-stage pre-voltage stabilizing circuit (1) and secondary LDO circuit (10), form the two-stage voltage stabilizing regulating circuit, its concrete process is: the voltage input end of the voltage regulating circuit (9) is connected with the output end of the switching circuit (2).
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