CN106711055B - A kind of hybrid bonded method - Google Patents
A kind of hybrid bonded method Download PDFInfo
- Publication number
- CN106711055B CN106711055B CN201611242099.1A CN201611242099A CN106711055B CN 106711055 B CN106711055 B CN 106711055B CN 201611242099 A CN201611242099 A CN 201611242099A CN 106711055 B CN106711055 B CN 106711055B
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- contact hole
- metal contact
- etch
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 238000005516 engineering process Methods 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 34
- 239000010949 copper Substances 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000003701 mechanical milling Methods 0.000 claims description 6
- 238000010348 incorporation Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 241000416536 Euproctis pseudoconspersa Species 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 15
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 230000003746 surface roughness Effects 0.000 abstract description 4
- 238000013459 approach Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 73
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011863 silicon-based powder Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8002—Applying permanent coating to the bonding area in the bonding apparatus, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8034—Bonding interfaces of the bonding area
- H01L2224/80359—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of hybrid bonded methods, and the process employs etching technics to remove certain thickness dielectric layer, redeposited one layer of organic dielectric layer, and integrally remove the organic dielectric layer on surface until exposing metallic pattern, and then obtain new bonding surface.The bonding technology temperature and metal approach of the organic dielectric layer, bond strength and SiO2、Si3N4Equal inorganic mediums are close, do not need complicated plasma-activated technology and harsh surface roughness requirements, and have certain flowability at high temperature, possess very big bonding technology window, advantageously reduce technique and integrate difficulty, improve product yield.
Description
Technical field
The present invention relates to ic manufacturing technology fields, and in particular to a kind of hybrid bonded method.
Background technique
As ic manufacturing technology enters 45nm and following technology generation, in order to overcome brought by feature size downsizing
Technical problem, industry have generallyd use some new technologies, such as strained silicon engineering, high dielectric constant/metal gates, multiple exposure
Light technology etc., and enter 16nm technology node, traditional two-dimentional cmos device has also turned to three-dimensional FinFET.These
The high investment of cutting edge technology and high risk keep numerous middle-size and small-size Integrated circuit manufacturers outside of the door, in order to seek life, those
The manufacturers being eliminated can only find another way, and a field technology revolution is being fermented.Three dimensional integrated circuits have been acknowledged as
Generation semiconductor technology, it is advantageous that high-performance, low-power consumption, small physical size, high integration density.How to realize vertical
Directly interconnection is the key that three-dimensionally integrated, and core technology is exactly to stack bonding (Stacked Bonding) and through silicon via (TSV).
There are three types of the manufacturing methods for stacking bonding, i.e., chip chamber bonding, chip are bonded between wafer bonding, silicon wafer.Wherein,
Chip-chip bonding is to use most methods at present, and be packaged manufacturer for mass production, although chip-chip bonding
Yield it is high, but scribing and test need to take a lot of time and resource, the manufacturing cost of this method are very high.Chip-silicon wafer
Bonding techniques first can carry out scribing, detection, the chip picked out to the silicon wafer of the relatively low product of yield, then be bonded to yield compared with
On the silicon wafer of high product, a part of processing step is reduced with this, opposite save the cost, this is the WeiLai Technology trend for encapsulating factory.
Silicon wafer-wafer bonding is then suitable for integrated, silicon wafer-wafer bonding maximization production efficiency, letter between the similar product of high yield
Change process flow, minimize cost, but if the yield of silicon wafer is not high or unstable, qualified chip (KGD) quantity will be by
Limitation, and then silicon wafer-wafer bonding qualification rate is influenced, this is the main direction of chip manufacturer, can give full play of technology
The production capacity that generation falls behind.Consider from following mass production application, silicon wafer-wafer bonding and chip-wafer bonding technology will become
Three-dimensionally integrated mainstream solution.
Silicon wafer-wafer bonding needs to realize the physical bond between silicon wafer using silicon wafer grade bonding techniques, or even directly obtains
Obtain the electrical connection between silicon wafer.Silicon wafer grade bonding techniques in three-dimensionally integrated include that bonding is bonded, metal is diffusion interlinked, congruent melting key
It closes, silicon substrate Direct Bonding and hybrid bonded etc., wherein hybrid bonded is emerging technology and most potential high yield, Gao Ke
By the bonding techniques of property.Hybrid bonded (Hybrid bonding) combines metal-metal bonding and dielectric-dielectric bonding, In
While obtaining vertical metal interconnection, the Physical Mechanical between 3D stacked chips is enhanced using the booster action of medium bonding
Energy.It is carried out simultaneously due to being electrically interconnected with micropore media filler, hybrid bonded technology is effectively simplified 3D process flow, and avoids
Characteristic size reduces the filling technique challenge of bring medium micropore, can be applied to bonding technology between highdensity silicon wafer.
Between silicon wafer demanding for integration density for bonding technology, it is contemplated that heat budget problem, it is hybrid bonded to adopt
The low-temperature bonding technique of the biggish medium activation of difficulty is integrated to realize with technique, and uses SiO2、Si3N4Equal inorganic mediums are made
For bonding material.Conventional metal interconnecting layer technique is completed in copper postchannel process, eventually stops at most upper one layer of copper interconnection layer
Cu CMP process, exposure copper and SiO2Then medium is activated surface dielectric by plasma surface activation technology, when two
When piece silicon wafer contacts with each other, stronger physical bond, i.e. cryogenic media bonding technology just occur at normal temperature for surface dielectric, then
Cu-Cu is bonded together by a step high-temperature annealing process and forms electrical connection, the common key of metal and medium is obtained with this
It closes.
But the requirement of the mass of medium on cryogenic media bonding technology para-linkage surface is very high, and in Cu CMP process, silicon
Medium flatness in piece is very good, especially medium (such as SiO2、Si3N4) surface roughness requirements control within 0.5nm,
Ideal medium bonding effect could be obtained, this brings severe challenge to Cu CMP process.In addition, what Cu CMP process occurred
The defects of scuffing, lapping liquid remain problem can all bring fatal empty problem to medium bonding technology, and then it is good to influence product
Rate.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide a kind of low temperature and the hybrid bonded technique of high temperature.
In order to achieve the above object, the present invention provides a kind of hybrid bonded techniques, comprising:
Step 01: a substrate is provided, then using postchannel process formed in the substrate metal contact hole and metal contact hole it
Between dielectric layer；
Step 02: the dielectric layer of etching removal setting thickness makes the surface of metal contact hole be higher by dielectric layer surface；
Step 03: one layer of organic dielectric layer is deposited on the substrate for completing step 02；Wherein, described in organic dielectric layer covering
Metal contact hole；
Step 04: whole removal organic dielectric layer is until expose metal contact hole surface downwards；
Step 05: will be according to the side and the lining with organic dielectric layer of another substrate of step 01~04 preparation
The side with organic dielectric layer at bottom carries out alignment bonding, wherein metal contact hole surface in another substrate with should
Metal contact hole surface in substrate aligns bonding, the organic media layer surface in another substrate with it is organic in the substrate
Dielectric layer surface aligns bonding.
Preferably, in the step 02, the setting is with a thickness of the 20%~50% of dielectric layer overall thickness.
Preferably, the step 03 further include: under inert gas atmosphere, anneal to substrate.
Preferably, in the step 04, using chemical mechanical milling tech or using dry etch process come whole downwards
Removal organic dielectric layer is until expose metal contact hole surface.
Preferably, lapping liquid used by the chemical mechanical milling tech in step 04 is that incorporation granular mass percentage is
The lapping liquid of 1-13%.
Preferably, the dry etch process of step 04 includes the first etch stages and the second etch stages；First etching rank
Section, the organic dielectric layer of first thickness is etched away downwards using the first etch rate；Second etch stages, using the second etching speed
Rate exposes metal contact hole surface after etching away the organic dielectric layer of second thickness downwards；Wherein, the first etch rate is greater than
Second etch rate, first thickness are greater than second thickness.
Preferably, in the first stage, using containing O2Etching gas, gas flow be 500~1000sccm, radio-frequency power
For 200~400W；Second stage uses flow for the C of 30~80sccm4F8, flow be 20~60sccm CO, flow 800
The mixed gas of the Ar of~1600sccm, radio-frequency power are the radio-frequency power of 100~300W.
Preferably, between the step 04 and the step 05 further include: removal metal contact hole surface is damaged
Layers of copper or etch residue.
Preferably, using the metal layer being damaged on chemical mechanical milling tech removal metal contact hole surface, alternatively, adopting
With the etch residue on wet-etching technology removal metal contact hole surface.
Preferably, thermocompression bonding technique is used in the step 05, used temperature is 300~350 DEG C
DEG C, used pressure is 0.5~3MPa, and used heating time is 1.5~3 hours.
Compared with prior art, a kind of hybrid bonded method of the invention uses etching technics and removes certain thickness Jie
Matter layer re-forms one layer of organic dielectric layer, and integrally removal organic dielectric layer surface certain thickness until expose metallic pattern,
And then obtain new bonding surface.The bonding technology temperature and metal approach of the organic dielectric layer, bond strength and SiO2、Si3N4
Equal inorganic mediums are close, do not need complicated plasma-activated technology and harsh surface roughness requirements, and have at high temperature
There is certain flowability, possess very big bonding technology window, advantageously reduces technique and integrate difficulty, improve product yield.
Detailed description of the invention
Fig. 1 is the flow diagram of the hybrid bonded method of a preferred embodiment of the invention
Fig. 2~6 are each step schematic diagram of the hybrid bonded method of a preferred embodiment of the invention
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
Below in conjunction with attached drawing 1~6 and specific embodiment, invention is further described in detail.It should be noted that attached drawing
It is all made of very simplified form, using non-accurate ratio, and only to facilitate, clearly reach aid illustration the present embodiment
Purpose.
Referring to Fig. 1, the hybrid bonded technique of one of the present embodiment includes:
Step 01: referring to Fig. 2, providing a substrate 00, then metal contact hole being formed in substrate 00 using postchannel process
Dielectric layer 01 between 02 and metal contact hole 02；
Specifically, substrate 00 here can use silicon substrate；The material that metal contact hole 02 uses can be copper, step
01 can specifically include: provide a silicon substrate 00, first in 00 surface metallization medium layer 01 of silicon substrate, dielectric layer 02 here is made
For inter-metal medium, it can be pure silicon dioxide, doping silicon dioxide or Low-k medium, can be selected according to different technologies requirement
The medium of suitable k value is selected, and using PECVD technique come metallization medium layer.Then fixed on 01 surface of dielectric layer using photoetching process
Justice goes out the graphics field of metal contact hole 02, can be required here according to different integration densities to select suitable photoetching process, such as
In 65nm and following technology generation, must just use 193nm photoetching technique.And contact hole is obtained using etching technics, it generally first adopts here
Medium is carved layer eating away with dry etch process, then removal of residue and photoresist are gone using wet clean process.Then PVD is used
Technique successively deposits barrier layer and seed layer, and general here first to deposit one layer of very thin Ta (N) barrier layer, redeposited one layer continuous
Copper seed layer.ECP process filling copper is used again, contact hole is filled up into copper here, and provides sufficiently thick copper come after guaranteeing
Continuous CMP process window.Finally the metallic copper on surface is all ground off using the copper CMP technique of standard, obtains the copper of planarization
01 surface of surface and dielectric layer, here it is not strictly necessary that the surface roughness of dielectric layer 01.
Step 02: referring to Fig. 3, the dielectric layer 01 of etching removal setting thickness, is higher by the surface of metal contact hole 02
01 surface of dielectric layer；
Specifically, only needing to remove the dielectric layer 01 on a part of surface layer here, but the etch amount of metal contact hole 02 is wanted
It is considerably less, the selective etch of dielectric layer 01 is first carried out using dry etch process, then using wet clean process removal etching
Residue.Since the etch resistant of the copper and tantalum nitrogen barrier layer that deposit in metal contact hole 02 is very capable, and copper reactant is difficult to
Volatilization, dry etch process are easier to realize that the etching selection ratio of dielectric layer 01 and copper is greater than 50:1.Dry etch process is passed through
The C of 40-100sccm4F8, 30-80sccm CO, 800-1600sccm Ar, control process pressure in 50-150mTorr, radio frequency
Power is 200-500W.Wet clean process for removing etch residue, but the etching extent of copper is answered it is as small as possible, using mark
Quasi- BEOL cleaning process uses the etching of the ST250 cleaning solution removal silicon chip surface of ATMI company under 30~40 DEG C of temperature controls
Residue, preferably 35 DEG C.It is explicitly defined in addition, not made here to 01 etch amount of dielectric layer, 01 etch amount of dielectric layer
It should be determined by the product in different technologies generation, it is known that characteristic size constantly reduces as technology node advances, copper-connection work
The dielectric thickness of skill is also constantly being reduced.For carrying out the metal contact hole 02 of hybrid bonded technique, preferable implementation of the invention
In case, the etch amount (set etch thicknesses) of dielectric layer 01 is controlled between the 20%-50% of 01 thickness of dielectric layer.
Step 03: referring to Fig. 4, depositing organic dielectric layer 03 on the substrate 00 for completing step 02；
Specifically, organic dielectric layer 03 here should have close to SiO2、Si3N4The bond strength of equal inorganic mediums, and after
The continuous bonding technology temperature used must not be higher than 400 DEG C, and the organic polymers such as benzocyclobutene BCB, polyimides PI may be selected
Material as organic dielectric layer.By taking benzocyclobutene (BCB) as an example, BCB be it is a kind of mixed in high molecular material it is a certain amount of
Silicon powder and the polymer that is formed, physical characteristic and inorganic medium are close, the thermal stability that has had, mechanical stability and resist
Acid/base corrosivity, all fine with the matching degree and adhesive force of Si sill, BCB bond strength meets lining up to 20MPa or more
The requirement of bonding techniques between bottom has certain fluidity, can have in addition, BCB will become glassy state under 300 DEG C of temperatures above
Filling pore is imitated, bonding effect between ideal silicon wafer is obtained.Here it is possible to which BCB is flatly sunk using traditional spin coating proceeding
Then under inert gas atmosphere product, anneals to BCB in surface of silicon, such as carry out 200~300 under n 2 atmosphere
DEG C be preferably 250 DEG C at carry out annealing 20~30 minutes, solidify BCB organic media, and has obtained adhesion and physics spy
Property.As shown in figure 4, organic dielectric layer 03 covers metal contact hole 02, and metal contact hole is higher by the top of organic dielectric layer 03
The certain height in 02 top.
Step 04: referring to Fig. 5, whole removal organic dielectric layer 03 is until expose 02 surface of metal contact hole downwards；
Specifically, between step 04 and step 05 further include: the metal layer being damaged on removal 02 surface of metal contact hole
Or etch residue.Organic dielectric layer 03 will be removed below and removes the metal layer being damaged or the quarter on 02 surface of metal contact hole
The process of erosion residue comes together to be described in detail.
Here it is possible to remove organic dielectric layer 03 using chemical mechanical milling tech, used lapping liquid is incorporation
Hydrogen peroxide, and/or the lapping liquid that incorporation granular mass percentage is 1-13%；Firstly, selection chemical mechanical grinding (CMP) technique
Organic dielectric layer 03 is ground, until exposing 02 surface of metal contact hole, the higher incorporation hydrogen peroxide of granule content can be used
Medium milling liquid is ground off the organic dielectric layer 03 on surface by the collective effect of oxidation organic dielectric layer 03 and physical grinding,
CMP process has planarization capability, can efficiently control the flatness of bonding surface, further, CMP process can also be in exposure
The layers of copper being damaged on a part of surface layer is ground off while metal contact hole 02 out, is repaired in step S02 with this to copper surface
Etching injury or reactant residual, these are all conducive to the bonding technology between subsequent silicon substrate.
Further, it is also possible to be connect come whole removal organic dielectric layer 03 downwards until exposing metal using dry etch process
02 surface of contact hole；Then using the etch residue on wet-etching technology removal 02 surface of metal contact hole.Due to organic media
Layer 03 has certain mobility at high temperature, can effective filling pore, thus, it is only required to metal contact hole 02 is exposed,
It is not strictly necessary that the flatness and roughness on 03 surface of organic dielectric layer.
Specifically, dry etch process includes the first etch stages and the second etch stages.
In the first etch stages, the organic dielectric layer 03 of first thickness is etched away downwards using the first etch rate；Second
Etch stages expose metal contact hole 02 after etching away the organic dielectric layer 03 of second thickness downwards using the second etch rate
Surface；The metal surface of metal contact hole 02 is oxidized in order to prevent, so, the first etch rate of use is greater than the second etching
Rate, first thickness are greater than second thickness.Specifically, in the first stage, using containing O2Etching gas quickly by organic media
Layer 03 is whole to be etched down to close to 02 surface of metal contact hole, using containing O2Gas flow is 500~1000sccm, radio frequency function
Rate is 200~400W.Then, in second stage, use flow for the C of 30~80sccm4F8, flow be 20~60sccm CO,
Flow is the mixed gas of the Ar of 800~1600sccm, and radio-frequency power is the radio-frequency power of 100~300W.
After dry etch process, etch residue, etching temperature can be removed using copper-connection wet-etching technology
It is 30~40 DEG C, for example, by using ST250 cleaning solution.
Step 05: referring to Fig. 6, by organic dielectric layer is had according to step 01~04 preparation another substrate 00'
The side of 03' carries out alignment with the side with organic dielectric layer 03 of the substrate 00 and is bonded, wherein another substrate
The surface metal contact hole 02' in 00' is aligned with 02 surface of metal contact hole in the substrate 00 to be bonded, another substrate
The surface organic dielectric layer 03' in 00' is aligned with 03 surface of organic dielectric layer in the substrate 00 to be bonded.
Specifically, using thermocompression bonding technique, used temperature is 300~350 DEG C, used pressure is 0.5~
3MPa, used heating time are 1.5~3 hours.Preferably, temperature used by high annealing is 340 DEG C, it is used
Pressure is 1.2MPa, and used heating time is 2 hours.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
It is non-to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is several more
Dynamic and retouching, the protection scope that the present invention is advocated should be subject to claims.
Claims (10)
1. a kind of hybrid bonded method characterized by comprising
Step 01: a substrate being provided, then forms Jie between metal contact hole and metal contact hole in the substrate with postchannel process
Matter layer；
Step 02: the dielectric layer of etching removal setting thickness makes the surface of metal contact hole be higher by dielectric layer surface；
Step 03: one layer of organic dielectric layer is deposited on the substrate for completing step 02；Wherein, organic dielectric layer covers the metal
Contact hole；
Step 04: whole removal organic dielectric layer surface certain thickness is until expose metal contact hole surface, and then obtain downwards
Obtain bonding surface newly；
Step 05: will be according to the side and the substrate with organic dielectric layer of another substrate of step 01~04 preparation
The side with organic dielectric layer carries out alignment bonding, wherein metal contact hole surface and the substrate in another substrate
In metal contact hole surface align bonding, the organic media in the organic media layer surface in another substrate and the substrate
Layer surface aligns bonding.
2. hybrid bonded method according to claim 1, which is characterized in that in the step 02, it is described setting with a thickness of
The 20%~50% of dielectric layer overall thickness.
3. hybrid bonded method according to claim 1, which is characterized in that the step 03 further include: in inert gas
Under atmosphere, anneal to substrate.
4. hybrid bonded method according to claim 1, which is characterized in that in the step 04, ground using chemical machinery
Grinding process removes organic dielectric layer until exposing metal contact hole surface come whole downwards using dry etch process.
5. hybrid bonded method according to claim 4, which is characterized in that the chemical mechanical milling tech institute in step 04
The lapping liquid that the lapping liquid used is 1-13% for incorporation granular mass percentage.
6. hybrid bonded method according to claim 4, which is characterized in that the dry etch process of step 04 includes first
Etch stages and the second etch stages；First etch stages etch away downwards the organic of first thickness using the first etch rate
Dielectric layer；Second etch stages expose gold after etching away the organic dielectric layer of second thickness downwards using the second etch rate
Belong to contact hole surface；Wherein, the first etch rate is greater than the second etch rate, and first thickness is greater than second thickness.
7. hybrid bonded method according to claim 6, which is characterized in that in the first stage, using containing O2Etching gas
Body, gas flow are 500~1000sccm, and radio-frequency power is 200~400W；Second stage uses flow for 30~80sccm's
C4F8, flow be 20~60sccm CO, flow be 800~1600sccm Ar mixed gas, radio-frequency power be 100~
The radio-frequency power of 300W.
8. hybrid bonded method according to claim 1, which is characterized in that between the step 04 and the step 05 also
It include: the layers of copper being damaged or etch residue for removing metal contact hole surface.
9. hybrid bonded method according to claim 8, which is characterized in that remove metal using chemical mechanical milling tech
The metal layer of hole surface being damaged is contacted, alternatively, using the etching residue on wet-etching technology removal metal contact hole surface
Object.
10. hybrid bonded method according to claim 1, which is characterized in that use thermocompression bonding work in the step 05
Skill, used temperature are 300~350 DEG C, and used pressure is 0.5~3MPa, and used heating time is 1.5~3
Hour.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611242099.1A CN106711055B (en) | 2016-12-29 | 2016-12-29 | A kind of hybrid bonded method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611242099.1A CN106711055B (en) | 2016-12-29 | 2016-12-29 | A kind of hybrid bonded method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106711055A CN106711055A (en) | 2017-05-24 |
| CN106711055B true CN106711055B (en) | 2019-11-22 |
Family
ID=58905912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611242099.1A Active CN106711055B (en) | 2016-12-29 | 2016-12-29 | A kind of hybrid bonded method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106711055B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107871712A (en) * | 2017-10-31 | 2018-04-03 | 中国电子科技集团公司第五十五研究所 | A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource |
| CN109192718B (en) * | 2018-08-28 | 2020-08-25 | 武汉新芯集成电路制造有限公司 | Multi-wafer bonding structure and bonding method |
| CN110060957B (en) * | 2019-04-22 | 2020-07-31 | 长江存储科技有限责任公司 | Semiconductor structure and semiconductor process |
| JP7398475B2 (en) | 2020-01-07 | 2023-12-14 | 長江存儲科技有限責任公司 | Metal dielectric bonding method and structure |
| CN111276469A (en) * | 2020-02-25 | 2020-06-12 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| CN115799184B (en) * | 2023-02-13 | 2023-04-28 | 江西萨瑞半导体技术有限公司 | Semiconductor packaging method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169845A (en) * | 2011-02-22 | 2011-08-31 | 中国科学院微电子研究所 | Multilayer hybrid synchronous bonding structure and method for three-dimensional packaging |
| CN104011848A (en) * | 2010-07-30 | 2014-08-27 | 昆山智拓达电子科技有限公司 | Tsv interconnect structure and manufacturing method thereof |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104167372A (en) * | 2014-08-08 | 2014-11-26 | 武汉新芯集成电路制造有限公司 | Mixed bonding method |
-
2016
- 2016-12-29 CN CN201611242099.1A patent/CN106711055B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104011848A (en) * | 2010-07-30 | 2014-08-27 | 昆山智拓达电子科技有限公司 | Tsv interconnect structure and manufacturing method thereof |
| CN102169845A (en) * | 2011-02-22 | 2011-08-31 | 中国科学院微电子研究所 | Multilayer hybrid synchronous bonding structure and method for three-dimensional packaging |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106711055A (en) | 2017-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106711055B (en) | A kind of hybrid bonded method | |
| US10651086B2 (en) | 3D integration method using SOI substrates and structures produced thereby | |
| CN106571334B (en) | Mixed bonding method between silicon wafers | |
| US8809123B2 (en) | Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers | |
| US8399180B2 (en) | Three dimensional integration with through silicon vias having multiple diameters | |
| US20150054149A1 (en) | Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby | |
| CN107644837A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| TWI645476B (en) | Method for bonding of contact surfaces | |
| WO2008063745A1 (en) | Method of making a contact on a backside of a die | |
| US20120061794A1 (en) | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods | |
| CN102208362B (en) | Preparation method of through-silicon-via back connection end | |
| CN107644838A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107644841A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| WO2012048973A1 (en) | Methods of forming through wafer interconnects in semiconductor structures using sacrificial material, and semiconductor structures formed by such methods | |
| Ko et al. | Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies | |
| Li et al. | 3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO 2-Reconstituted Tiers | |
| CN105448861B (en) | The production method of chip, its production method and stacked die | |
| Lo et al. | 3D chip-to-chip stacking with through silicon interconnects | |
| CN107644836A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| US20240071823A1 (en) | Semiconductor device circuitry formed through volumetric expansion | |
| US20240071970A1 (en) | Semiconductor device with volumetrically-expanded side-connected interconnects | |
| Ohba | Bumpless WOW stacking for large-scale 3D integration | |
| TWI415219B (en) | Method of forming via interconnects for 3-d wafer/chip stacking | |
| CN103730407B (en) | Copper connection wire structure and forming method thereof | |
| TW202412181A (en) | Package structure and bonding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |