TWI415219B - Method of forming via interconnects for 3-d wafer/chip stacking - Google Patents

Method of forming via interconnects for 3-d wafer/chip stacking Download PDF

Info

Publication number
TWI415219B
TWI415219B TW98141072A TW98141072A TWI415219B TW I415219 B TWI415219 B TW I415219B TW 98141072 A TW98141072 A TW 98141072A TW 98141072 A TW98141072 A TW 98141072A TW I415219 B TWI415219 B TW I415219B
Authority
TW
Taiwan
Prior art keywords
mask
performing
bottom
via interconnect
sidewall
Prior art date
Application number
TW98141072A
Other versions
TW201120991A (en
Inventor
Darrell Mcreynolds
Original Assignee
Darrell Mcreynolds
C Sun Mfg Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Darrell Mcreynolds, C Sun Mfg Ltd filed Critical Darrell Mcreynolds
Priority to TW98141072A priority Critical patent/TWI415219B/en
Publication of TW201120991A publication Critical patent/TW201120991A/en
Application granted granted Critical
Publication of TWI415219B publication Critical patent/TWI415219B/en

Links

Abstract

The present invention provides a method of forming via interconnects in a silicon wafer comprising: forming a mask on a substrate; performing an etching step on the mask to form an opening; etching the substrate at the opening to form a via interconnect, the via interconnect has a sidewall, a bottom, and a depth; performing a chemical vapor deposition step with sulfur hexafluoride and oxygen for depositing a insulating oxide layer, the insulating oxide layer covers the sidewall and the bottom of the via interconnect and the mask; performing an ion bombardment gas etching step to etch the insulating oxide layer covered on the bottom of the via interconnect with a ion bombardment gas, the ion bombardment gas comprises at least one of the argon, boron, helium, nitrogen, and fluorocarbon; and performing a physical vapor deposition step to form a conductive material layer, the conductive material layer covers the sidewall and the bottom of the via interconnect and the mask.
TW98141072A 2009-12-01 2009-12-01 Method of forming via interconnects for 3-d wafer/chip stacking TWI415219B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW98141072A TWI415219B (en) 2009-12-01 2009-12-01 Method of forming via interconnects for 3-d wafer/chip stacking

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98141072A TWI415219B (en) 2009-12-01 2009-12-01 Method of forming via interconnects for 3-d wafer/chip stacking

Publications (2)

Publication Number Publication Date
TW201120991A TW201120991A (en) 2011-06-16
TWI415219B true TWI415219B (en) 2013-11-11

Family

ID=45045388

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98141072A TWI415219B (en) 2009-12-01 2009-12-01 Method of forming via interconnects for 3-d wafer/chip stacking

Country Status (1)

Country Link
TW (1) TWI415219B (en)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5658472A (en) * 1995-02-24 1997-08-19 International Business Machines Corporation Method for producing deep vertical structures in silicon substrates
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US20030190814A1 (en) * 1999-12-23 2003-10-09 Applied Materials, Inc. Method of reducing micromasking during plasma etching of a silicon-comprising substrate
US20040072422A1 (en) * 2002-10-09 2004-04-15 Nishant Sinha Methods of forming conductive through-wafer vias
US20060046468A1 (en) * 2004-08-31 2006-03-02 Salman Akram Through-substrate interconnect fabrication methods and resulting structures and assemblies
US20060076664A1 (en) * 2004-10-07 2006-04-13 Chien-Hua Chen 3D interconnect with protruding contacts
US20060180941A1 (en) * 2004-08-31 2006-08-17 Kirby Kyle K Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US20070045858A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US20070128737A1 (en) * 2003-03-14 2007-06-07 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US20070141804A1 (en) * 2004-08-25 2007-06-21 Sankarapillai Chirayarikathuve Method of forming through-wafer interconnects for vertical wafer level packaging
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US20080293240A1 (en) * 2007-05-21 2008-11-27 Fuji Electric Device Technology Co., Ltd. Manufacturing method of a silicon carbide semiconductor device
US20080299762A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method for forming interconnects for 3-D applications
US20100001641A1 (en) * 2008-07-07 2010-01-07 Chul-Hong Kim Substrate structure for plasma display panel, method of manufacturing the substrate structure, and plasma display panel including the substrate structure
US20100084747A1 (en) * 2008-10-03 2010-04-08 Chih-Hua Chen Zigzag Pattern for TSV Copper Adhesion

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5658472A (en) * 1995-02-24 1997-08-19 International Business Machines Corporation Method for producing deep vertical structures in silicon substrates
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US20030190814A1 (en) * 1999-12-23 2003-10-09 Applied Materials, Inc. Method of reducing micromasking during plasma etching of a silicon-comprising substrate
US20040072422A1 (en) * 2002-10-09 2004-04-15 Nishant Sinha Methods of forming conductive through-wafer vias
US20070158853A1 (en) * 2002-10-09 2007-07-12 Micron Technology, Inc. Device with novel conductive via structure
US20070128737A1 (en) * 2003-03-14 2007-06-07 Micron Technology, Inc. Microelectronic devices and methods for packaging microelectronic devices
US20070141804A1 (en) * 2004-08-25 2007-06-21 Sankarapillai Chirayarikathuve Method of forming through-wafer interconnects for vertical wafer level packaging
US20060180941A1 (en) * 2004-08-31 2006-08-17 Kirby Kyle K Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US20060046468A1 (en) * 2004-08-31 2006-03-02 Salman Akram Through-substrate interconnect fabrication methods and resulting structures and assemblies
US20060076664A1 (en) * 2004-10-07 2006-04-13 Chien-Hua Chen 3D interconnect with protruding contacts
US20070045858A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US20080293240A1 (en) * 2007-05-21 2008-11-27 Fuji Electric Device Technology Co., Ltd. Manufacturing method of a silicon carbide semiconductor device
US20080299762A1 (en) * 2007-05-29 2008-12-04 Freescale Semiconductor, Inc. Method for forming interconnects for 3-D applications
US20100001641A1 (en) * 2008-07-07 2010-01-07 Chul-Hong Kim Substrate structure for plasma display panel, method of manufacturing the substrate structure, and plasma display panel including the substrate structure
US20100084747A1 (en) * 2008-10-03 2010-04-08 Chih-Hua Chen Zigzag Pattern for TSV Copper Adhesion

Also Published As

Publication number Publication date
TW201120991A (en) 2011-06-16

Similar Documents

Publication Publication Date Title
US10361201B2 (en) Semiconductor structure and device formed using selective epitaxial process
US20120104512A1 (en) Sealed air gap for semiconductor chip
WO2012102809A3 (en) Polysilicon films by hdp-cvd
CN103098185B (en) Forming a hydrogen-free silicon-containing dielectric film method
WO2010033924A3 (en) Etch reactor suitable for etching high aspect ratio features
TW200915439A (en) Method for fabricating recess gate in semiconductor device
WO2012125317A2 (en) Methods and apparatus for conformal doping
TW201631693A (en) Self-aligned process
TW201332085A (en) Semiconductor modules and methods of forming the same
TW201250814A (en) Hybrid laser and plasma etch wafer dicing using substrate carrier
TW200723440A (en) Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
WO2010009295A3 (en) Hybrid heterojunction solar cell fabrication using a metal layer mask
TW201001618A (en) Semiconductor structure and method for manufacturing the same
TWI232516B (en) Trench isolation without grooving
TW200937519A (en) Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes
TW200636827A (en) Silicon oxide cap over high dielectric constant films
GB2468458A (en) Method of etching a high aspect ratio contact
TW201318057A (en) Combined silicon oxide etch and contamination removal process
TW201630067A (en) Technique to deposit sidewall passivation for high aspect ratio cylinder etch
TW201643955A (en) Technique to deposit sidewall passivation for high aspect ratio cylinder etch
WO2011149616A3 (en) Planarizing etch hardmask to increase pattern density and aspect ratio
WO2003088318A3 (en) Method of fabricating vertical structure leds
WO2008064246A3 (en) Method of clustering sequential processing for a gate stack structure
TW201708592A (en) Method of forming sin thin film on substrate in reaction space
TW201207851A (en) Perpendicular magnetic tunnel junction structure