CN107871712A - A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource - Google Patents
A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource Download PDFInfo
- Publication number
- CN107871712A CN107871712A CN201711047414.XA CN201711047414A CN107871712A CN 107871712 A CN107871712 A CN 107871712A CN 201711047414 A CN201711047414 A CN 201711047414A CN 107871712 A CN107871712 A CN 107871712A
- Authority
- CN
- China
- Prior art keywords
- gallium nitride
- transistor
- bcb
- silicon
- disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
Abstract
The present invention relates to a kind of method of silicon transistor and gallium nitride transistor Manufacturing resource, including：Evaporation/sputtering first interconnects metal on gallium nitride transistor disk；One layer of BCB of spin coating on gallium nitride transistor disk, the interconnection metal of covering first, carries out planarization etching to BCB, exposes the first interconnection metal surface；Evaporation/sputtering second interconnects metal on silicon transistor disk；One layer of BCB of spin coating on silicon transistor disk, the interconnection metal of covering second, carries out planarization etching to BCB, exposes the second interconnection metal surface；Silicon transistor disk is relative with gallium nitride transistor disk front to be bonded；Silicon substrate after para-linkage is ground thinned；Metal is interconnected in silicon substrate perforate filling the 3rd, realizes the Manufacturing resource of silicon transistor and gallium nitride transistor.The present invention realizes that gallium nitride transistor is integrated on same disk with silicon transistor by interconnecting metal micro convex point and method hybrid bonded BCB so that integrated chip volume more minimizes.
Description
Technical field
The invention belongs to semiconductor process technique field, particularly a kind of silicon transistor and gallium nitride transistor Manufacturing resource
Method.
Background technology
Gallium nitride transistor has the advantages that high power, high breakdown, but its integrated level is relatively low, and power consumption is larger.If energy
It is enough that gallium nitride tube device and ripe silicon transistor are integrated on same disk, it is excellent to give full play to both respective performances
Gesture, the impossible performance of any monotechnics is realized, is significant.
Method mainly includes monolithic heterogeneous epitaxial technology and back-off used by realizing transistor level Manufacturing resource at present
Weld Micro-package technique.For monolithic heterogeneous epitaxial technology, if direct heteroepitaxial growth epitaxial layer of gallium nitride on a silicon substrate
If, because silicon from gallium nitride adheres to different material systems separately, there is the problems such as lattice mismatch and thermal mismatching in the two, therefore silicon serves as a contrast
Gallium nitride epitaxial materialses on bottom are second-rate, and the semi-conducting material of heteroepitaxial growth contains very high dislocation density so that
Material property changes, and this have impact on gallium nitride device performance.Back-off weldering Micro-package technique is by gallium nitride die
The form micro convex point that unit is welded by back-off is bonded to the top of silicon transistor, and each dimpling spot size is up to a hundred microns of amounts
Level, and the bond strength of bump bonding is not high, simultaneously because the object of the Integration ofTechnology is chip unit rather than transistor,
Therefore integrated flexibility is not high by larger limitation, integrated level.
In view of the above-mentioned problems, researcher does not find good solution at present, it is low to can only obtain integrated level
Chip-scale integration mode, this severely limits the development of integrated technology.
The content of the invention
It is an object of the invention to provide a kind of method of silicon transistor and gallium nitride transistor Manufacturing resource.
The technical scheme for realizing the object of the invention is：A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource,
Comprise the following steps：
Step 1, gallium nitride transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is got rid of
It is dry；The first interconnection metal is evaporated or sputters in gallium nitride transistor disk surfaces；
Step 2, in one layer of BCB of gallium nitride transistor disk front spin coating, BCB thickness is more than the thickness of the first interconnection metal
Degree, the first interconnection metal is completely covered, and softcure is carried out to BCB；
Step 3, dry planarization etching is carried out to the BCB surfaces on gallium nitride transistor disk using plasma, directly
Expose to the first interconnection metallic upper surface；
Step 4, silicon transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is dried；
Silicon transistor disk surfaces ground evaporation side corresponding with the first interconnection metal sites or the interconnection metal of sputtering second；
Step 5, in one layer of BCB of silicon transistor disk front spin coating, BCB thickness is more than the thickness of the second interconnection metal,
The second interconnection metal is completely covered, and softcure is carried out to BCB；
Step 6, dry planarization etching is carried out to the BCB surfaces on silicon transistor disk using plasma, until the
Expose two interconnection metal surfaces；
Step 7, it is gallium nitride transistor disk is positive relatively and by respective on two disks with silicon transistor disk
Alignment mark carry out pattern alignment, realized in bonding apparatus the first interconnection metal and second interconnection metal it is co-melting bonding and
BCB hot pressing is bonded simultaneously；
Step 8, after para-linkage the silicon substrate of disk be ground by milling apparatus it is thinned；
Step 9, selective etch perforate is carried out on a silicon substrate, exposes the interconnection metal of silicon transistor, what is etched
Sputtering or the interconnection metal of plating the 3rd in through hole, complete the Manufacturing resource of silicon transistor and gallium nitride transistor.
Compared with prior art, remarkable advantage of the invention is：
The present invention interconnects metal with method hybrid bonded BCB to realize gallium nitride transistor and silicon wafer by micron dimension
Body pipe is integrated on same disk, welds micro- assemble method with existing back-off and compares, improves integrated level so that integrated chip
Volume is more minimized, while BCB bondings are added while metal bonding, further increases bond strength.
Brief description of the drawings
Fig. 1 is silicon transistor wafer sample schematic diagram.
Fig. 2 is gallium nitride transistor wafer sample schematic diagram.
Fig. 3 is that selective evaporation/sputtering first interconnects metal schematic diagram on gallium nitride transistor disk.
Fig. 4 is one layer of BCB schematic diagram of spin coating on gallium nitride transistor disk.
Fig. 5 is that planarization etching schematic diagram is carried out to the BCB on gallium nitride transistor disk.
Fig. 6 is that selective evaporation/sputtering second interconnects metal schematic diagram on silicon transistor disk.
Fig. 7 is one layer of BCB schematic diagram of spin coating on silicon transistor disk.
Fig. 8 is that planarization etching schematic diagram is carried out to the BCB on silicon transistor disk.
Fig. 9, which is that silicon transistor disk is relative with gallium nitride transistor disk front, is bonded schematic diagram.
Figure 10 is that thinned schematic diagram is ground to silicon substrate.
Figure 11 is the interconnection metal schematic diagram of silicon substrate perforate filling the 3rd.
Embodiment
A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource, comprises the following steps：
Step 1, gallium nitride transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is got rid of
It is dry；In the selective evaporation of gallium nitride transistor disk surfaces or the interconnection metal of sputtering first, the first interconnection metal thickness is that 2-3 is micro-
Rice, the first interconnection metal is copper or gold；
Step 2, in one layer of BCB of gallium nitride transistor disk front spin coating, BCB thickness is more than the thickness of the first interconnection metal
Degree, the first interconnection metal is completely covered, and 120-140 degrees Celsius of softcure, 1-2 hours softcure time are carried out to BCB；
Step 3, dry planarization etching is carried out to the BCB surfaces on gallium nitride transistor disk using plasma, directly
Expose to the first interconnection metal surface；
Step 4, silicon transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is dried.
The selective evaporation of silicon transistor disk surfaces or the interconnection metal of sputtering second, the second interconnection metal thickness 2-3 microns, the second interconnection
Metal is indium or tin；
Step 5, in one layer of BCB of silicon transistor disk front spin coating, BCB thickness is more than the thickness of the second interconnection metal,
The second interconnection metal is completely covered, and 120-140 degrees Celsius of softcure, 1-2 hours softcure time are carried out to BCB；
Step 6, dry planarization etching is carried out to the BCB surfaces on silicon transistor disk using plasma, until the
Expose two interconnection metal surfaces；
Step 7, by the high transistor disk of gallium nitride and silicon transistor disk front relatively and by respective on two disks
Alignment mark carry out pattern alignment, temperature be 200-250 degrees Celsius under conditions of, the first interconnection is realized in bonding apparatus
Metal and the co-melting bonding of the second interconnection metal and BCB hot pressing are bonded simultaneously；
Step 8, the silicon substrate of disk is ground thinned, the thickness of thinned remaining silicon substrate by milling apparatus after para-linkage
Degree is in 10-20 microns；
Step 9, selective etch perforate is carried out on a silicon substrate, exposes the interconnection metal of silicon transistor, what is etched
Sputtering or the interconnection metal of plating the 3rd in through hole, complete the Manufacturing resource of silicon transistor and gallium nitride transistor.
The technical solution of the present invention is further described with reference to the accompanying drawings and examples.
Embodiment
The method of silicon transistor and gallium nitride transistor Manufacturing resource is as follows in the present embodiment：
(1) silicon transistor disk and gallium nitride transistor disk are cleaned up with acetone, ethanol and deionized water, are put into
Drier is dried.As shown in Figure 1 and Figure 2, the first alignment mark 1 and the second alignment mark 2 are that two disks are aligned in figure
With.
(2) first in gallium nitride transistor disk surfaces spin coating photoresist, then by obtaining selectivity after exposure imaging
Figure, re-evaporation or splash-proofing sputtering metal and peel off, finally obtain the first interconnection metal 3, the first 2 microns of 3 thickness of interconnection metal, the
The material of one interconnection metal 3 is gold, as shown in Figure 3.
(3) in one layer of BCB of gallium nitride transistor disk front spin coating, BCB thickness is more than the thickness of the first interconnection metal 3
Degree, is completely covered the first interconnection metal 3, and disk is put into baking oven and carries out 140 degrees Celsius of softcures, softcure time 1 to BCB
Hour, as shown in Figure 4.
(4) using plasma etch apparatus is carried out to the BCB surfaces on gallium nitride transistor disk dry planarization quarter
Erosion, until the first interconnection metal 3 surface is exposed, as shown in Figure 5.
(5) first in silicon transistor disk surfaces spin coating photoresist, then by obtaining selective figure after exposure imaging,
Re-evaporation or splash-proofing sputtering metal and peel off, finally obtain the second interconnection metal 4, the second 2 microns of 4 thickness of interconnection metal, second is mutual
Connection metal 4 is tin metal material, as shown in Figure 6.
(6) in one layer of BCB of silicon transistor disk front spin coating, BCB thickness is more than the thickness of the second interconnection metal 4, complete
All standing second interconnects metal 4, disk is put into baking oven 140 degrees Celsius of softcures are carried out to BCB, 1 hour softcure time,
As shown in Figure 7.
(7) dry planarization etching is carried out to the BCB surfaces on silicon transistor disk using plasma etch apparatus, directly
Expose to the second interconnection metal 4 surface, as shown in Figure 8.
(8) it is gallium nitride transistor disk and silicon transistor disk front is relative and pass through respective alignment on two disks
Mark alignment, under conditions of temperature is 250 degrees Celsius, the first interconnection metal 3 and the second interconnection gold are realized in bonding apparatus
Belong to 4 co-melting bondings and BCB hot pressing while be bonded, as shown in Figure 9.
(9) silicon substrate of disk is ground thinned by milling apparatus after para-linkage, passes through and remaining silicon substrate is thinned
Thickness control is at 10 microns, as shown in Figure 10.
(10) selective etch perforate is carried out on a silicon substrate, exposes the interconnection metal of silicon transistor, it is logical what is etched
The 3rd interconnection metal 5 is sputtered or electroplated in hole, the Manufacturing resource of silicon transistor and gallium nitride transistor is completed, such as Figure 11 institutes
Show.
By above step, the Manufacturing resource of silicon transistor and gallium nitride transistor is realized.
Claims (9)
1. a kind of method of silicon transistor and gallium nitride transistor Manufacturing resource, it is characterised in that comprise the following steps：
Step 1, gallium nitride transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is dried；
Gallium nitride transistor disk surfaces are evaporated or the interconnection metal of sputtering first；
Step 2, in one layer of BCB of gallium nitride transistor disk front spin coating, BCB thickness is more than the thickness of the first interconnection metal,
The first interconnection metal is completely covered, and softcure is carried out to BCB；
Step 3, dry planarization etching is carried out to the BCB surfaces on gallium nitride transistor disk using plasma, until the
One interconnection metallic upper surface is exposed；
Step 4, silicon transistor disk is cleaned, then is rinsed with deionized water, drier is then placed in and is dried；In silicon wafer
Body pipe disk surfaces ground evaporation side corresponding with the first interconnection metal sites or the interconnection metal of sputtering second；
Step 5, in one layer of BCB of silicon transistor disk front spin coating, BCB thickness is more than the thickness of the second interconnection metal, completely
The interconnection metal of covering second, and softcure is carried out to BCB；
Step 6, dry planarization etching is carried out to the BCB surfaces on silicon transistor disk using plasma, until second mutual
Expose connection metal surface；
Step 7, it is gallium nitride transistor disk and silicon transistor disk front is relative and pass through respective alignment on two disks
Mark carries out pattern alignment, and the first interconnection metal and the co-melting bonding of the second interconnection metal and BCB heat are realized in bonding apparatus
Pressure is bonded simultaneously；
Step 8, after para-linkage the silicon substrate of disk be ground by milling apparatus it is thinned；
Step 9, selective etch perforate is carried out on a silicon substrate, exposes the interconnection metal of silicon transistor, in the through hole etched
Interior sputtering or plating the 3rd interconnection metal, complete the Manufacturing resource of silicon transistor and gallium nitride transistor.
2. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that first
Interconnection metal thickness is 2-3 microns.
3. the method for silicon transistor according to claim 2 and gallium nitride transistor Manufacturing resource, it is characterised in that first
It is copper or gold to interconnect metal.
4. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that step
120-140 degrees Celsius of softcure is carried out to BCB in 2, the softcure time is 1-2 hours.
5. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that second
Interconnection metal thickness is 2-3 microns.
6. the method for silicon transistor according to claim 5 and gallium nitride transistor Manufacturing resource, it is characterised in that second
It is indium or tin to interconnect metal.
7. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that step
120-140 degrees Celsius of softcure is carried out to BCB in 5, the softcure time is 1-2 hours.
8. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that step
In 7 under conditions of temperature is 200-250 degrees Celsius, realize that the first interconnection metal and the second interconnection metal are total in bonding apparatus
Melt bonding and BCB hot pressing while be bonded.
9. the method for silicon transistor according to claim 1 and gallium nitride transistor Manufacturing resource, it is characterised in that step
The thickness of remaining silicon substrate is thinned in 8 to 10-20 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711047414.XA CN107871712A (en) | 2017-10-31 | 2017-10-31 | A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711047414.XA CN107871712A (en) | 2017-10-31 | 2017-10-31 | A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107871712A true CN107871712A (en) | 2018-04-03 |
Family
ID=61753516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711047414.XA Pending CN107871712A (en) | 2017-10-31 | 2017-10-31 | A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107871712A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
| CN112340694A (en) * | 2020-11-03 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465373A (en) * | 2014-10-28 | 2015-03-25 | 中国电子科技集团公司第五十五研究所 | Method for making gallium nitride high electron-mobility transistor on silicon slice |
| CN106409824A (en) * | 2016-09-05 | 2017-02-15 | 中国电子科技集团公司第五十五研究所 | Transistor integration method |
| WO2017052552A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Multi-layer silicon/gallium nitride semiconductor |
| CN106711055A (en) * | 2016-12-29 | 2017-05-24 | 上海集成电路研发中心有限公司 | Mixed bonding method |
| CN107195627A (en) * | 2017-05-12 | 2017-09-22 | 中国电子科技集团公司第五十五研究所 | A kind of gallium nitride transistor and the integrated method of silicon transistor |
-
2017
- 2017-10-31 CN CN201711047414.XA patent/CN107871712A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465373A (en) * | 2014-10-28 | 2015-03-25 | 中国电子科技集团公司第五十五研究所 | Method for making gallium nitride high electron-mobility transistor on silicon slice |
| WO2017052552A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Multi-layer silicon/gallium nitride semiconductor |
| CN106409824A (en) * | 2016-09-05 | 2017-02-15 | 中国电子科技集团公司第五十五研究所 | Transistor integration method |
| CN106711055A (en) * | 2016-12-29 | 2017-05-24 | 上海集成电路研发中心有限公司 | Mixed bonding method |
| CN107195627A (en) * | 2017-05-12 | 2017-09-22 | 中国电子科技集团公司第五十五研究所 | A kind of gallium nitride transistor and the integrated method of silicon transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109243974A (en) * | 2018-08-02 | 2019-01-18 | 中国电子科技集团公司第五十五研究所 | A method of reducing wafer bonding deviation of the alignment |
| CN109406555A (en) * | 2018-10-15 | 2019-03-01 | 上海华力微电子有限公司 | A kind of sample removes hierarchical method |
| CN110600414A (en) * | 2019-08-01 | 2019-12-20 | 中国科学院微电子研究所 | Wafer heterogeneous alignment method and device |
| CN112340694A (en) * | 2020-11-03 | 2021-02-09 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
| CN112340694B (en) * | 2020-11-03 | 2023-05-12 | 中国电子科技集团公司第二十九研究所 | Preparation method of glass micro-channel radiator for gallium nitride power amplifier chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107871712A (en) | A kind of method of silicon transistor and gallium nitride transistor Manufacturing resource | |
| US9837372B1 (en) | Wafer-level die to package and die to die interconnects suspended over integrated heat sinks | |
| CN101656244B (en) | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method | |
| JP4594934B2 (en) | Integrated electronic chip and interconnect device, and method for manufacturing the same | |
| CN102214624B (en) | Semiconductor structure with through holes and manufacturing method thereof | |
| JP5550076B2 (en) | Low resistance through-wafer vias | |
| JP3895595B2 (en) | Method for vertically integrating electrical components by back contact | |
| KR102215288B1 (en) | Barrier layer for interconnection in 3D integrated devices | |
| US8344471B2 (en) | CMOS image sensor big via bonding pad application for AICu process | |
| US8456004B2 (en) | Template wafer and process for small pitch flip-chip interconnect hybridization | |
| CN100442545C (en) | Method for preparing focal plane of quantum trap infrared detecter | |
| CN102280456B (en) | Infrared focal plane array seeker integrated structure and manufacturing method | |
| KR20040060916A (en) | Chip and wafer integration process using vertical connections | |
| US20080088004A1 (en) | Wafer level package structure with build up layers | |
| CN107579032B (en) | A kind of backside process method of compound semiconductor device | |
| CN102637713B (en) | Method for packaging image sensor comprising metal micro-bumps | |
| CN107195627A (en) | A kind of gallium nitride transistor and the integrated method of silicon transistor | |
| JP5003023B2 (en) | Substrate processing method and semiconductor device manufacturing method | |
| TW202236580A (en) | Package structures with built-in emi shielding | |
| CN105047620A (en) | Stacked Dies With Wire Bonds and Method | |
| CN104795338A (en) | Wafer-level low-cost packaging process and structure of backside-illuminated image chip | |
| CN102812548B (en) | Multichip IC | |
| JP6309001B2 (en) | Receiver chip in imaging system | |
| CN102544040B (en) | Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor | |
| CN104465570B (en) | A kind of TSV Interposer structures and its method for packing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180403 |