CN106708459A - Large screen splicing controller - Google Patents
Large screen splicing controller Download PDFInfo
- Publication number
- CN106708459A CN106708459A CN201710159024.5A CN201710159024A CN106708459A CN 106708459 A CN106708459 A CN 106708459A CN 201710159024 A CN201710159024 A CN 201710159024A CN 106708459 A CN106708459 A CN 106708459A
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- card
- control
- large screen
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
- H04N5/44504—Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
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- Engineering & Computer Science (AREA)
- Computer Graphics (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Studio Circuits (AREA)
Abstract
The invention discloses a large screen splicing controller which comprises a power supply, a cross backboard, a control card and N connectors. Input cards or output cards can be inserted into the connectors, the power supply supplies power to the whole large screen splicing controller, the cross backboard realize exchange of a high-speed video single and equally distributes control information to corresponding sub cards, the input cards collect the video signals and serialize the same, the output cards perform high-speed serial signal decoding and realize a video processing function, and the control card is connected to a control host computer and controls the whole system. The invention is a processor of a hardware architecture based on FPGA, so that the utilization ratios of ports are improved, the design is flexible, and perfect synchronization of all output pictures can be guaranteed.
Description
Technical field
It is to be related to a kind of large screen splicing controller specifically the present invention relates to technical field of image processing.
Background technology
Image mosaic controller is widely used in municipal unit and enterprise, used as information issue, monitor in real time, meeting etc.
The application of formal occasion.By the control of image mosaic controller, windowing, segmentation, roaming, splicing, the contracting of each picture can be realized
Put, many pictures are superimposed.Existing image mosaic controller generally includes input card, output card and the control of switch card and its connection
Card.
However, in existing image mosaic controller, switch card is in occupation of than larger cost.Wherein, any switch card
What the input and output port number that can be provided was usually fixed, it is impossible to change its interface quantity or position.Greatly limitation
The utilization rate of switching card port, reduces the disposal ability and cost performance of image mosaic controller, is unfavorable for image mosaic control
The popularization and application of device processed.
Drawbacks described above, is worth solving.
The content of the invention
In order to overcome the shortcomings of existing technology, the present invention provides a kind of large screen splicing controller.
Technical solution of the present invention is as described below：
A kind of large screen splicing controller, it is characterised in that including power supply, intersect backboard, control card and N number of connector,
The connector includes input card and output card, and the power supply is powered for whole large screen splicing controller, described to intersect the back of the body
Plate is connected with the input card, the output card and the control card respectively, and the input card other end connects vision signal
Source, the output card other end connects video display terminal, and the control card other end connects control main frame；In N number of company
Connect in device, there is a connector to be input into as fixed, the X connector is exported as fixed, the remaining connection
Device can be configured to input or export.
According to the present invention of such scheme, it is characterised in that N=16, X=4.
According to the present invention of such scheme, it is characterised in that the intersection backboard include fast signal exchange device, FPGA, can
Mbus device and clock multichannel buffer, the high speed signal exchanger complete vision signal and intersect, and the FPGA is completed
The distribution of control signal, base map data and caption data, the programmable clock device and the clock multichannel buffer are formed and regarded
Frequency synchronizing clock signals.
According to the present invention of such scheme, it is characterised in that the control main frame is interacted with user's, by the control of user
Information is converted into control parameter and is issued to the control card by TCP/IP, while obtained with the control cartoon letters currently setting
Standby information.
Further, the control card reads the information of each described input card and the output card, by video letter
The relevant information in number source is transferred to the control main frame, and each control instruction of the control main frame is sent by the control card
To the corresponding input card and the output card, while the instruction according to the control main frame completes high on the intersection backboard
The handover operation of fast video channel.
According to the present invention of such scheme, it is characterised in that in the input card course of work, first carry out adopting for video
Collection, after being packed through data, completes scrambling, high-speed serial signals are formed after reverse non-return-to-zero coding and the intersection is transferred to
Backboard.
According to the present invention of such scheme, it is characterised in that the output card realizes that high-speed serial signals are received, by mirror
Phase device, low pass filter, Voltage-Controlled oscillation circuit and frequency divider complete the recovery of data clock, and the data clock is gone here and there for high speed
The clock of row extracting data；Lost favour by the data and complete the parallelization of data, the data after parallelization are carried out reversely
Non-return-to-zero decoding, descrambling, word alignment, key information correction, obtain complete video flowing after unpacking；And regarded obtained in the previous step
The function that frequency stream completion scaling, windowing, segmentation, splicing, multi-drawing layer stacking, roaming and base map, subtitle superposition show.
According to the present invention of such scheme, its advantage is that the present invention can realize input and output clamp quantity
Freely configure, output picture can realize any way tiled display, Random route switching；Single screen of the invention can at most open 4
Window, the input source windowing number of individual signals is unrestricted；The present invention is a kind of processor of the hardware structure based on FPGA, is integrally carried
The utilization rate of each port high；The present invention has very strong parallel processing capability, and picture is smooth smooth, supports that output frame is same
Step, it is ensured that the perfect synchronization of all output pictures.And starting up speed of the present invention does not receive virus attack soon, better meets
The requirement of user, is conducive to popularization and application.
Brief description of the drawings
Fig. 1 is structural representation of the invention.
Fig. 2 is that switching backplane video exchange hardware of the present invention connects block diagram.
Fig. 3 realizes flow chart for input card of the present invention.
Fig. 4 realizes flow chart for output card of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings and implementation method is conducted further description to the present invention：
As shown in figure 1, a kind of large screen splicing controller, including power supply, intersection backboard, control card and N number of connector.
Connector includes input card and output card, and power supply is powered for whole large screen splicing controller, intersects backboard point
It is not connected with input card, output card and control card, input card other end connection video signal collective device, the output card other end connects
Connect video display, control card other end connection control main frame；In N number of connector, there is a connector to be input into as fixed,
X connector is exported as fixed, and remaining connector can be configured to input or export.
In the present embodiment, N=16, X=4, i.e., in input and output board number configuration process, it is possible to achieve input maximum 12
Road, minimum 4 tunnel of output, are input into minimum 1 tunnel, export maximum 15 tunnel.
As shown in Fig. 2 intersecting backboard completes the vision signal exchange that input snaps into output card, realize that control snaps into each company
The communication between device is connect, by the data duplications such as base map captions to each input card, output card.
Intersecting backboard includes high speed signal exchanger, FPGA, programmable clock device, clock multichannel buffer.High speed signal
Exchanger completes vision signal and intersects；FPGA completes control signal, base map data, the distribution of caption data；Programmable clock device
Audio video synchronization clock signal is constituted with clock multichannel buffer.
Corresponding application software is run in control main frame, completion is interacted with user's, and it is converted into control parameter simultaneously
Control card is issued to by TCP/IP, while obtaining the information of current device with control cartoon letters.
Control card reads each subcard（Input card, output card）Information and signal source relevant information be transferred to control master
Machine, each control instruction of control main frame by control card be sent to corresponding subcard.Simultaneously according to the instruction of control main frame
Complete the handover operation of high-speed video passage on backboard.
As shown in figure 3, the vision signal of collection is changed into high-speed serial signals and is sent to intersection backboard by input card.Defeated
Enter in the card course of work, first carry out the collection of video, after being packed through data, complete scrambling, carry out shape after reverse non-return-to-zero coding
Into high-speed serial signals and it is transferred to intersection backboard.
As shown in figure 4, output card realizes that high-speed serial signals are received, by phase discriminator, LPF（Low pass filter）、VCO
（Voltage-Controlled oscillation circuit）And frequency divider complete data clock recovery, the data clock be high-speed serial data in extract when
Clock；Lost favour by data and complete the parallelization of data, the data after parallelization are carried out into reverse non-return-to-zero decoding, descrambling, word pair
Together, key information correction, obtains complete video flowing after unpacking；And video flowing obtained in the previous step is completed into scaling, windowing, is divided
Cut, splice, the function that multi-drawing layer stacking, roaming and base map, subtitle superposition show.
The present invention is integrally improved the utilization rate of each port, increased the splicing ability of whole controller, more preferably
The requirement for meeting user, be conducive to popularization and application.
It should be appreciated that for those of ordinary skills, can according to the above description be improved or converted,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Exemplary description is carried out to patent of the present invention above in conjunction with accompanying drawing, it is clear that the realization of patent of the present invention is not received
The limitation of aforesaid way, if the various improvement that the method design of patent of the present invention and technical scheme are carried out are employed, or without
The design of patent of the present invention and technical scheme are directly applied to other occasions by improvement, within the scope of the present invention.
Claims (6)
1. a kind of large screen splicing controller, it is characterised in that including power supply, intersect backboard, control card and N number of connection
Device, the connector includes input card and output card, and the power supply is powered for whole large screen splicing controller, the intersection
Backboard is connected with the input card, the output card and the control card respectively, the input card other end connection video letter
Number source, the output card other end connects video display terminal, and the control card other end connects control main frame；
In N number of connector, there is a connector to be input into as fixed, the X connector is exported as fixed,
The remaining connector can be configured to input or export.
2. large screen splicing controller according to claim 1, it is characterised in that the intersection backboard includes fast signal exchange
Device, FPGA, programmable clock device and clock multichannel buffer, the high speed signal exchanger complete vision signal and intersect, institute
State FPGA and complete the distribution of control signal, base map data and caption data, the programmable clock device and the clock multichannel are slow
Rush device and form audio video synchronization clock signal.
3. large screen splicing controller according to claim 1, it is characterised in that the control main frame is interacted with user's,
The control information of user is converted into control parameter and the control card is issued to by TCP/IP, at the same with the control cartoon
Letter obtains the information of current device.
4. large screen splicing controller according to claim 3, it is characterised in that the control card reads each input
The information of card and the output card, the control main frame, the control master are transferred to by the relevant information of the video signal source
Each control instruction of machine is sent to the corresponding input card and the output card by the control card, while according to described
The instruction of control main frame completes the handover operation for intersecting high-speed video passage on backboard.
5. large screen splicing controller according to claim 1, it is characterised in that in the input card course of work, first
The collection of video is carried out, after being packed through data, scrambling is completed, high-speed serial signals are formed after reverse non-return-to-zero coding and is passed
It is defeated to the intersection backboard.
6. large screen splicing controller according to claim 1, it is characterised in that the output card realizes high-speed serial signals
Receive, the recovery of data clock, the data are completed by phase discriminator, low pass filter, Voltage-Controlled oscillation circuit and frequency divider
Clock is the clock of extraction in high-speed serial data；Lost favour by the data and complete the parallelization of data, after parallelization
Data carry out reverse non-return-to-zero decoding, descrambling, word alignment, key information correction, and complete video flowing is obtained after unpacking；And will be upper
The video flowing that one step is obtained completes scaling, windowing, segmentation, splicing, multi-drawing layer stacking, roaming and base map, subtitle superposition and shows
Function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710159024.5A CN106708459A (en) | 2017-03-17 | 2017-03-17 | Large screen splicing controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710159024.5A CN106708459A (en) | 2017-03-17 | 2017-03-17 | Large screen splicing controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106708459A true CN106708459A (en) | 2017-05-24 |
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ID=58886816
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710159024.5A Pending CN106708459A (en) | 2017-03-17 | 2017-03-17 | Large screen splicing controller |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110134352A (en) * | 2018-02-08 | 2019-08-16 | 北京淳中科技股份有限公司 | A kind of signal processing system, control device, output device and method |
| CN111031380A (en) * | 2019-12-20 | 2020-04-17 | 威创集团股份有限公司 | Subtitle video processing method and system |
| CN112256215A (en) * | 2020-09-23 | 2021-01-22 | 安徽中科新辰技术有限公司 | Large-screen visual comprehensive application all-in-one machine equipment |
| CN113038036A (en) * | 2019-12-24 | 2021-06-25 | 西安诺瓦星云科技股份有限公司 | Background image display method, video processing equipment, display system and main control card |
| CN113810652A (en) * | 2021-09-17 | 2021-12-17 | 随锐科技集团股份有限公司 | Method and system for on-wall display of conference |
| CN114584823A (en) * | 2020-12-01 | 2022-06-03 | 深圳市奥拓电子股份有限公司 | Flexible windowing video splicing processor, LED display system and storage medium |
| CN116095418A (en) * | 2022-11-30 | 2023-05-09 | 天地阳光通信科技（北京）有限公司 | Subtitle roaming system and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202634558U (en) * | 2012-06-28 | 2012-12-26 | 深圳市唯奥视讯技术有限公司 | Image processing device |
| CN104572534A (en) * | 2014-12-06 | 2015-04-29 | 呼和浩特铁路局科研所 | Locomotive information monitoring equipment and operating method thereof |
| CN105630446A (en) * | 2015-12-23 | 2016-06-01 | 广州市天誉创高电子科技有限公司 | FPGA technology based video processing system |
| CN105721795A (en) * | 2016-01-21 | 2016-06-29 | 西安诺瓦电子科技有限公司 | Video matrix stitching device and switching bottom plate thereof |
| CN205545627U (en) * | 2016-03-29 | 2016-08-31 | 南京欧帝科技股份有限公司 | Video mosaicing processing ware of tailorable signal source |
| CN206975625U (en) * | 2017-03-17 | 2018-02-06 | 深圳市东明炬创电子有限公司 | A kind of large screen splicing controller |
-
2017
- 2017-03-17 CN CN201710159024.5A patent/CN106708459A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202634558U (en) * | 2012-06-28 | 2012-12-26 | 深圳市唯奥视讯技术有限公司 | Image processing device |
| CN104572534A (en) * | 2014-12-06 | 2015-04-29 | 呼和浩特铁路局科研所 | Locomotive information monitoring equipment and operating method thereof |
| CN105630446A (en) * | 2015-12-23 | 2016-06-01 | 广州市天誉创高电子科技有限公司 | FPGA technology based video processing system |
| CN105721795A (en) * | 2016-01-21 | 2016-06-29 | 西安诺瓦电子科技有限公司 | Video matrix stitching device and switching bottom plate thereof |
| CN205545627U (en) * | 2016-03-29 | 2016-08-31 | 南京欧帝科技股份有限公司 | Video mosaicing processing ware of tailorable signal source |
| CN206975625U (en) * | 2017-03-17 | 2018-02-06 | 深圳市东明炬创电子有限公司 | A kind of large screen splicing controller |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110134352A (en) * | 2018-02-08 | 2019-08-16 | 北京淳中科技股份有限公司 | A kind of signal processing system, control device, output device and method |
| CN110134352B (en) * | 2018-02-08 | 2022-02-01 | 北京淳中科技股份有限公司 | Signal processing system, control device, output device and method |
| CN111031380A (en) * | 2019-12-20 | 2020-04-17 | 威创集团股份有限公司 | Subtitle video processing method and system |
| CN113038036A (en) * | 2019-12-24 | 2021-06-25 | 西安诺瓦星云科技股份有限公司 | Background image display method, video processing equipment, display system and main control card |
| CN112256215A (en) * | 2020-09-23 | 2021-01-22 | 安徽中科新辰技术有限公司 | Large-screen visual comprehensive application all-in-one machine equipment |
| CN114584823A (en) * | 2020-12-01 | 2022-06-03 | 深圳市奥拓电子股份有限公司 | Flexible windowing video splicing processor, LED display system and storage medium |
| CN113810652A (en) * | 2021-09-17 | 2021-12-17 | 随锐科技集团股份有限公司 | Method and system for on-wall display of conference |
| CN116095418A (en) * | 2022-11-30 | 2023-05-09 | 天地阳光通信科技（北京）有限公司 | Subtitle roaming system and method |
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Inventor after: Zeng Xumin Inventor after: Wang Jiaye Inventor after: Zhan Chenghai Inventor after: Tu Huakang Inventor after: Wei Yushan Inventor after: Zeng Shuisheng Inventor after: Xiao Yuan Inventor after: Li Dajie Inventor before: Wang Jiaye Inventor before: Li Dajie Inventor before: Zhang Daogen Inventor before: Wang Jie Inventor before: Yuan Hongsheng Inventor before: Zeng Xumin |