CN106684154A - Film transistor and preparation method thereof, and array substrate - Google Patents
Film transistor and preparation method thereof, and array substrate Download PDFInfo
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- CN106684154A CN106684154A CN201611262076.7A CN201611262076A CN106684154A CN 106684154 A CN106684154 A CN 106684154A CN 201611262076 A CN201611262076 A CN 201611262076A CN 106684154 A CN106684154 A CN 106684154A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 140
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 81
- 239000011229 interlayer Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 76
- 239000010409 thin film Substances 0.000 claims description 69
- 239000010408 film Substances 0.000 claims description 59
- 239000007769 metal material Substances 0.000 claims description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000007789 gas Substances 0.000 abstract description 27
- 238000012423 maintenance Methods 0.000 abstract description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- 238000009776 industrial production Methods 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 229910004205 SiNX Inorganic materials 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 239000002356 single layer Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 5
- 229910018503 SF6 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000003912 environmental pollution Methods 0.000 description 2
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229920005570 flexible polymer Polymers 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a film transistor and a preparation method thereof, and an array substrate. The preparation method of the film transistor includes preparing a polycrystalline silicon layer on a substrate; preparing a metal film layer and an interlayer insulation film on the polycrystalline silicon layer in sequence; forming a first via hole penetrating through the interlayer insulation film in the metal film layer and preparing a drain electrode and a source electrode. According to the invention, by adding the metal film layer on the polycrystalline silicon layer, the polycrystalline silicon layer can be protected when the via hole is formed through etching and error etching of the polycrystalline silicon layer is avoided, so that the yield of the film transistor is improved. Since etching gases have comparatively high selection ratio as for the insulation layer and the metal film layer, two-phase etching is not required and gases such as C4F8, C2HF5 and the like having high carbon content are not needed in use. Therefore, generation of reactive product of CFx in an equipment chamber is avoided, so that equipment maintenance period is prolonged and industrial production cost is saved.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin film transistor (TFT) and preparation method thereof, including the thin film
The array base palte of transistor.
Background technology
Polysilicon (p-si) thin film transistor (TFT) (Thin Film Transistor, TFT) due to response time it is fast, hold
The advantages of heavy doping, channel current are stablized easily is realized, is widely applied in display field.
In the preparation technology of polycrystalline SiTFT, before preparing source/drain, via technique is first carried out, in p-si
Layer via formed above.Traditional via technique, one is only with CF4/O2Gas is performed etching, and this technique is due to etching gas
And there are p-Si layers while the problem being etched away to the selection of dielectric film and p-Si than low in body.In order to improve to dielectric film and
The selection ratio of p-Si, another kind of technique is to adopt CF4/O2After gas performs etching certain hour, using C4F8And C2HF5Deng
The higher gas of carbon containing continues etching.But, used C4F8And C2HF5In the case of gas, CFxReactive product it is attached
In apparatus cavity, cause equipment to need the normal maintainings of Jing, shorten the maintenance cycle of equipment.
The content of the invention
In view of this, it is necessary to which a kind of thin film transistor (TFT) and preparation method thereof, array base palte are provided, polysilicon can be avoided
Layer is etched by mistake, protects polysilicon layer, while the maintenance cycle of extension device, saves commercial production cost.
The invention discloses a kind of preparation method of thin film transistor (TFT), which includes：
Polysilicon layer is prepared on substrate；
Metallic diaphragm and interlayer dielectric are prepared on the polysilicon layer sequentially；
The first via through the interlayer dielectric is formed on the metallic diaphragm and source-drain electrode is prepared.
Wherein in one embodiment, first mistake formed on the metallic diaphragm through the interlayer dielectric
Hole, be：
Performed etching using fluorine-containing pre-set gas, the through the interlayer dielectric is formed on the metallic diaphragm
One via.
It is wherein in one embodiment, described that metallic diaphragm and interlayer dielectric are sequentially prepared on the polysilicon layer,
Including：
Metallic diaphragm is prepared on region of the polysilicon layer corresponding to source-drain electrode；
Interlayer dielectric is prepared on the polysilicon layer, the interlayer dielectric covers the metallic diaphragm.
It is wherein in one embodiment, described to prepare interlayer dielectric on the polysilicon layer, including：
Gate insulating film, grid and interlayer dielectric are prepared on the polysilicon layer sequentially；
Also, first via formed on the metallic diaphragm through the interlayer dielectric, be：In the gold
The first via through the interlayer dielectric and the gate insulating film is formed in category film layer.
It is wherein in one embodiment, described to prepare metal film on region of the polysilicon layer corresponding to source-drain electrode
Layer, including：
Gate insulating film is prepared on the polysilicon layer；
The second via through the gate insulating film is formed on the region corresponding to source-drain electrode；
Prepare grid and metallic diaphragm on the gate insulating film respectively, the metallic diaphragm covers second mistake
Hole；
Also, it is described to prepare interlayer dielectric on the polysilicon layer, be：Interlayer is prepared on the gate insulating film
Dielectric film, the interlayer dielectric cover the grid and the metallic diaphragm.
Wherein in one embodiment, it is described prepare polysilicon layer on substrate before, the preparation of the thin film transistor (TFT)
Method also includes：
Grid and gate insulating film are prepared on the substrate sequentially；
It is described that polysilicon layer is prepared on substrate, be：Polysilicon layer is prepared on the gate insulating film.
Wherein in one embodiment, before grid is prepared, the preparation method of the thin film transistor (TFT) also includes：
Cushion is prepared on the substrate.
The invention also discloses a kind of thin film transistor (TFT), the thin film transistor (TFT) is using the preparation as described in above-mentioned any one
Method is prepared.
Wherein in one embodiment, the metallic diaphragm using with grid identical metal material.
The invention also discloses a kind of array base palte, which includes the thin film transistor (TFT) as described in above-mentioned any one.
Above-mentioned thin film transistor (TFT) and preparation method thereof, array base palte, by increasing a metallic diaphragm, energy on the polysilicon layer
Enough in etching vias, polysilicon layer is protected, it is to avoid polysilicon layer is etched by mistake, so as to improve the yields of thin film transistor (TFT).
Due to etching gas to insulating barrier and metallic diaphragm with compared with high selectivity, without the need for perform etching in two stages, also without using
The higher C of carbon containing4F8And C2HF5Deng gas, therefore CF will not be generated in apparatus cavityxReactive product, so as to extend
The maintenance cycle of equipment, saves commercial production cost, also reduces environmental pollution.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
The accompanying drawing of other embodiment is obtained according to these accompanying drawings.
Schematic flow sheets of the Fig. 1 for the preparation method of the thin film transistor (TFT) of one embodiment of the invention；
Schematic flow sheets of Fig. 2 a for the preparation method of the thin film transistor (TFT) of another embodiment of the present invention；
Schematic flow sheets of Fig. 2 b for the preparation method of the thin film transistor (TFT) of further embodiment of this invention；
Fig. 3 a are the schematic flow sheet of the preparation method of the thin film transistor (TFT) of a specific embodiment of the invention；
Fig. 3 b are the structural representation of the thin film transistor (TFT) that a specific embodiment of the invention is prepared；
Fig. 4 a are the schematic flow sheet of the preparation method of the thin film transistor (TFT) of another specific embodiment of the present invention；
Fig. 4 b are the structural representation of the thin film transistor (TFT) that another specific embodiment of the present invention is prepared；
Fig. 5 a are the schematic flow sheet of the preparation method of the thin film transistor (TFT) of still another embodiment of the present invention；
Fig. 5 b are the structural representation of the thin film transistor (TFT) that still another embodiment of the present invention is prepared.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is below in conjunction with drawings and Examples, right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.
In describing the invention, it is to be understood that term " first ", " second " are only used for describing purpose, and can not
It is interpreted as indicating or implying relative importance or the implicit quantity for indicating indicated technical characteristic.Thus, define " the
One ", at least one this feature can be expressed or be implicitly included to the feature of " second ".In describing the invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise expressly limited specifically.
Thin film transistor (TFT) according to embodiments of the present invention and preparation method thereof, array base palte are described below in conjunction with the accompanying drawings.Example
Such as, the preparation method of the thin film transistor (TFT) of one embodiment of the invention, including：Polysilicon layer is prepared on substrate；In the polycrystalline
Metallic diaphragm and interlayer dielectric are prepared on silicon layer sequentially；The through the interlayer dielectric is formed on the metallic diaphragm
One via simultaneously prepares source-drain electrode.For example, above-mentioned preparation method, is the preparation method of the thin film transistor (TFT) of top gate structure.And for example, on
Preparation method is stated, is the preparation method of the thin film transistor (TFT) of bottom grating structure.
Fig. 1 is referred to, which is the schematic flow sheet of the preparation method of the thin film transistor (TFT) of one embodiment of the invention.The preparation
Method includes：
S110, prepares polysilicon layer on substrate.For example, polysilicon layer is prepared on the glass substrate.And for example, in flexible base
Polysilicon layer is prepared on plate.And for example, polysilicon layer is prepared in flexible polymer substrate.
In one embodiment, the preparation method is used for the thin film transistor (TFT) for preparing top gate structure.Now, it is a kind of to implement
Mode is, polysilicon layer is directly prepared on substrate.Another embodiment is that cushion is prepared on substrate, then slow
Rush.Another embodiment is, when using flexible base board, in order to the steam for improving flexible base board hinders
Every ability, aqueous vapor separation layer is prepared on flexible substrates, polysilicon layer is prepared on aqueous vapor separation layer；Or, in water vapor rejection
Cushion and polysilicon layer are prepared on layer sequentially.
In another embodiment, the preparation method is used for the thin film transistor (TFT) for preparing bottom grating structure.Now, preparing
Before polysilicon layer, grid and gate insulating film are sequentially prepared on substrate first, polysilicon layer is prepared on gate insulating film.Its
In, a kind of embodiment is, grid and gate insulating film are directly sequentially prepared on substrate.Another embodiment is, in base
Cushion is prepared on plate, grid and gate insulating film is then sequentially prepared on the buffer layer.Another embodiment is to work as employing
During flexible base board, in order to improve the water vapor rejection ability of flexible base board, aqueous vapor separation layer is prepared on flexible substrates, hinder in steam
Grid and gate insulating film are prepared on interlayer sequentially；Or, cushion, grid and grid are sequentially prepared on aqueous vapor separation layer exhausted
Velum.
Wherein, cushion is SiOxLayer, SiNxLayer or SiOxLayer and SiNxThe stacked combination of layer.For example, cushion is monolayer
SiOxLayer, or monolayer SiNxLayer, or multilamellar SiOxLayer, or multilamellar SiNxLayer, or at least one of which SiOxLayer and at least one
Layer SiNxThe stacking of layer.
S120, sequentially prepares metallic diaphragm and interlayer dielectric on the polysilicon layer.
Used as a kind of embodiment, the metallic diaphragm is completely covered polysilicon layer.For example, the metallic diaphragm is one layer or many
Layer.And for example, the metallic diaphragm is multilamellar, and the wherein material of different metal film layer can be with identical or different.
Alternatively, the metallic diaphragm covers the subregion of polysilicon layer, and such as metallic diaphragm at least covers
The region of correspondence via on lid polysilicon layer.And for example, the metallic diaphragm covers the region of correspondence source-drain electrode on polysilicon layer.Again
Such as, step S120 is specially：Metallic diaphragm is prepared on region of the polysilicon layer corresponding to source-drain electrode；In the polysilicon
Interlayer dielectric is prepared on layer, the interlayer dielectric covers the metallic diaphragm.Now, can be existed by patterned mask plate
Metallic diaphragm is prepared on polysilicon layer.
In one embodiment, the preparation method is used for the thin film transistor (TFT) for preparing top gate structure.Now, it is a kind of to implement
Mode is to prepare metallic diaphragm on the polysilicon, and gate insulating film, grid and layer insulation are sequentially prepared on metallic diaphragm
Film.Another embodiment is to prepare gate insulating film on the polysilicon layer, prepares grid and gold on gate insulating film respectively
Category film layer.For example, for improve production efficiency, can be prepared using identical metal material simultaneously by patterned mask plate
Grid and metallic diaphragm.
In another embodiment, the preparation method is used for the thin film transistor (TFT) for preparing bottom grating structure.Now, in polycrystalline
Metallic diaphragm is prepared on silicon, interlayer dielectric is prepared on metallic diaphragm.
It should be appreciated that in being embodied as, the material of metallic diaphragm can be with identical or different with the material of grid.For example, grid
Pole selects metal molybdenum or Titanium, metallic diaphragm select metal molybdenum, Titanium or other metal materials.For example, metal film
Layer choosing with source-drain electrode identical metal material.And for example, above-mentioned metallic diaphragm and source-drain electrode select metallic aluminium, Titanium or titanium
The materials such as aluminium alloy.And for example, above-mentioned metallic diaphragm is the overlaying structure of aluminium lamination and titanium layer；And for example, above-mentioned metallic diaphragm be titanium/
Three layers of overlaying structure of aluminum/titanium.
In the present embodiment, increase by a metallic diaphragm between polysilicon layer and interlayer dielectric, metal contact can be produced
Interface, in follow-up via etch technique, due to etching gas to metallic diaphragm and interlayer dielectric with compared with high selectivity,
Polysilicon layer can be avoided to be etched by mistake, therefore, it is possible to protect polysilicon layer.
S130, forms the first via through the interlayer dielectric on the metallic diaphragm and prepares source-drain electrode.
For example, the first via is formed by dry etch process.For example, performed etching using fluorine-containing pre-set gas, shape
Into the first via.And for example, by ICP (Inductively Couple Plasma, inductive couple plasma) etching technics, adopt
Performed etching with fluorine-containing pre-set gas, form the first via.Preferably, pre-set gas are fluorine-containing and carbon-free gas,
Or, pre-set gas are fluorine-containing and the less gas of phosphorus content.For example, pre-set gas are that fluorine-containing and phosphorus content is less than C4F8
And C2HF5Gas；And for example, pre-set gas are carbon tetrafluoride (CF4) gas, sulfur hexafluoride (SF6) gas, carbon tetrafluoride and oxygen
Mixed gas (the CF of gas4/O2) or sulfur hexafluoride and oxygen mixed gas (SF6/O2)。
Wherein, the first via is formed in above the metallic diaphragm, and the diameter of the via is less than or equal to described
The width of metallic diaphragm.
In one embodiment, for the thin film transistor (TFT) of some top gate structures, first via also extends through gate insulator
Film.For example, the thin film transistor (TFT) of the top gate structure for gate insulating film on metallic diaphragm, first via also extend through grid
Pole dielectric film.
In traditional handicraft, source-drain electrode, source-drain electrode filling via so that source-drain electrode and polysilicon layer reality after forming via, are prepared
Existing Ohmic contact.In the present embodiment, on polysilicon layer, increase by a metallic diaphragm, equally Ohmic contact can be realized with source-drain electrode.Example
Such as, in order to obtain the Ohmic contact interface with traditional handicraft identical metal with quasiconductor, above-mentioned metallic diaphragm is selected and source and drain
Pole identical metal material, such as titanium, aluminum, titanium-aluminium alloy etc..
Wherein, source-drain electrode includes source electrode and drain electrode.For example, formed on metallic diaphragm through two of interlayer dielectric the
One via, then prepares two electrodes for filling two first vias, and in the two electrodes, any one is as source electrode, another
Individual conduct drain electrode.
The preparation method of above-mentioned thin film transistor (TFT), by increasing by a metallic diaphragm on the polysilicon layer, can be etched
Kong Shi, protects polysilicon layer, it is to avoid polysilicon layer is etched by mistake, so as to improve the yields of thin film transistor (TFT).Due to etching gas
Body, need not be performed etching with compared with high selectivity in two stages to insulating barrier and metallic diaphragm, also higher without using carbon containing
C4F8And C2HF5Deng gas, therefore CF will not be generated in apparatus cavityxReactive product, so as to the maintenance of extension device
Maintenance period, commercial production cost is saved, environmental pollution is also reduced.
In one embodiment, as shown in Figure 2 a, step S120 includes：
S121, prepares metallic diaphragm on region of the polysilicon layer corresponding to source-drain electrode.
S122, prepares interlayer dielectric on the polysilicon layer, and the interlayer dielectric covers the metallic diaphragm.
In one embodiment, for example, when preparing the thin film transistor (TFT) of top gate structure, step S122 is specially：Described many
Gate insulating film, grid and interlayer dielectric are prepared on crystal silicon layer sequentially.Now, step S130 is specially：Formed through described
First via of interlayer dielectric and the gate insulating film.
In one embodiment, for example when preparing the thin film transistor (TFT) of top gate structure, as shown in Figure 2 b, step S121 bag
Include：
S121a, prepares gate insulating film on the polysilicon layer；
S121b, forms the second via through the gate insulating film on the region corresponding to source-drain electrode；
S121c, prepares grid and metallic diaphragm on the gate insulating film respectively, and the metallic diaphragm covers described the
Two vias.
Now, step S122 is：Interlayer dielectric is prepared on the gate insulating film, the interlayer dielectric covers institute
State grid and the metallic diaphragm.
In one embodiment, for example when preparing the thin film transistor (TFT) of bottom grating structure, before step S110, above-mentioned preparation
Method also includes：Grid and gate insulating film are prepared on the substrate sequentially.Now, step S122 is specially：In the grid
Polysilicon layer is prepared on the dielectric film of pole.
Several specific embodiments of the preparation method of the thin film transistor (TFT) of the present invention are presented herein below.
For example, Fig. 3 a and Fig. 3 b are seen also.As shown in Figure 3 a, the preparation side of the thin film transistor (TFT) of a specific embodiment
Method includes：
S310, prepares polysilicon layer 11 on substrate.
For example, polysilicon layer is directly prepared on substrate.And for example, in order to lift the performance of polysilicon layer, first on substrate
Cushion is prepared, polysilicon layer is prepared on the buffer layer.Wherein, cushion is monolayer SiOxLayer, or monolayer SiNxLayer, or
Multilamellar SiOxLayer, or multilamellar SiNxLayer, or at least one of which SiOxLayer and at least one of which SiNxThe stacking of layer.
S320, sequentially prepares metallic diaphragm 12, gate insulating film 13, grid 14 and interlayer exhausted on the polysilicon layer 11
Velum 15.
S330, forms the first mistake through the interlayer dielectric and the gate insulating film on the metallic diaphragm
Hole.
S340, prepares source-drain electrode 16.Wherein the first via is filled by source-drain electrode 16.
Above-mentioned preparation method is used to prepare the thin film transistor (TFT) of top gate structure, according to above-mentioned preparation method, prepare as
Thin film transistor (TFT) 10 shown in Fig. 3 b.
And for example, Fig. 4 a and Fig. 4 b are seen also.As shown in fig. 4 a, the preparation of the thin film transistor (TFT) of another specific embodiment
Method includes：
S410, prepares polysilicon layer 11 on substrate.
For example, polysilicon layer is directly prepared on substrate.And for example, in order to lift the performance of polysilicon layer, first on substrate
Cushion is prepared, polysilicon layer is prepared on the buffer layer.Wherein, cushion is monolayer SiOxLayer, or monolayer SiNxLayer, or
Multilamellar SiOxLayer, or multilamellar SiNxLayer, or at least one of which SiOxLayer and at least one of which SiNxThe stacking of layer.
S420, prepares gate insulating film 13 on the polysilicon layer 11.
S430, forms the second via through the gate insulating film 13 on the region corresponding to source-drain electrode.
S440, prepares grid 14 and metallic diaphragm 12 on the gate insulating film 13 respectively, and the metallic diaphragm 12 covers
Cover second via.
S450, prepares interlayer dielectric 15 on the gate insulating film 13, and the interlayer dielectric 15 covers the grid
Pole 14 and the metallic diaphragm 12.
S460, forms the first via through the interlayer dielectric 15 on the metallic diaphragm 12.
S470, prepares source-drain electrode 16.
Above-mentioned preparation method is used to prepare the thin film transistor (TFT) of top gate structure, according to above-mentioned preparation method, prepare as
Thin film transistor (TFT) 10 shown in Fig. 4 b.
And for example, Fig. 5 a and Fig. 5 b are seen also.As shown in Figure 5 a, the preparation of the thin film transistor (TFT) of still another embodiment
Method includes：
S510, sequentially prepares grid 14 and gate insulating film 13 on the substrate；
For example, grid is prepared in direct substrate.And for example, the pollution in order to avoid substrate to grid, before the gate is formed,
Cushion is prepared on substrate first, cushion is monolayer SiOxLayer, or monolayer SiNxLayer, or multilamellar SiOxLayer, or multilamellar
SiNxLayer, or at least one of which SiOxLayer and at least one of which SiNxThe stacking of layer.
S520, prepares polysilicon layer 11 on the gate insulating film.
S530, sequentially prepares metallic diaphragm 12 and interlayer dielectric 15 on the polysilicon layer.
S540, forms the first via through the interlayer dielectric 15 on the metallic diaphragm 12.
S550, prepares source-drain electrode 16.
Above-mentioned preparation method is used to prepare the thin film transistor (TFT) of bottom grating structure, according to above-mentioned preparation method, prepare as
Thin film transistor (TFT) 10 shown in Fig. 5 b.
The invention also discloses a kind of thin film transistor (TFT), the thin film transistor (TFT) is using the preparation described in any of the above-described embodiment
Method is prepared.For example, thin film transistor (TFT) of the thin film transistor (TFT) for top gate structure.And for example, the thin film transistor (TFT) is bottom gate
The thin film transistor (TFT) of structure.
Wherein in one embodiment, the metallic diaphragm in the thin film transistor (TFT) using with grid identical metal material.
Wherein in one embodiment, the metallic diaphragm in the thin film transistor (TFT) using with source-drain electrode identical metal material
Material.
The invention also discloses a kind of array base palte, the array base palte includes the film crystal described in any of the above-described embodiment
Pipe.For example, some data wires, some scan lines and some thin film transistor (TFT)s in array distribution are included on the array base palte, if
Dry data wire and some scan line vertical interlaceds form multiple unit areas, are provided with an at least thin film brilliant in each unit area
Body pipe.For example, a thin film transistor (TFT), the grid connection scan line of the thin film transistor (TFT) are provided with each unit area；This is thin
The source electrode of film transistor connects the driving voltage input line of data wire, i.e. pixel；The drain electrode connection place pixel of thin film transistor (TFT)
Pixel electrode anode.Voltage in scan line controls the on/off of thin film transistor (TFT), when the thin film transistor (TFT) of a certain pixel
During unlatching, the pixel drive voltage on data wire is input to pixel electrode by source electrode and drain electrode, makes the pixel operation.
Each technical characteristic of embodiment described above arbitrarily can be combined, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more concrete and detailed, but and
Therefore can not be construed as limiting the scope of the patent.It should be pointed out that for one of ordinary skill in the art comes
Say, without departing from the inventive concept of the premise, some deformations and improvement can also be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be defined by claims.
Claims (10)
1. a kind of preparation method of thin film transistor (TFT), it is characterised in that include：
Polysilicon layer is prepared on substrate；
Metallic diaphragm and interlayer dielectric are prepared on the polysilicon layer sequentially；
The first via through the interlayer dielectric is formed on the metallic diaphragm and source-drain electrode is prepared.
2. preparation method as claimed in claim 1, it is characterised in that described to be formed through the layer on the metallic diaphragm
Between dielectric film the first via, be：
Performed etching using fluorine-containing pre-set gas, the first mistake through the interlayer dielectric is formed on the metallic diaphragm
Hole.
3. preparation method as claimed in claim 1, it is characterised in that described that metal film is sequentially prepared on the polysilicon layer
Layer and interlayer dielectric, including：
Metallic diaphragm is prepared on region of the polysilicon layer corresponding to source-drain electrode；
Interlayer dielectric is prepared on the polysilicon layer, the interlayer dielectric covers the metallic diaphragm.
4. preparation method as claimed in claim 3, it is characterised in that described to prepare layer insulation on the polysilicon layer
Film, including：
Gate insulating film, grid and interlayer dielectric are prepared on the polysilicon layer sequentially；
Also, first via formed on the metallic diaphragm through the interlayer dielectric, be：In the metal film
The first via through the interlayer dielectric and the gate insulating film is formed on layer.
5. preparation method as claimed in claim 3, it is characterised in that it is described the polysilicon layer corresponding to source-drain electrode area
Metallic diaphragm is prepared on domain, including：
Gate insulating film is prepared on the polysilicon layer；
The second via through the gate insulating film is formed on the region corresponding to source-drain electrode；
Prepare grid and metallic diaphragm on the gate insulating film respectively, the metallic diaphragm covers second via；
Also, it is described to prepare interlayer dielectric on the polysilicon layer, be：Layer insulation is prepared on the gate insulating film
Film, the interlayer dielectric cover the grid and the metallic diaphragm.
6. preparation method as claimed in claim 1, it is characterised in that it is described prepare polysilicon layer on substrate before, also wrap
Include：
Grid and gate insulating film are prepared on the substrate sequentially；
It is described that polysilicon layer is prepared on substrate, be：Polysilicon layer is prepared on the gate insulating film.
7. preparation method as claimed in claim 6, it is characterised in that before grid is prepared, also include：
Cushion is prepared on the substrate.
8. a kind of thin film transistor (TFT), it is characterised in that the thin film transistor (TFT) is adopted as any one of claim 1 to 7
Preparation method prepare.
9. thin film transistor (TFT) as claimed in claim 8, it is characterised in that the metallic diaphragm using with grid identical metal
Material.
10. a kind of array base palte, it is characterised in that including thin film transistor (TFT) as claimed in claim 8 or 9.
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| CN201611262076.7A CN106684154A (en) | 2016-12-30 | 2016-12-30 | Film transistor and preparation method thereof, and array substrate |
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| CN201611262076.7A CN106684154A (en) | 2016-12-30 | 2016-12-30 | Film transistor and preparation method thereof, and array substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019062260A1 (en) * | 2017-09-28 | 2019-04-04 | 信利（惠州）智能显示有限公司 | Thin-film transistor and method for manufacturing same, array substrate, and display device |
| CN109659357A (en) * | 2018-12-18 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor (TFT) and display panel |
| US20220059630A1 (en) * | 2020-08-18 | 2022-02-24 | Samsung Display Co., Ltd. | Display device and method for manufacturing the same |
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| CN1236981A (en) * | 1998-05-26 | 1999-12-01 | 松下电器产业株式会社 | Film transistor and its making method |
| US6066547A (en) * | 1997-06-20 | 2000-05-23 | Sharp Laboratories Of America, Inc. | Thin-film transistor polycrystalline film formation by nickel induced, rapid thermal annealing method |
| CN102790096A (en) * | 2012-07-20 | 2012-11-21 | 京东方科技集团股份有限公司 | Film transistor as well as manufacturing method thereof, array substrate and display equipment |
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| US6066547A (en) * | 1997-06-20 | 2000-05-23 | Sharp Laboratories Of America, Inc. | Thin-film transistor polycrystalline film formation by nickel induced, rapid thermal annealing method |
| CN1236981A (en) * | 1998-05-26 | 1999-12-01 | 松下电器产业株式会社 | Film transistor and its making method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019062260A1 (en) * | 2017-09-28 | 2019-04-04 | 信利（惠州）智能显示有限公司 | Thin-film transistor and method for manufacturing same, array substrate, and display device |
| CN109659357A (en) * | 2018-12-18 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor (TFT) and display panel |
| US11189731B2 (en) | 2018-12-18 | 2021-11-30 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin-film transistor and display panel |
| US20220059630A1 (en) * | 2020-08-18 | 2022-02-24 | Samsung Display Co., Ltd. | Display device and method for manufacturing the same |
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