CN106653640B - Wafer chip time parameter method of adjustment based on wafer position - Google Patents
Wafer chip time parameter method of adjustment based on wafer position Download PDFInfo
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- CN106653640B CN106653640B CN201710010523.8A CN201710010523A CN106653640B CN 106653640 B CN106653640 B CN 106653640B CN 201710010523 A CN201710010523 A CN 201710010523A CN 106653640 B CN106653640 B CN 106653640B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
Abstract
A kind of wafer chip time parameter method of adjustment based on wafer position of the present invention, utilize CHIPID module built-in in each wafer of every wafer, pass through the setting of the custom field in CHIPID module, indirect assignment write-in is carried out to the adjustment amount of object time parameter, it can be before head end test or back end test, determine that the time parameter and adjustment amount for needing to be adjusted in each chip in all wafers；Therefore the technique distribution for a wafer only being needed to be provided according to fab, either carry out the wafer distribution that primary monitoring test obtains, assignment using custom field in CHIPID module is primary, it can be in subsequent head end test or back end test, directly required time parameter is adjusted, save the time that test is monitored to each chip, greatly improve working efficiency, repeatedly monitoring bring adjustment deviation is avoided simultaneously, testing cost is reduced, chip wafer yields is improved.
Description
Technical field
The present invention relates to chip wafer methods of adjustment, specially the wafer chip time parameter adjustment side based on wafer position
Method.
Background technique
The wafer test of the front end DRAM, due to technique change, the time parameters such as tWR, tRP, tRCD of each wafer chip are in crystalline substance
It is in non-uniform Distribution on circle, and time parameter is unsatisfactory for the wafer chip of condition, can be abandoned, so as to cause chip wafer non-defective unit
The reduction of rate.Existing solution is to be monitored test to wafer, obtains the technique distribution of tWR time parameter, then,
Technique distribution based on tWR time parameter, carries out monolithic to each chip on wafer and is independently adjusted so that tWR meets product
Specification requirement.Therefore it to every wafer chip, requires first to be monitored test, tWR time parameter could be adjusted.It is other
Time parameter adjustment is also in this way, will lead to being significantly increased for testing time in this way.
Summary of the invention
Aiming at the problems existing in the prior art, the present invention provides a kind of wafer chip time parameter based on wafer position
Method of adjustment can quickly adjust undesirable time parameter on wafer chip, and method is simple, easy to operate,
Testing efficiency is high.
The present invention is to be achieved through the following technical solutions:
Wafer chip time parameter method of adjustment based on wafer position, includes the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and obtains all crystalline substances on the wafer
The technique distribution of time parameter in piece；
Step 2, it is distributed according to the technique of time parameter in wafer chip, obtains the survey for needing the object time parameter adjusted
Test result, and test result is compared with specification requirement value, determine the default adjustment amount of object time parameter；
Step 3, in head end test, the adjustment amount of object time parameter is passed through into CHIPID in the corresponding wafer chip that fuses
The FUSE of module custom field carries out assignment, so that the default adjustment amount of object time parameter is built in CHIPID module
In custom field；
Step 4, in head end test, the assignment of custom field in CHIPID module is read, is arranged in obtaining step 2
The default adjustment amount of object time parameter is completed according to the obtained corresponding FUSE of default adjustment amount fusing object time parameter
The adjustment of object time parameter.
Preferably, further include secondary adjustment in back end test to object time parameter, specific step is as follows；
A. the test result of object time parameter is obtained by back end test；
B. read the assignment of custom field in CHIPID module, the object time parameter being arranged in obtaining step 2 it is pre-
If adjustment amount；
C. binding test result and default adjustment amount obtain the secondary adjustment amount of object time parameter；
D. according to the obtained corresponding EFUSE of secondary adjustment amount fusing object time parameter, object time parameter is completed
Secondary adjustment.
Wafer chip time parameter method of adjustment based on wafer position, includes the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and obtains all crystalline substances on the wafer
The technique distribution of time parameter in piece；
Step 2, it is distributed according to the technique of time parameter in wafer chip, obtains the survey for needing the object time parameter adjusted
Test result, and test result is compared with specification requirement value, determine the default adjustment amount of object time parameter；
Step 3, in head end test, the adjustment amount of object time parameter is passed through into CHIPID in the corresponding wafer chip that fuses
The FUSE of module custom field carries out assignment, so that the default adjustment amount of object time parameter is built in CHIPID module
In custom field；
Step 4, in back end test, the assignment of custom field in CHIPID module is read, is arranged in obtaining step 2
The default adjustment amount of object time parameter；According to the obtained corresponding EFUSE of default adjustment amount fusing object time parameter, complete
The adjustment of object time parameter.
Further, the object time parameter is in tWR time parameter, tRP time parameter and tRCD time parameter
It is at least one.
Compared with prior art, the invention has the following beneficial technical effects:
The present invention utilizes CHIPID (CHIP Identity, chip sequence built-in in each wafer of every wafer
Number) module, by the setting of the custom field in CHIPID module, to the adjustment amount progress indirect assignment of object time parameter
Write-in, can before head end test or back end test, determine that need to be adjusted in each chip in all wafers when
Between parameter and adjustment amount；Therefore the technique distribution for a wafer only being needed to be provided according to fab, or carry out primary
The wafer distribution that monitoring test obtains, the assignment using custom field in CHIPID module are primary, it will be able to before subsequent
When end test or back end test, directly required time parameter is adjusted, saves and each chip is monitored
The time of test greatly improves working efficiency, at the same avoid repeatedly monitoring bring adjustment deviation, reduce test at
This, improves chip wafer yields.
Further, using in back end test to the secondary operation of EFUSE (electrically programmable fuse), can be to head end test
In the operation of FUSE (resistance fuse) be modified and adjust again it is easy to operate reliable and stable so that adjustment mode is flexible.
Detailed description of the invention
Fig. 1 is the flow chart of method of adjustment described in present example 1.
Fig. 2 is the flow chart of method of adjustment described in present example 2.
Fig. 3 is the flow chart of method of adjustment described in present example 3.
Fig. 4 is wafer process distribution map described in present example.
Specific embodiment
Below with reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
Method And Principle of the present invention is as follows.
Each wafer of every wafer, all built-in CHIPID module, CHIPID module includes multiple fields, each word
Section FUSE containing multidigit；The field includes: fab code name, design manufacturer's code name, product type, product capacity, chip seat
Mandatory fields and some custom fields such as mark.Default condition, FUSE is unblown, and each field information is complete " 0 ", fusing
The FUSE of respective field, can be to respective field assignment.
The time parameters such as the time parameter of the chip, such as tWR, tRP, tRCD have corresponding respectively
FUSE and EFUSE.Default condition, it is unblown that time parameter corresponds to FUSE/EFUSE, does not adjust corresponding time parameter；Time parameter
After corresponding FUSE/EFUSE fusing, corresponding time parameter can adjust.
The present invention is based on wafer process distribution, wafer process distribution as shown in figure 4, corresponding different location chip
CHIPID module custom field in the FUSE values of the setting adjustment time parameters such as tWR, tRP, tRCD realize default adjustment
The write-in of amount, the FUSE of time parameters such as the subsequent fusing adjustment of FUSE value tWR, tRP, tRCD according to the setting and/or
EFUSE, so as to adjust the object times parameter such as corresponding tWR, tRP, tRCD.
Example 1
The present invention is based on the wafer chip time parameter methods of adjustment of wafer position, as shown in Figure 1, include the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and obtains all crystalline substances on the wafer
The technique distribution of time parameter in piece；
Step 2, tWR time parameter is adjusted, then it is object time parameter；According to time parameter in wafer chip
Technique distribution, obtain the test result of tWR time parameter for needing to adjust, and test result and specification requirement value are compared
Compared with determining the default adjustment amount of tWR time parameter；
Step 3, in head end test, the adjustment amount of tWR time parameter is passed through into CHIPID in the corresponding wafer chip that fuses
The FUSE of module custom field carries out assignment, so that the default adjustment amount of tWR time parameter is built in CHIPID module
In custom field；
Step 4, in head end test, the assignment of custom field in CHIPID module is read, is arranged in obtaining step 2
The default adjustment amount of tWR time parameter completes tWR according to the obtained corresponding FUSE of default adjustment amount fusing tWR time parameter
The adjustment of time parameter.
Example 2
The present invention is based on the wafer chip time parameter methods of adjustment of wafer position, as shown in Fig. 2, include the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and obtains all crystalline substances on the wafer
The technique distribution of time parameter in piece；
Step 2, tRP time parameter is adjusted, then it is object time parameter；According to time parameter in wafer chip
Technique distribution, obtain the test result of tRP time parameter for needing to adjust, and test result and specification requirement value are compared
Compared with determining the default adjustment amount of tRP time parameter；
Step 3, in head end test, the adjustment amount of tRP time parameter is passed through into CHIPID in the corresponding wafer chip that fuses
The FUSE of module custom field carries out assignment, so that the default adjustment amount of tRP time parameter is built in CHIPID module
In custom field；
Step 4, in head end test, the assignment of custom field in CHIPID module is read, is arranged in obtaining step 2
The default adjustment amount of tRP time parameter completes tRP according to the obtained corresponding FUSE of default adjustment amount fusing tRP time parameter
The adjustment of time parameter.
Step 5, to the secondary adjustment of tRP time parameter in back end test；
5.1. the test result of tRP time parameter is obtained by back end test；
5.2. read the assignment of custom field in CHIPID module, the tRP time parameter being arranged in obtaining step 2 it is pre-
If adjustment amount；
5.3. binding test result and default adjustment amount obtain the secondary adjustment amount of tRP time parameter；
5.4. according to the obtained corresponding EFUSE of secondary adjustment amount fusing tRP time parameter, tRP time parameter is completed
Secondary adjustment.
Example 3
The present invention is based on the wafer chip time parameter methods of adjustment of wafer position, as shown in figure 3, include the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and obtains all crystalline substances on the wafer
The technique distribution of time parameter in piece；
Step 2, tRCD time parameter is adjusted, then it is object time parameter；Joined according to the time in wafer chip
Several technique distributions, obtain the test result for needing the tRCD time parameter adjusted, and by test result and specification requirement value into
Row compares, and determines the default adjustment amount of tRCD time parameter；
Step 3, in head end test, the adjustment amount of tRCD time parameter is passed through into CHIPID in the corresponding wafer chip that fuses
The FUSE of module custom field carries out assignment, so that the default adjustment amount of tRCD time parameter is built in CHIPID module
In custom field；
Step 4, in back end test, the assignment of custom field in CHIPID module is read, is arranged in obtaining step 2
The default adjustment amount of tRCD time parameter；According to the obtained corresponding EFUSE of default adjustment amount fusing tRCD time parameter, complete
The adjustment of tRCD time parameter.
Example 4
The present invention is based on the wafer chip time parameter method of adjustment of wafer position, can simultaneously to multiple time parameters into
Row adjustment, can using as example 1-3 any one method, after confirming multiple object time parameters, respectively to its
Assignment is carried out in the different custom fields of CHIPID module, then in head end test or back end test, respectively according to reading
Value, it is corresponding that operation is adjusted to different object time parameters.
Claims (4)
1. the wafer chip time parameter method of adjustment based on wafer position, which is characterized in that include the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and is obtained on the wafer in all wafers
The technique of time parameter is distributed；
Step 2, it is distributed according to the technique of time parameter in wafer chip, obtains the test knot for needing the object time parameter adjusted
Fruit, and test result is compared with specification requirement value, determine the default adjustment amount of object time parameter；
Step 3, in head end test, the adjustment amount of object time parameter is passed through into CHIPID module in the corresponding wafer chip that fuses
The FUSE of custom field carries out assignment, so that the default adjustment amount of object time parameter is built in making by oneself for CHIPID module
In adopted field；
Step 4, in head end test, the assignment of custom field in CHIPID module, the target being arranged in obtaining step 2 are read
The default adjustment amount of time parameter completes target according to the obtained corresponding FUSE of default adjustment amount fusing object time parameter
The adjustment of time parameter.
2. the wafer chip time parameter method of adjustment according to claim 1 based on wafer position, which is characterized in that also
Including, to the secondary adjustment of object time parameter, specific step is as follows in back end test；
A. the test result of object time parameter is obtained by back end test；
B. the assignment of custom field in CHIPID module, the default tune for the object time parameter being arranged in obtaining step 2 are read
Whole amount；
C. binding test result and default adjustment amount obtain the secondary adjustment amount of object time parameter；
D. according to the obtained corresponding EFUSE of secondary adjustment amount fusing object time parameter, the secondary of object time parameter is completed
Adjustment.
3. the wafer chip time parameter method of adjustment based on wafer position, which is characterized in that include the following steps,
Step 1, the technique that wafer test obtains wafer position from fab or for the first time is distributed, and is obtained on the wafer in all wafers
The technique of time parameter is distributed；
Step 2, it is distributed according to the technique of time parameter in wafer chip, obtains the test knot for needing the object time parameter adjusted
Fruit, and test result is compared with specification requirement value, determine the default adjustment amount of object time parameter；
Step 3, in head end test, the adjustment amount of object time parameter is passed through into CHIPID module in the corresponding wafer chip that fuses
The FUSE of custom field carries out assignment, so that the default adjustment amount of object time parameter is built in making by oneself for CHIPID module
In adopted field；
Step 4, in back end test, the assignment of custom field in CHIPID module, the target being arranged in obtaining step 2 are read
The default adjustment amount of time parameter；According to the obtained corresponding EFUSE of default adjustment amount fusing object time parameter, target is completed
The adjustment of time parameter.
4. the wafer chip time parameter method of adjustment according to claim 1 or 3 based on wafer position, feature exist
In the object time parameter is at least one of tWR time parameter, tRP time parameter and tRCD time parameter.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937835A (en) * | 2010-06-30 | 2011-01-05 | 上海华岭集成电路技术有限责任公司 | Method for modifying parameters for fuse-class wafer |
| CN102520332A (en) * | 2011-12-15 | 2012-06-27 | 无锡中星微电子有限公司 | Wafer testing device and method for the same |
| CN102867765A (en) * | 2012-09-27 | 2013-01-09 | 盛美半导体设备（上海）有限公司 | Detector and detection method for wafer position |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007287770A (en) * | 2006-04-13 | 2007-11-01 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
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2017
- 2017-01-06 CN CN201710010523.8A patent/CN106653640B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937835A (en) * | 2010-06-30 | 2011-01-05 | 上海华岭集成电路技术有限责任公司 | Method for modifying parameters for fuse-class wafer |
| CN102520332A (en) * | 2011-12-15 | 2012-06-27 | 无锡中星微电子有限公司 | Wafer testing device and method for the same |
| CN102867765A (en) * | 2012-09-27 | 2013-01-09 | 盛美半导体设备（上海）有限公司 | Detector and detection method for wafer position |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
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