CN207424736U - A kind of system of automatic calibrating clock frequency - Google Patents
A kind of system of automatic calibrating clock frequency Download PDFInfo
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- CN207424736U CN207424736U CN201720857352.8U CN201720857352U CN207424736U CN 207424736 U CN207424736 U CN 207424736U CN 201720857352 U CN201720857352 U CN 201720857352U CN 207424736 U CN207424736 U CN 207424736U
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Abstract
A kind of system of automatic calibrating clock frequency, including：Chip operation clock is using externally input standard time clock as work clock；Target clock counter is using externally input standard time clock as calibration target clock；Start a wheel calibration, target clock counter starts simultaneously at counting with calibration clock counter, when target clock counter to the object count result for calibrating target clock is N1 when stop, at this point, calibration clock counter is N2 to the calibration count results of internal clock PLL to be calibrated；Target alignment parameter generating unit calculates the absolute value N of the count difference value of N1 and N2, and judges whether N is less than the error Configuration Values N3 of clock calibration error configurator, if N is less than N3, calibrates success, otherwise continues next round calibration；Chip operation clock selector selects the clock to be calibrated of the inside after calibrating successfully as work clock.The utility model further shortens prover time, and by using chip operation clock selector, improves calibration test efficiency.
Description
" technical field "
The utility model is related to technical field of integrated circuits, and in particular to a kind of system of automatic calibrating clock frequency.
" background technology "
In the prior art, in chip there are two types of the signal sources of work clock：It is a kind of be by chip outside quartz crystal shake
Swing device offer, this kind of stable clock signal and accurate, shortcoming is that external quartz crystal oscillator volume is larger, cost is higher；Separately
It is a kind of, it is the clock oscillator by chip internal（PLL）It generates, but due to the limitation of integrated circuit manufacturing process so that
Clock frequency and design standard in chip have certain deviation.With the raising of integrated chipization requirement, the clock source of chip is big
It needs to be integrated into the inside of chip, this requires in chip volume production test session, calibrate clock frequency more.
Traditional clock correcting method is：Change different clock frequency calibration parameters, pass through external testing board, measurement
Internal clock frequencies under each parameter, until reaching in the range of expected clock frequency error.Such calibration method, consumption
Time-consuming longer, testing cost is very high.
For this purpose, the prior art proposes another clock frequency calibration method, this method need not be external to clock frequency
It measures, portion designs a kind of automatic Iterative calibration circuit in the chip.Automatic Iterative calibration circuit includes standard counter
With calibration counter.According to the differences of two counters after every wheel calibration, judge current clock frequency deviation whether
In error range.Then terminate to calibrate in error range, otherwise automatically generate next calibration parameter, carry out next round calibration.
But this kind of method stills need repeated multiple times calibration, and total prover time is still longer.
Application publication number is that the utility model patent of CN103677078A discloses a kind of calibration method of clock frequency, is
System and chip although improving automatic Iterative calibration clock method, shorten prover time, however before calibration terminates, core
Piece does not have the accurate work clock of frequency, can not ensure that chip works normally.This method still expends certain time, in calibration process
In cannot parallel be carried out with other functional tests, it is less efficient.
" utility model content "
To solve problem above, the utility model provides a kind of system of automatic calibrating clock frequency, make chip when
During clock frequency calibration, normal other functional tests are carried out at the same time, substantially increase testing efficiency.The specific skill of the utility model
Art scheme is as follows：
A kind of system of automatic calibrating clock frequency, the system comprises：
Chip operation clock selector, for accessing externally input standard time clock, and when selecting externally input standard
Clock or the internal calibration clock after calibrating successfully are exported as work clock；
Target clock counter, for using the externally input standard time clock as calibration target clock, and to calibration
Target clock is counted, and exports object count result N1 to clock calibration parameters generation unit；
Calibrate clock counter, for being counted to internal clock to be calibrated, and export calibration count results N2 to when
Clock calibration parameter generation unit；
Clock calibration error configurator, for output error Configuration Values N3 to target alignment parameter generating unit；
The target alignment parameter generating unit, for the counting according to object count result N1 and calibration count results N2
The absolute value N of difference, judges whether absolute value N is less than the error Configuration Values N3, if N is less than N3, calibrates success, otherwise
Continue to calibrate.
Further, the system also includes：
Calibration parameter storage unit, for storing the target alignment parameter generating unit finally successful successfully school of calibration
Quasi- parameter, and using successful calibration parameter output as the Configuration Values of internal clock to be calibrated.
Technical solution provided by the utility model further shortens prover time, and passes through creative use chip operation
Before chip internal clock PLL calibrations to be calibrated are not completed, external input clock may be selected as chip operation in clock selector
Clock carries out other functional tests, makes the chip clock frequency calibration no longer independent engaged test time, improves testing efficiency；
In clock calibration process, external provide only is needed to calibrate target clock, has configured clock calibration error, you can be automatically performed chip
The calibration of internal clock PLL to be calibrated, the technical solution is efficiently convenient, and can be automatically performed clock frequency calibration.
" description of the drawings "
Fig. 1 is a kind of method flow diagram of automatic calibrating clock frequency of the utility model.
Fig. 2 is a kind of system architecture diagram of automatic calibrating clock frequency of the utility model.
" specific embodiment "
Specific embodiment of the present utility model is described further below in conjunction with the accompanying drawings：
The method of automatic calibrating clock frequency as shown in Figure 1, the described method comprises the following steps：
Chip operation clock selector accesses externally input standard time clock, and the externally input standard time clock is made
For work clock；
Target clock counter accesses externally input standard time clock, and using the externally input standard time clock as school
Quasi- target clock；
Start a wheel calibration, target clock counter starts simultaneously at counting with calibration clock counter, when the target
Clock counter when the object count result for calibrating target clock is N1 to stopping, at this point, the calibration clock counter is to inside
The calibration count results of clock PLL to be calibrated are N2；
Target alignment parameter generating unit calculates the absolute value N of the count difference value of N1 and N2, and judges whether N is less than clock
The error Configuration Values N3 of calibration error configurator if N is less than N3, calibrates success, otherwise continues next round calibration；
Chip operation clock selector selects the clock to be calibrated of the inside after calibrating successfully as work clock.
Method described in the utility model, the work clock of chip can be inputted and design mesh by target clock interface
The clock of the same frequency of mark；Chip is calibrated without waiting for clock frequency and completed, and can obtain the accurate work clock of frequency.
As long as chip has the accurate work clock of frequency, in the chip while portion's clock alignment, the survey of other functions can be carried out parallel
Examination, testing efficiency greatly improve.
Preferably, it is described continue calibration include：According to the absolute value N of count difference value and configuration calibration count difference value N4,
It calculates often wheel and estimates calibration stepped parameter P1=N/N4, and calibration stepped parameter P1 adjustment lower whorl calibration parameters are estimated according to every wheel
P performs next round calibration.By using calibration stepped parameter is estimated, target alignment parameter can be found quickly, greatly shortens school
Between punctual.
Preferably, the basis, which is often taken turns, estimates calibration stepped parameter P1 adjustment lower whorl calibration parameter P, including：If N1 is big
In N2, then increase the calibration parameter P, make lower whorl calibration parameter P=P+P1；If N1 is less than N2, reduce the calibration ginseng
Number, makes calibration parameter P=P-P1 described in lower whorl.
Preferably, the execution next round calibration, including：Judge whether the calibration parameter P reaches maximum or most
Small value, if reached, and N would be more than N3, then calibrates and fail.
Preferably, the calibration parameter P is equipped with 128 gears, and the frequency deviation of clock of adjacent gear positions is 0.5%, adjustable
Scope is -32% to+32%.Adjustable scope is set, can different devices be selected according to different demands, realize highest
Valency ratio.
Preferably, the limits of error scope that the clock calibration error configurator is configured is 0% to 25%.It sets most
Big allowable error scope can select different devices according to different demands, realize the best price/performance ratio.
Preferably, after described calibrate successfully, the inside after the selection of chip operation clock selector is calibrated successfully is treated
Before clock is calibrated as work clock, further include：Successful successful calibration parameter is finally calibrated in storage, and is exported as calibration
The Configuration Values of internal calibration clock after success.Chip under most accurate work clock is worked, improves core
Piece working performance and work quality.
Preferably, the method further includes：In each electrification reset of chip, read the final of last storage and be calibrated to
The calibration parameter of work(, the Configuration Values as internal clock to be calibrated.
A kind of system of automatic calibrating clock frequency as shown in Figure 2, the system comprises chip operation clock selector,
Target clock counter, calibration clock counter, clock calibration error configurator, clock calibration parameters generation unit, calibration knot
Fruit register and calibration parameter storage unit.
Wherein, chip operation clock selector for accessing externally input standard time clock, and selects externally input mark
Punctual clock or the internal calibration clock after calibrating successfully are exported as work clock.Target clock counter, for inciting somebody to action
The externally input standard time clock is counted as calibration target clock, and to calibration target clock, and exports target meter
Result N1 is counted to clock calibration parameters generation unit.Clock counter is calibrated, based on being carried out to internal clock PLL to be calibrated
Number, and calibration count results N2 is exported to clock calibration parameters generation unit.Clock calibration error configurator, for output error
Configuration Values N3 is to target alignment parameter generating unit.The target alignment parameter generating unit, for according to object count result
The absolute value N of the count difference value of N1 and calibration count results N2, judges whether absolute value N is less than the error Configuration Values N3, such as
Fruit N is less than N3, then calibrates success, otherwise continue to calibrate.Calibration result register, for storing calibration result.Calibration parameter is deposited
Storage unit finally calibrates successful successful calibration parameter for storing the target alignment parameter generating unit, and it is described into
Configuration Values of the work(calibration parameter output as internal clock to be calibrated.
System described in the utility model, the work clock of chip can be inputted and design mesh by target clock interface
The clock of the same frequency of mark；Chip is calibrated without waiting for clock frequency and completed, and can obtain the accurate work clock of frequency.
As long as chip has the accurate work clock of frequency, in the chip while portion's clock alignment, the survey of other functions can be carried out parallel
Examination, testing efficiency greatly improve.
Preferably, target clock counter is 12bit counters, and externally input standard time clock is counted, and calibrates clock
Counter is 13bit counters, and clock PLL to be calibrated to the inside of chip is counted.When starting a wheel calibration, target clock counts
Device and calibration clock counter, start simultaneously at counting, which is simultaneously stopped counting after calibrating.When target clock counter counts
Stop a wheel calibration when counting to N1, calibration clock counter records the count value N2 of wheel calibration simultaneously, calculates the meter of N1 and N2
The absolute value of number difference N.Wherein, N1 can take the maximum count value of 12bit counters, can thus not have to provide additionally
Counter counts the value of N1, so as to reduce hardware cost, reduces data processing difficulty.
Preferably, clock calibration error configurator is 10bit, and Configuration Values N3 can be permitted by the absolute value N of count difference value
Perhaps maximum.Maximum allowable offset scope can match somebody with somebody for 0 to 25%, i.e. maximum allowable offset is 0% during N3=" 0000000000 ",
Maximum allowable offset is 25% during N3=" 1111111111 ".
Preferably, in clock calibration parameters generation unit, calibration parameter P is 7bit, shares 128 gear parameters, initially
Calibration parameter is " 1000000 ", and calibration parameter value is bigger, and PLL frequencies are faster, otherwise slower.Adjacent gear positions parameter clock frequency is inclined
Difference is 0.5%, i.e., calibration accuracy is 0.5%, and adjustable scope is -32% ~+32%.Including adjacent gear positions params-count difference device, use
Adjacent gear positions calibration parameter count difference value is configured, such as adjacent calibration parameter " 1000000 " and " 1000001 " calibrate count difference
Value is configured to N4.Often wheel estimates calibration stepped parameter P1=N/N4（P1 round numbers, minimum 1）.According to target clock counter N1
With calibrating clock counter N2, if N1 shows that PLL is slower than calibration target clock more than N2, calibration parameter should be increased, then lower whorl
Calibration parameter P=P+P1；If N1 shows that PLL is faster than calibration target clock less than N2, calibration parameter should be reduced, then lower whorl is calibrated
Parameter P=P-P1；As a result of calibration stepped parameter is estimated, can be quickly find target alignment parameter, greatly shorten calibration
Time.If P increases to maximum " 1111111 " or is reduced to minimum value " 0000000 ", PLL frequencies reach permission not yet
Error range in, then calibrate and fail, terminate calibration, if P does not increase to maximum " 1111111 " also or is reduced to minimum
It is worth " 0000000 ", if N is less than N3, calibrates success, terminate calibration, otherwise continue to calibrate.
Preferably, calibration result register records calibration result by two flag bits；First mark position 1, characterization
Calibration terminates, the first mark position 0, and characterization calibration does not terminate.Second mark position 1, characterization are calibrated successfully, the second mark position
0, characterization calibration failure.Clock calibration error configurator, for configuring the error range of clock frequency departure.Calibration parameter storage is single
Member can be the memories such as OTP, MTP or EEPROM, and successful successful calibration parameter is finally calibrated for storing.On chip is each
The parameter configuration value of PLL after reset can be read from calibration parameter storage unit.
In conclusion technical solution provided by the utility model further shortens prover time, and made by innovation
With chip operation clock selector, before chip PLL calibrations are not completed, when external input clock may be selected as chip operation
Clock carries out other functional tests, makes the chip clock frequency calibration no longer independent engaged test time, improves testing efficiency；
In clock calibration process, external offer standard time clock is only needed（Target frequency clock）, you can the calibration of chip PLL is automatically performed,
The technical solution is efficiently convenient, and can be automatically performed clock frequency calibration.
Above example is only fully to disclose and unrestricted the utility model, all creation purports based on the utility model,
The replacement of equivalence techniques feature without creative work should be considered as the scope of the application exposure.
Claims (2)
1. a kind of system of automatic calibrating clock frequency, it is characterised in that：The system comprises：
Chip operation clock selector, for accessing externally input standard time clock, and select externally input standard time clock or
Internal calibration clock after person calibrates successfully is exported as work clock；
Target clock counter, for using the externally input standard time clock as calibration target clock, and to calibrate target
Clock is counted, and exports object count result N1 to clock calibration parameters generation unit；
Clock counter is calibrated, for being counted to internal clock to be calibrated, and exports calibration count results N2 to clock school
Quasi- parameter generating unit；
Clock calibration error configurator, for output error Configuration Values N3 to target alignment parameter generating unit；
The target alignment parameter generating unit, for the count difference value according to object count result N1 and calibration count results N2
Absolute value N, judge absolute value N whether be less than the error Configuration Values N3, if N be less than N3, calibrate success, otherwise continue
Calibration.
2. the system of automatic calibrating clock frequency according to claim 1, which is characterized in that the system also includes：
Calibration parameter storage unit finally calibrates successful successful calibration ginseng for storing the target alignment parameter generating unit
Number, and using successful calibration parameter output as the Configuration Values of internal clock to be calibrated.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720857352.8U CN207424736U (en) | 2017-07-14 | 2017-07-14 | A kind of system of automatic calibrating clock frequency |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720857352.8U CN207424736U (en) | 2017-07-14 | 2017-07-14 | A kind of system of automatic calibrating clock frequency |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107219884A (en) * | 2017-07-14 | 2017-09-29 | 珠海市微半导体有限公司 | A kind of method and system of automatic calibrating clock frequency |
| CN112187225A (en) * | 2020-10-09 | 2021-01-05 | 京东方科技集团股份有限公司 | Clock calibration method and device |
| CN107219884B (en) * | 2017-07-14 | 2024-05-03 | 珠海一微半导体股份有限公司 | Method and system for automatically calibrating clock frequency |
-
2017
- 2017-07-14 CN CN201720857352.8U patent/CN207424736U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107219884A (en) * | 2017-07-14 | 2017-09-29 | 珠海市微半导体有限公司 | A kind of method and system of automatic calibrating clock frequency |
| CN107219884B (en) * | 2017-07-14 | 2024-05-03 | 珠海一微半导体股份有限公司 | Method and system for automatically calibrating clock frequency |
| CN112187225A (en) * | 2020-10-09 | 2021-01-05 | 京东方科技集团股份有限公司 | Clock calibration method and device |
| CN112187225B (en) * | 2020-10-09 | 2023-11-03 | 京东方科技集团股份有限公司 | Clock calibration method and device |
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