CN106653578B - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
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- CN106653578B CN106653578B CN201611104653.XA CN201611104653A CN106653578B CN 106653578 B CN106653578 B CN 106653578B CN 201611104653 A CN201611104653 A CN 201611104653A CN 106653578 B CN106653578 B CN 106653578B
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- substrate
- alignment mark
- mark hole
- structural layer
- face
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- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 230000007613 environmental effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract description 33
- 238000000034 method Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a processing method of a wafer, which comprises the steps of carrying out graphical processing on a first end surface of a first substrate to form a structural layer and a photoresist coating, and defining an alignment mark hole on the photoresist coating; etching the structural layer and the first substrate in the region of the alignment mark hole to enable the alignment mark hole to extend to the first substrate; bonding the surface of the first substrate, which is provided with the structural layer, with the second substrate; thinning the second end face of the first substrate, and exposing the alignment mark hole from the second end face of the first substrate; e) and positioning is carried out through the alignment mark hole. Before the two wafers are bonded, an alignment mark hole with a preset depth is embedded in one of the wafers in advance, after the two wafers are bonded, the wafers are processed to a preset thickness through a grinding process, and the alignment mark hole is exposed for secondary positioning, so that the surface of the wafer can be processed with high precision by adopting the original equipment.
Description
Technical Field
The invention relates to a processing method of a wafer.
Background
Wafer (Wafer) refers to a silicon Wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a Wafer because it has a circular shape. The wafer fabrication process and associated fabrication tools may include thermal oxidation, diffusion, ion implantation, Rapid Thermal Processing (RTP), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), epitaxial formation/growth processes, etching processes, photolithography processes, and/or other fabrication processes and tools. When the Wafer is in a state of completing the bonding process of two wafers, if the outer surface of the Wafer needs to be processed, the two wafers must be copied to the outer surface in advance, which is a complicated processing mode, and alignment marks of the Wafer are repeatedly copied to generate multiple alignment errors, so that the precision of the alignment marks cannot meet the processing requirements of precise elements.
Disclosure of Invention
An object of the present invention is to provide a new technical solution for a wafer processing method.
According to a first aspect of the present invention, there is provided a method for processing a wafer, comprising the steps of:
a) carrying out patterning processing on a first end face of a first substrate to form a structural layer, arranging a photoresist coating above the structural layer, and defining an alignment mark hole on the photoresist coating;
b) etching the structural layer and the first substrate in the region of the alignment mark hole to enable the alignment mark hole to extend to the first substrate;
c) bonding the surface of the first substrate, which is provided with the structural layer, with the second substrate;
d) thinning the second end face of the first substrate, and exposing the alignment mark hole from the second end face of the first substrate;
e) and positioning through the alignment mark hole, and carrying out patterning processing on the second end face of the first substrate.
Optionally, in the step b), the alignment mark hole is formed after etching and is a blind hole extending into the first substrate.
Optionally, in the step b), a through hole penetrating through both ends of the first substrate is formed after the alignment mark hole is etched.
Optionally, in the step d), the second end face of the first substrate is thinned by grinding.
According to the manufacturing method, before the two wafers are bonded, the alignment mark hole with the preset depth is embedded in one wafer in advance, after the two wafers are bonded, the wafers are processed to the preset thickness through a grinding process, and the alignment mark hole exposed is used for secondary positioning, so that the surface of the wafer can be processed with high precision by adopting original equipment.
The inventor of the present invention finds that in the prior art, the wafer often needs to be turned over, which is a tedious processing method, and the alignment mark of the wafer is repeatedly printed to generate multiple alignment errors, so that the precision of the alignment mark cannot meet the processing requirement of the precision component. Therefore, the technical task to be achieved or the technical problems to be solved by the present invention are never thought or anticipated by those skilled in the art, and therefore the present invention is a new technical solution.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 to 4 are process flow charts of the processing method of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The invention provides a processing method of a wafer, which is characterized by comprising the following steps:
a) carrying out patterning treatment on a first end face of a first substrate 1 to form a structural layer 2; refer to fig. 1; the first substrate 1 may be a single crystal silicon material well known to those skilled in the art; the structure of the structural layer 2 can be a microphone structure, and can also be structures such as an inertial sensor and an environmental sensor;
arranging a photoresist coating 3 above the structural layer 2, and arranging an alignment mark hole 4 on the photoresist coating 3; for example, photolithography and the like can be used to define the alignment mark hole 4 for positioning on the photoresist coating 3;
b) etching the structural layer 2 and the first substrate 1 in the region of the alignment mark hole 4, so that the alignment mark hole 4 extends to the first substrate 1; etching down to a predetermined depth through the alignment mark hole 4 on the photoresist coating 3, thereby completing the embedding process of the alignment mark hole 4, referring to fig. 2;
c) bonding the side of the first substrate 1 provided with the structural layer 2 to the second substrate 5, with reference to fig. 3; the structural layer 2 on the first substrate 1 and the second substrate 5 may be bonded together, for example, by an adhesive layer 6, which may be, for example, a silicon-silicon bond, or other bonding means known to those skilled in the art;
d) thinning the second end face of the first substrate 1 and exposing the alignment mark hole 4 from the second end face of the first substrate 1, referring to fig. 4; thinning the second end face of the first substrate 1 by grinding, for example, to obtain a first substrate 1 with a predetermined thickness, wherein the alignment mark hole 4 is exposed from the second end face;
e) the second end face of the first substrate 1 is patterned by being positioned through the alignment mark holes 4 located on the second end face.
In the present invention, preferably, in the step b), the alignment mark hole 4 is formed by etching to form a blind hole extending into the first substrate 1, that is, the alignment mark hole 4 does not penetrate through the second end face of the first substrate 1, and the alignment mark hole 4 is exposed from the second end face by the grinding in the subsequent step d).
In another preferred embodiment of the present invention, in the step b), the alignment mark hole 4 is a through hole formed through the first substrate 1 after etching, that is, the alignment mark hole 4 penetrates through both ends of the first substrate 1; step d) only requires that the second end face of the first substrate 1 is ground to a predetermined thickness.
According to the manufacturing method, before the two wafers are bonded, the alignment mark hole with the preset depth is embedded in one wafer in advance, after the two wafers are bonded, the wafers are processed to the preset thickness through a grinding process, and the alignment mark hole exposed is used for secondary positioning, so that the surface of the wafer can be processed with high precision by adopting original equipment.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (2)
1. A processing method of a wafer is characterized by comprising the following steps:
a) carrying out patterning processing on a first end face of a first substrate (1) to form a structural layer (2), arranging a photoresist coating (3) above the structural layer (2), and defining an alignment mark hole (4) on the photoresist coating (3);
the structure of the structural layer (2) is a microphone structure, an inertial sensor or an environmental sensor;
b) etching the structural layer (2) and the first substrate (1) in the region of the alignment mark hole (4) so that the alignment mark hole (4) extends to the first substrate (1);
in the step b), the alignment mark hole (4) is a through hole which is formed after etching and penetrates through two end faces of the first substrate (1);
c) the first substrate (1) with the structural layer (2) is arranged below the second substrate (5), and the structural layer (2) of the first substrate (1) is bonded with the second substrate (5) through a bonding layer (6), wherein the bonding is a silicon-silicon bonding mode;
d) thinning the second end face of the first substrate (1), and exposing the alignment mark hole (4) from the second end face of the first substrate (1);
e) and positioning through the alignment mark hole (4) to perform patterning processing on the second end face of the first substrate (1).
2. The processing method according to claim 1, characterized in that: and in the step d), the second end face of the first substrate (1) is thinned in a grinding mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611104653.XA CN106653578B (en) | 2016-12-05 | 2016-12-05 | Wafer processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611104653.XA CN106653578B (en) | 2016-12-05 | 2016-12-05 | Wafer processing method |
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| Publication Number | Publication Date |
|---|---|
| CN106653578A CN106653578A (en) | 2017-05-10 |
| CN106653578B true CN106653578B (en) | 2020-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611104653.XA Active CN106653578B (en) | 2016-12-05 | 2016-12-05 | Wafer processing method |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113488394B (en) * | 2021-07-08 | 2022-08-12 | 湖北三维半导体集成制造创新中心有限责任公司 | Wafer bonding method and system |
| CN116544181B (en) * | 2023-07-07 | 2023-11-28 | 长鑫存储技术有限公司 | Semiconductor packaging method and semiconductor packaging structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223391A (en) * | 1999-01-28 | 2000-08-11 | Sharp Corp | Manufacture of semiconductor device |
| CN1510522A (en) * | 2002-12-20 | 2004-07-07 | Asml | Device manufacturing method |
| CN103035518A (en) * | 2012-05-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of insulated gate bipolar transistor wafer |
| CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
-
2016
- 2016-12-05 CN CN201611104653.XA patent/CN106653578B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000223391A (en) * | 1999-01-28 | 2000-08-11 | Sharp Corp | Manufacture of semiconductor device |
| CN1510522A (en) * | 2002-12-20 | 2004-07-07 | Asml | Device manufacturing method |
| CN103035518A (en) * | 2012-05-09 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of insulated gate bipolar transistor wafer |
| CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
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| Publication number | Publication date |
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| CN106653578A (en) | 2017-05-10 |
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Effective date of registration: 20200609 Address after: 266104 room 103, 396 Songling Road, Laoshan District, Qingdao, Shandong Province Patentee after: Goer Microelectronics Co.,Ltd. Address before: 261031 Dongfang Road, Weifang high tech Development Zone, Shandong, China, No. 268 Patentee before: GOERTEK Inc. |
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