CN106645855B - A method of eliminating four-way digital three-dimensional waveform randomized jitter - Google Patents
A method of eliminating four-way digital three-dimensional waveform randomized jitter Download PDFInfo
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- CN106645855B CN106645855B CN201610911269.4A CN201610911269A CN106645855B CN 106645855 B CN106645855 B CN 106645855B CN 201610911269 A CN201610911269 A CN 201610911269A CN 106645855 B CN106645855 B CN 106645855B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses it is a kind of eliminate four-way digital three-dimensional waveform randomized jitter method, using channel 1,2 Wave datas synchronization signal Sync_sig1 as reference data, eliminate channel 3,4 waveform randomized jitter；Concretely, first with synchronization signal Sync_sig1 and Sync_sig2 clock signal Sync_clk_R synchronous lower generation time interval signal Sync_interval, clock signal Sync_clk_R is recycled to count time interval signal Sync_interval, obtain the time that Wave data Wave_dat1 is ahead of Wave_dat2, the time is recycled to carry out delay adjustment to Wave data Wave_dat1, and final received clock signal Sync_sig_R is set by the synchronization signal Sync_sig2 of Wave data Wave_dat2, realize the reception of two-way Wave data, to eliminate channel 3, 4 waveform randomized jitter.
Description
Technical field
The invention belongs to digital oscilloscope technical fields, more specifically, are related to a kind of elimination four-way digital three-dimensional
The method of waveform randomized jitter.
Background technique
By it, rapidly and efficiently parallel processing architecture realizes that the waveform for obtaining multi collect carries out to digital three-dimensional oscillograph
Multiple stacking, the number that real-time tracer signal occurs in different amplitudes and moment position, by this information according to certain when display
Proportional relationship is converted into the luminance information of waveform color on liquid crystal display.Therefore, user is when operating digital three-dimensional oscilloscope
It is general can to judge that input signal occurs in certain amplitudes or moment position by the depth of display waveform color on screen
Rate.
In digital three-dimensional oscillograph as shown in Figure 1, analog signal is passed through after signal condition channel, is sampled by ADC,
And sampling is exported in deposit acquisition memory.After memory, which stores, to be completed, i.e., after completion one acquisition, by memory
Stored data is sequential read out, and sampled data is mapped to Wave data corresponding with LCD screen dot matrix in parallel coprocessor
Library starts the acquisition and mapping of a new round again after the completion of mapping.It is real-time in waveform database by multi collect and mapping
Cumulative time for having recorded input signal and occurring in different amplitudes and moment position (or in waveform database difference storage unit)
Number；At the same time, microprocessor carries out the work such as waveform operation, menu management and human-computer interaction.When arrival liquid crystal display timing
When refresh time, waveform database is transferred in display-memory wave regions, so by starting display refresh control logic automatically
Liquid crystal display is sent to after being combined with the menu data in display-memory menu area afterwards to show.
It is partially the core of digital three-dimensional oscillograph in Fig. 1 dotted line frame, implementation process is as shown in Figure 2.All streams in Fig. 2
Cheng Jun is realized in a FPGA, wherein timing signal is issued by microprocessor.In a complete software period, when micro- place
Reason device is completed a series of such as waveform operations, menu management and human-computer interaction operation and has been updated in video memory in menu area
Rong Shi can issue timing signal to FPGA.It, can be in currently acquisition waveform mapping completion when FPGA receives the timing signal
Afterwards, information all in waveform database are transferred in video memory wave regions in such a way that address is incremented by, after the completion of to be sent,
It is read and is shown by liquid crystal display.
In two oscilloscope channels, due to being realized in a piece of FPGA, regardless of currently being mapped for point mapping or vector, two
The acquisition and mapping in a channel synchronously complete.After timing signal arrives, respective waveform database data are started simultaneously at
Transmission, two paths of data is a circuit-switched data according to certain ruled synthesis at video memory end, and is stored in video memory wave regions.
However in four-way digital oscilloscope, since the demands such as I/O resource, logical resource double, more FPGA cores are needed
Piece completes the acquisition and display of four-way, and the acquisition in four channels can not be synchronously completed with mapping.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of elimination four-way digital three-dimensional oscillograph waves
The method of shape randomized jitter controls acquiring and synchronous, the Jin Eryou of mapping for four channels by setting clock sync signal
Effect eliminates the randomized jitter of waveform on display screen.
For achieving the above object, the method that the present invention eliminates four-way digital three-dimensional waveform randomized jitter,
Characterized by comprising the following steps:
(1), start four-way digital three-dimensional oscillograph, four channels are shown it is fully open, on a display screen with channel
1, the synchronization signal Sync_sig1 of 2 Wave datas is reference data, and whether the waveform in observation channel 3,4 will appear randomized jitter,
If the waveform in channel 3,4 is beated, (2) are entered step, are otherwise remained unchanged；
(2), the waveform randomized jitter on display screen is eliminated
(2.1), using the clock signal Sync_clk_R of identical frequency synchronous receiving channel 1,2 Wave data Wave_
The synchronization signal Sync_sig1 and Sync_sig2 of dat1 and channel 3,4 Wave data Wave_dat2 and the two；
(2.2), using synchronization signal Sync_sig1 and Sync_sig2 in the synchronous lower generation of clock signal Sync_clk_R
Time interval signal Sync_interval between the two rising edge；
(2.3), time interval signal Sync_interval is counted using clock signal Sync_clk_R, is obtained
Count value is M, i.e. the time that Wave data Wave_dat1 is ahead of Wave_dat2 is MT, wherein T indicates clock signal
The period of Sync_clk_R；
(2.4), according to the M value counted to get, delay adjustment is carried out to Wave data Wave_dat1, i.e., by Wave_dat1
Postpone M clock signal Sync_clk_R period, to guarantee that Wave data Wave_dat1 and Wave data Wave_dat2 are complete
Alignment；
(2.5), final received clock signal is set by the synchronization signal Sync_sig2 of Wave data Wave_dat2
Sync_sig_R, then realize the reception of two-way Wave data, and be sent to display screen and show.
Goal of the invention of the invention is achieved in that
A kind of method for eliminating four-way digital three-dimensional waveform randomized jitter of the present invention, with channel 1,2 waveform numbers
According to synchronization signal Sync_sig1 be reference data, eliminate channel 3,4 waveform randomized jitter；Concretely, first with synchronization
The synchronous lower generation time interval signal Sync_ of signal Sync_sig1 and Sync_sig2 in clock signal Sync_clk_R
Interval recycles clock signal Sync_clk_R to count time interval signal Sync_interval, obtains waveform
Data Wave_dat1 is ahead of the time of Wave_dat2, and the time is recycled to carry out delay tune to Wave data Wave_dat1
It is whole, and final received clock signal Sync_sig_ is set by the synchronization signal Sync_sig2 of Wave data Wave_dat2
R realizes the reception of two-way Wave data, to eliminate the waveform randomized jitter in channel 3,4.
Meanwhile a kind of method for eliminating four-way digital three-dimensional waveform randomized jitter of the present invention also has and following has
Beneficial effect:
(1), the present invention realizes that structure is simple, does not need to increase additional hardware chip, can be in existing hardware platform base
It is upper to can be realized by the programming of simple hardware identification code.
(2), the present invention can substantially eliminate four-way digital three-dimensional waveform randomized jitter.Pass through accurate detection in real time
Delay time between the two-way Wave data not homologous from two, and dynamic adjustment two-way Wave data on this basis
Between time unifying relationship.Between being adjusted, two-way Wave data remains alignment, trembles at random to eliminate waveform
It is dynamic.
Detailed description of the invention
Fig. 1 is two channel number word oscilloscope architecture block diagrams；
Fig. 2 is the work flow diagram of two channel number word oscillographs；
Fig. 3 is four-way digital oscilloscope FPGA structure figure；
Fig. 4 is four-way digital oscilloscope structural block diagram；
Fig. 5 is four-way Wave data transmission time sequence figure；
Fig. 6 is synchronization signal rising time interval measurement timing diagram；
Fig. 7 is four-way Wave data dynamic adjustment schematic diagram.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 3 is four-way digital three-dimensional oscilloscope architecture block diagram of the present invention.
In the present embodiment, four-way digital three-dimensional oscillograph is using 3 FPGA structures as shown in Figure 3, wherein
FPGA1 is identical as FPGA2 model, is each responsible for the acquisition and mapping in channel 1,2 and channel 3,4, FPGA3 be responsible for receiving from
Video memory is written in the Wave data in four channels after synthesis, and controls the display function of liquid crystal display.
The total trigger signal of system is generated by FPGA1, and is sent to the signal acquisition in synchronous four channels FPGA2.Micro process
Device issues timing signal, FPGA1 and FPGA2 and starts each channel Wave data after the mapping for completing current acquisition waveform
Wave data in library is transferred in video memory with identical synchronised clock frequency.Since the input waveform in each channel may be different
Sample, therefore the current acquisition mapping of FPGA1 and FPGA2 is not to be completed at the same time.In order to which waveform is shown normally, it is necessary to FPGA1
It all completes just to start Wave data transmission with currently acquisition mapping in FPGA2.As shown in figure 3, setting F1 and F2 respectively indicates timing
Signal is completed in the mapping for currently acquiring waveform to rear FPGA1 and FPGA2, and total completion signal F=F1&F2 is generated in FPGA1,
And it is sent in FPGA2.Therefore, two panels FPGA will can just start respective Wave data transmission until F is effective.Consider
The influence of signal transmission delay between FPGA, it is effective that FPGA1 may determine F prior to FPGA2, to first start Wave data biography
It is defeated.Therefore, when receiving this two paths of data in FPGA3, since there are the time differences, no matter using from FPGA1 or FPGA2
Synchronization signal synchronize reception two paths of data, all two-way Wave data can be caused not to be aligned.
Below with reference to Fig. 4, the method for eliminating four-way digital three-dimensional waveform randomized jitter a kind of to the present invention into
Row is described in detail, specifically includes the following steps:
(1), start four-way digital three-dimensional oscillograph, four channels are shown it is fully open, on a display screen with channel
1, the synchronization signal Sync_sig1 of 2 Wave datas is reference data, and whether the waveform in observation channel 3,4 will appear randomized jitter,
If the waveform in channel 3,4 is beated, (2) are entered step, are otherwise remained unchanged；
In the present embodiment, when Wave data transmits according to figure 5, channel 1,2 can be observed on a display screen
Waveform keeps stablizing display, and the waveform in channel 3,4 then will appear randomized jitter；Its reason is channel 1,2 in design process
Wave data time upper advanced channel 3,4 Wave datas, while the delay between two-way Wave data is random.
(2), the waveform randomized jitter on display screen is eliminated
(2.1), using the clock signal Sync_clk_R of identical frequency synchronous receiving channel 1,2 Wave data Wave_
The synchronization signal Sync_sig1 and Sync_sig2 of dat1 and channel 3,4 Wave data Wave_dat2 and the two；
(2.2), as shown in fig. 6, using synchronization signal Sync_sig1 and Sync_sig2 in clock signal Sync_clk_R
The lower time interval signal Sync_interval generated between the two rising edge is synchronized, i.e., when signal Sync_sig1 is high electricity
It is flat, while when Sync_sig2 is low level, otherwise it is low that Sync_interval is effectively high in vain；
(2.3), time interval signal Sync_interval is counted using clock signal Sync_clk_R, is obtained
Count value is M, i.e. the time that Wave data Wave_dat1 is ahead of Wave_dat2 is MT, wherein T indicates clock signal
The period of Sync_clk_R；
In the present embodiment, as shown in fig. 6, system resets count value, is working as after last Wave data finishes receiving
In preceding Wave data receive process and when Sync_interval is high level, to the rising edge meter of clock signal Sync_clk_R
Number often carrys out a rising edge, and count value stops counting when 1, Sync_interval being added to be low, and obtaining count value is M.M is wave
The clock signal Sync_clk_R number of cycles of the advanced Wave_dat2 of graphic data Wave_dat1.
(2.4), according to the M value counted to get, delay adjustment is carried out to Wave data Wave_dat1, i.e., by Wave_dat1
Postpone M clock signal Sync_clk_R period, to guarantee that Wave data Wave_dat1 and Wave data Wave_dat2 are complete
Alignment；
In the present embodiment, as shown in fig. 7, the time of the advanced Wave_dat2 of Wave data Wave_dat1 is M clock
The signal Sync_clk_R period.In order to synchronize the display of the two, elimination channel 3,4 shows random relative to channel 1,2 waveforms
Bounce is receiving clock Sync_clk_R control according to the delay count value M between the two-way Wave data measured in (2.3)
Under, Wave data Wave_dat1 is postponed into M clock Sync_clk_R period, to realize the perfectly aligned of two-way Wave data.
(2.5), final received clock signal is set by the synchronization signal Sync_sig2 of Wave data Wave_dat2
Sync_sig_R, then realize the reception of two-way Wave data, and be sent to display screen and show.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (3)
1. a kind of method for eliminating four-way digital three-dimensional waveform randomized jitter, which comprises the following steps:
(1), start four-way digital three-dimensional oscillograph, four channels are shown it is fully open, on a display screen with channel 1,2 waves
The synchronization signal Sync_sig1 of graphic data is reference data, and whether the waveform in observation channel 3,4 will appear randomized jitter, if
The waveform in channel 3,4 is beated, then enters step (2), otherwise remain unchanged；
(2), the waveform randomized jitter on display screen is eliminated
(2.1), using the synchronous receiving channel 1 of the clock signal Sync_clk_R of identical frequency, 2 Wave data Wave_dat1 and
Channel 3,4 Wave data Wave_dat2 and Wave_dat1 and Wave_dat2 synchronization signal Sync_sig1 and Sync_
sig2；
(2.2), using synchronization signal Sync_sig1 and Sync_sig2 in both synchronous lower generations of clock signal Sync_clk_R
Time interval signal Sync_interval between rising edge；
(2.3), time interval signal Sync_interval is counted using clock signal Sync_clk_R, is counted
Value is M, i.e. the time that Wave data Wave_dat1 is ahead of Wave_dat2 is MT, wherein T indicates clock signal Sync_
The period of clk_R；
(2.4), according to the M value counted to get, delay adjustment is carried out to Wave data Wave_dat1, i.e., is postponed Wave_dat1
The M clock signal Sync_clk_R period, to guarantee that Wave data Wave_dat1 and Wave data Wave_dat2 are perfectly aligned；
(2.5), final received clock signal Sync_ is set by the synchronization signal Sync_sig2 of Wave data Wave_dat2
Sig_R, then realize the reception of two-way Wave data, and be sent to display screen and show.
2. a kind of method for eliminating four-way digital three-dimensional waveform randomized jitter according to claim 1, special
Sign is, the generation method of the time interval signal Sync_interval are as follows:
When clock Sync_clk_R to when, if signal Sync_sig1 is high level, while when Sync_sig2 is low level,
Then Sync_interval is that high level is effective, otherwise effective for low level.
3. a kind of method for eliminating four-way digital three-dimensional waveform randomized jitter according to claim 1, special
Sign is, in the step (2.3), is carried out using clock signal Sync_clk_R to time interval signal Sync_interval
, after last Wave data finishes receiving the method for counting are as follows: 1), system resets count value；2) it, is connect in current form data
During receipts and when Sync_interval is high level, the rising edge of clock signal Sync_clk_R is counted, is often come on one
Edge is risen, count value stops counting when 1, Sync_interval being added to be low level.
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| US4974167A (en) * | 1989-02-28 | 1990-11-27 | Tektronix, Inc. | Erasable data acquisition and storage instrument |
| US20060176151A1 (en) * | 2005-02-07 | 2006-08-10 | Lecroy Corporation | Pattern trigger in a coherent timebase |
| CN101136737A (en) * | 2007-07-16 | 2008-03-05 | 中兴通讯股份有限公司 | System and method for eliminating long line transmission time delay of source synchronizing signal |
| CN102435809A (en) * | 2011-10-12 | 2012-05-02 | 秦轲 | Multi-channel digital oscilloscope and signal synchronization method thereof |
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