CN106611582A

CN106611582A - Shift register, grid driving circuit, display panel and driving method

Info

Publication number: CN106611582A
Application number: CN201710135056.1A
Authority: CN
Inventors: 王梓轩; 王飞; 陈宇霆
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2017-03-08
Filing date: 2017-03-08
Publication date: 2017-05-03
Also published as: US20190066559A1; WO2018161523A1; US10593245B2

Abstract

The invention relates to a shift register, a grid driving circuit, a display panel and a driving method. The shift register comprises an input circuit, a reset circuit, an output circuit and an output pull-down circuit, wherein the input circuit is connected with a pull-up node and an input signal end; the reset circuit is connected with the pull-up node, a reset signal end and a first power end to receive a first power supply voltage; the output circuit is connected with the pull-up node, a clock signal end and an output end; and the output pull-down circuit is connected with the output end, and configured as an output end in which a second power supply voltage is written. The first power supply voltage is different from the second power supply voltage. The shift register, the grid driving circuit, the display panel and the driving method can be used to improve the circuit stability.

Description

Shift register, gate driver circuit, display floater and driving method

Technical field

Embodiment of the disclosure is related to a kind of shift register, gate driver circuit, display floater and driving method.

Background technology

With developing rapidly for Display Technique, direction of the display floater increasingly towards high integration and low cost is developed. Gate driver circuit substrate (Gate-driver on Array, GOA) technology is by photoetching process that gate driver circuit is straight Connect on the array base palte for being integrated in display device, GOA circuits generally include the shift register of multiple cascades, each shift LD Device corresponds to a line grid line (for example, each shift register provides scanning drive signal to a line grid line), to realize to showing The turntable driving of panel.This integrated technology can save the binding of grid integrated circuits (Integrated Circuit, IC) (Bonding) region and the space in (Fan-out) region is fanned out to, so as to realize the narrow frame of display floater, while can drop Low product cost, the yield for improving product.

The reliability of GOA directly influences the reliability of display floater, therefore, how to improve the reliability of GOA also becomes One of emphasis of research.

The content of the invention

Embodiment of the disclosure provides a kind of shift register, including：Input circuit, with pull-up node and input signal end Connect respectively；Reset circuit, is connected respectively to receive the first power supply with the pull-up node, reset signal end and the first power end Voltage；Output circuit, is connected respectively with the pull-up node, clock signal terminal and outfan；And output pull-down circuit, with institute State outfan connection, be configured to for second source voltage to write the outfan, wherein, first supply voltage with it is described Second source voltage is different.

For example, in the shift register that the embodiment of the present disclosure is provided, the output circuit includes storage capacitance and first Transistor, the first pole of the first transistor is connected with clock signal terminal, the control pole of the first transistor with it is described on Draw node connection, the second pole of the first transistor is connected with the outfan, the first end of the storage capacitance with it is described Pull-up node connects, and the second end of the storage capacitance is connected with the outfan.

For example, in the shift register that the embodiment of the present disclosure is provided, the input circuit includes transistor seconds, described First pole of transistor seconds is connected with the input signal end, the control pole of the transistor seconds and the input signal end Connection, the second pole of the transistor seconds is connected with the pull-up node；The reset circuit includes third transistor, described First pole of third transistor is connected with the pull-up node, and the control pole of the third transistor connects with the reset signal end Connect, the second pole of the third transistor is connected with first power end.

For example, in the shift register that the embodiment of the present disclosure is provided, the output pull-down circuit is included under the first output Pull transistor, the first pole of the first output pull-down transistor is connected with the outfan, crystal pulling under first output The control pole of pipe is connected with the reset signal end, and the second pole of the first output pull-down transistor is connected with second source end To receive second source voltage.

For example, the shift register that the embodiment of the present disclosure is provided, also including the first pull-down control circuit, wherein, it is described defeated Go out pull-down circuit including the first output pull-down transistor, the first pole of the first output pull-down transistor connects with the outfan Connect, the control pole of the first output pull-down transistor is connected with first pull-down control circuit, first output is drop-down Second pole of transistor is configured to receive the second source voltage；First pull-down control circuit is configured to control institute State the opening and closing of the first output pull-down transistor.

For example, in the shift register that the embodiment of the present disclosure is provided, first pull-down control circuit includes that first is sub Control circuit and the second sub- control circuit, the first sub- control circuit and the 3rd power end, the first pull-down node and described Second sub- control circuit connects respectively, the second sub- control circuit and the pull-up node, first pull-down node and First power end connects respectively.

For example, in the shift register that the embodiment of the present disclosure is provided, the first sub- control circuit includes the first control Transistor and the second controlling transistor, the second sub- control circuit includes the 3rd controlling transistor and the 4th controlling transistor, The control pole of the first output pull-down transistor is connected with first pull-down node；The first of first controlling transistor Pole is connected with the 3rd power end, and the control pole of first controlling transistor is connected with the 3rd power end, and described Second pole of one controlling transistor is connected with primary nodal point；First pole of second controlling transistor and the 3rd power end Connection, the control pole of second controlling transistor is connected with the primary nodal point, the second pole of second controlling transistor It is connected with first pull-down node；First pole of the 3rd controlling transistor is connected with first pull-down node, described The control pole of the 3rd controlling transistor is connected with the pull-up node, second pole and described first of the 3rd controlling transistor Power end connects；First pole of the 4th controlling transistor is connected with the primary nodal point, the 4th controlling transistor Control pole is connected with the pull-up node, and the second pole of the 4th controlling transistor is connected with first power end.

For example, the shift register that the embodiment of the present disclosure is provided, also including the second pull-down control circuit, wherein, it is described defeated Going out pull-down circuit also includes the second output pull-down transistor, the first pole of the second output pull-down transistor and the outfan Connection, the control pole of the second output pull-down transistor is connected with second pull-down control circuit, under second output Second pole of pull transistor is configured to receive the second source voltage；Second pull-down control circuit is configured to control The opening and closing of the second output pull-down transistor.

For example, in the shift register that the embodiment of the present disclosure is provided, first pull-down control circuit includes that first is sub Control circuit and the second sub- control circuit, second pull-down control circuit includes the 3rd sub- control circuit and the 4th son control electricity Road, the first sub- control circuit and the first power supply signal end, the first pull-down node and the second sub- control circuit difference Connection, the second sub- control circuit is distinguished with the pull-up node, first pull-down node and first power end Connection, the 3rd sub- control circuit and second source signal end, the second pull-down node and the 4th sub- control circuit point Do not connect, the 4th sub- control circuit and the pull-up node, second pull-down node and first power end divide Do not connect.

For example, in the shift register that the embodiment of the present disclosure is provided, the first sub- control circuit includes the first control Transistor and the second controlling transistor, the second sub- control circuit includes the 3rd controlling transistor and the 4th controlling transistor, The 3rd sub- control circuit includes the 5th controlling transistor and the 6th controlling transistor, and the 4th sub- control circuit includes the Seven controlling transistors and the 8th controlling transistor, the control pole and first pull-down node of the first output pull-down transistor Connection, the second pole of the first output pull-down transistor is connected to receive second source letter with the second source signal end Number；First pole of first controlling transistor is connected to receive the first power supply signal with the first power supply signal end, and described first The control pole of controlling transistor is connected to receive first power supply signal, first control with the first power supply signal end Second pole of transistor is connected with primary nodal point；First pole of second controlling transistor connects with the first power supply signal end Connect to receive first power supply signal, the control pole of second controlling transistor is connected with the primary nodal point, described Second pole of two controlling transistors is connected with the first pull-down node；Under first pole and described first of the 3rd controlling transistor Node connection, the control pole of the 3rd controlling transistor is drawn to be connected with the pull-up node, the 3rd controlling transistor Second pole is connected to receive first supply voltage with the first power end；First pole of the 4th controlling transistor with it is described Primary nodal point connects, and the control pole of the 4th controlling transistor is connected with the pull-up node, the 4th controlling transistor The second pole be connected to receive first supply voltage with first power end；The control of the second output pull-down transistor Pole processed is connected with second pull-down node, second pole and the first power supply signal end of the second output pull-down transistor Connect to receive first power supply signal；First pole of the 5th controlling transistor is connected with the second source signal end To receive the second source signal, the control pole of the 5th controlling transistor is connected to connect with the second source signal end The second source signal is received, the second pole of the 5th controlling transistor is connected with secondary nodal point；The 6th control crystal First pole of pipe is connected to receive the second source signal with the second source signal end, the 6th controlling transistor Control pole is connected with the secondary nodal point, and the second pole of the 6th controlling transistor is connected with the second pull-down node；Described First pole of seven controlling transistors is connected with second pull-down node, the control pole of the 7th controlling transistor with it is described on Node connection is drawn, the second pole of the 7th controlling transistor is connected to receive first supply voltage with the first power end； First pole of the 8th controlling transistor is connected with the secondary nodal point, the control pole of the 8th controlling transistor with it is described Pull-up node connects, and the second pole of the 8th controlling transistor is connected to receive first power supply with first power end Voltage；First power supply signal and second source signal reverse signal each other, first power supply signal and described Voltage when two power supply signals are low level signal is the second source voltage.

For example, the shift register that the embodiment of the present disclosure is provided, also including pull-up node pull-down circuit, with the pull-up section Point, first pull-down node, second pull-down node and first power end connect respectively.

For example, in the shift register that the embodiment of the present disclosure is provided, the pull-up node pull-down circuit is included under first Pull transistor and the second pull-down transistor, the first pole of first pull-down transistor is connected with the pull-up node, and described The control pole of one pull-down transistor is connected with second pull-down node, the second pole of first pull-down transistor and described One power end connects to receive first supply voltage；First pole of second pull-down transistor connects with the pull-up node Connect, the control pole of second pull-down transistor is connected with first pull-down node, the second of second pull-down transistor Pole is connected to receive first supply voltage with first power end.

Embodiment of the disclosure also provides a kind of gate driver circuit, including the displacement that disclosure any embodiment is provided is posted Storage.

For example, the gate driver circuit of embodiment of the present disclosure offer, including multiple disclosure any embodiments of cascade is carried For shift register, wherein, in addition to the first order and afterbody shift register, the input signal of this grade of shift register End is connected with the outfan of upper level shift register；The reset signal end of this grade of shift register and next stage shift register Outfan connection.

Embodiment of the disclosure also provides a kind of display floater, including the raster data model electricity that disclosure any embodiment is provided Road.

Embodiment of the disclosure also provides a kind of driving method of the shift register that disclosure any embodiment is provided, bag Include：First supply voltage is write into the pull-up node；And the second source voltage is write into the outfan, its In, first supply voltage is different from the second source voltage.

Description of the drawings

In order to be illustrated more clearly that the technical scheme of the embodiment of the present disclosure, below will be in embodiment or description of Related Art The required accompanying drawing for using is briefly described, it should be apparent that, drawings in the following description merely relate to some of the disclosure Embodiment, restriction not of this disclosure.

Fig. 1 is a kind of one of schematic diagram of shift register that the embodiment of the present disclosure is provided；

Fig. 2 is the two of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 3 is the three of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 4 is the four of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 5 is the five of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 6 is the six of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 7 is the seven of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 8 is the eight of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Fig. 9 is the nine of the schematic diagram of a kind of shift register that the embodiment of the present disclosure is provided；

Figure 10 is a kind of driver' s timing figure of shift register that the embodiment of the present disclosure is provided；

Figure 11 is a kind of schematic diagram of gate driver circuit that the embodiment of the present disclosure is provided；

Figure 12 is a kind of schematic diagram of display floater that the embodiment of the present disclosure is provided；And

Figure 13 is a kind of flow chart of the driving method of shift register that the embodiment of the present disclosure is provided.

Specific embodiment

Below in conjunction with accompanying drawing, the technical scheme in the embodiment of the present disclosure is clearly and completely described with reference to attached The non-limiting example embodiment for illustrating in figure and describing in detail in the following description, the example for being more fully described below the disclosure is implemented Example and their various features and Advantageous details.It should be noted that the feature illustrated in figure is not required to be drawn to scale.This The open description for eliminating known materials, component and Technology, so as to the example embodiment for not making the disclosure is obscured.It is given Example be only intended to the enforcement for being conducive to understanding disclosure example embodiment, and further enable those skilled in the art real Apply example embodiment.Thus, these examples are understood not to the restriction of the scope of embodiment of this disclosure.

Unless otherwise specifically defined, the technical term or scientific terminology that the disclosure is used should be disclosure art The ordinary meaning that the interior personage with general technical ability is understood." first ", " second " and similar word used in the disclosure Language is not offered as any order, quantity or importance, and is used only to distinguish different ingredients.Additionally, in the disclosure In each embodiment, same or similar reference number represents same or similar component.

Embodiment of the disclosure provides a kind of shift register 100, as shown in figure 1, the shift register 100 includes input Circuit 110, reset circuit 120, output circuit 130 and output pull-down circuit 140.Input circuit 110 and pull-up node PU and defeated Enter signal end INPUT to connect respectively；Reset circuit 120 and pull-up node PU, reset signal end RESET and the first power end LVSS1 connects respectively, and the first power end LVSS1 is configured to supply the first supply voltage VSS1；Output circuit 130 and pull-up section Point PU, clock signal terminal CLK and outfan OUTPUT connect respectively；Output pull-down circuit 140 is connected with outfan OUTPUT, defeated Go out pull-down circuit 140 to be configured to for second source voltage VSS2 to write outfan OUTPUT.First supply voltage VSS1 and Two supply voltage VSS2 are different.

For example, as shown in Fig. 2 in the shift register 100 that the embodiment of the present disclosure is provided, output circuit 130 includes depositing Storing up electricity holds C and the first transistor T1.First pole of the first transistor T1 is connected with clock signal terminal CLK, the first transistor T1's Control pole is connected with pull-up node PU, and second pole of the first transistor T1 is connected with outfan OUTPUT, and the first of storage capacitance C End is connected with pull-up node PU, and the second end of storage capacitance C is connected with outfan OUTPUT.

For example, the grid of the control extremely transistor of the transistor described in the embodiment of the present disclosure.

It should be noted that the transistor adopted in embodiment of the disclosure can be that thin film transistor (TFT) or field effect are brilliant Body pipe or other characteristic identical switching devices.The source electrode of the transistor for adopting here, drain electrode can be in structure it is symmetrical, So its source electrode, drain electrode can be not different in structure.In embodiment of the disclosure, in order to distinguish transistor except grid The two poles of the earth outside pole, directly describe wherein one extremely the first pole, another extremely the second pole, so in the embodiment of the present disclosure all Or first pole and the second pole of portion of transistor can be as needed exchange.For example, the crystal described in the embodiment of the present disclosure The first of pipe extremely can be source electrode, and second can be extremely drain electrode；Or, the first of transistor extremely drains, the second extremely source electrode. Additionally, distinguishing and transistor can be divided into into N-type and P-type transistor according to the characteristic of transistor.When transistor is P-type transistor When, cut-in voltage is low level voltage (for example, 0V, -5V), and closing voltage is high level voltage (for example, 5V, 10V)；Work as crystal Manage for N-type transistor when, cut-in voltage be high level voltage (for example, 5V, 10V), close voltage be low level voltage (for example, 0V、-5V)。

For example, when the first transistor T1 is N-type transistor, the first supply voltage VSS1 is less than second source voltage VSS2.Again for example, when the first transistor T1 is N-type transistor, the first supply voltage VSS1 is -11V, and second source is electric Pressure VSS2 is -8V.Embodiment of the disclosure includes but is not limited to this, the first supply voltage VSS1 and second source voltage VSS2 Can also be other magnitudes of voltage, as long as the first supply voltage VSS1 is less than second source voltage VSS2.

For example, when the first transistor T1 is P-type transistor, the first supply voltage VSS1 is more than second source voltage VSS2.Again for example, when the first transistor T1 is P-type transistor, the first supply voltage VSS1 is -8V, and second source is electric Pressure VSS2 is -11V.Embodiment of the disclosure includes but is not limited to this, the first supply voltage VSS1 and second source voltage VSS2 can also be other magnitudes of voltage, as long as the first supply voltage VSS1 is more than second source voltage VSS2.

In some cases, when the threshold voltage shift of the first transistor T1 is to less than or equal to 0V, the first transistor T1 Raceway groove in the presence of its grid voltage and source voltage may open, that is to say, that the first transistor T1 threshold voltages Drift may cause it to turn on when turning on, and then cause shift-register circuit multi output phenomenon occur.The disclosure The shift register that embodiment is provided applies respectively different voltages by the grid in the first transistor and the second pole, reduce by Cause the risk of shift register failure in the first transistor threshold voltage shift, increase the first transistor threshold voltage shift Design redundancy.

It should be noted that embodiment of the disclosure is illustrated so that each transistor is N-type transistor as an example, also It is to say, embodiment of the disclosure is illustrated so that the first supply voltage VSS1 is less than second source voltage VSS2 as an example.Based on this Open description and teaching to the implementation, those of ordinary skill in the art can under the premise of creative work is not made The embodiment of the present disclosure is readily apparent that using P-type transistor or N-type and the implementation of P-type transistor combination, therefore, these realizations Mode is also in the protection domain of the disclosure.

For example, when the first transistor T1 is N-type transistor, when its gate source voltage Vgs (i.e. grid and source voltage it Difference) less than threshold voltage vt h when, the first transistor T1 close；When the first transistor T1 gate source voltages Vgs is more than threshold voltage During Vth, the first transistor T1 conductings.In view of the drain-to-gate voltage Vgd (voltages i.e. between grid and drain electrode of the first transistor T1 Difference) formation of impact drain electrode side raceway groove in the first transistor T1 courses of work, when drain-to-gate voltage Vgd is less than threshold voltage During Vth, the raceway groove in drain electrode side disappears, and the first transistor enters pinching area.

For example, first pole (such as source electrode) of the first transistor T1 is connected with clock signal terminal CLK in the embodiment of the present disclosure, The control pole (such as grid) of the first transistor T1 is connected with pull-up node PU, second pole (for example draining) of the first transistor T1 It is connected with outfan OUTPUT.Therefore, stage (such as fourth stage t4 shown in Figure 10), the first transistor T1 are kept in voltage Grid voltage be the first supply voltage VSS1 (such as -11V), the drain voltage of the first transistor T1 is second source voltage VSS2 (such as -8V).Now, the drain-to-gate voltage Vgd=-3V of the first transistor T1, (i.e. Vgd=identical compared to drain-to-gate voltage Situation 0V), the raceway groove of the drain electrode side of the first transistor T1 is less susceptible to form induction channels, makes the first transistor T1 in folder Disconnected state, so as to the threshold voltage vt h drifts reduced due to the first transistor T1 cause the risk for failing, increases the first transistor The design redundancy of threshold voltage shift.

For example, as shown in figure 3, in the shift register 100 that the embodiment of the present disclosure is provided, input circuit 110 includes the Two-transistor T2.First pole of transistor seconds T2 is connected with input signal end INPUT, the control pole of transistor seconds T2 with it is defeated Enter signal end INPUT connections, second pole of transistor seconds T2 is connected with pull-up node PU.

For example, as shown in figure 3, reset circuit 120 includes third transistor T3.First pole of third transistor T3 and pull-up Node PU connects, and the control pole of third transistor T3 is connected with reset signal end RESET, the second pole of third transistor T3 and the One power end LVSS1 connects to receive the first supply voltage VSS1.For example, when third transistor T3 is turned on, the first power end The first supply voltage VSS1 of LVSS1 is transferred to pull-up node PU.

It should be noted that the input circuit 110 and reset circuit 120 shown in Fig. 3 is only of the embodiment of the present disclosure Example, embodiment of the disclosure includes but is not limited to the situation shown in Fig. 3.

For example, as shown in figure 4, in the shift register 100 that the embodiment of the present disclosure is provided, output pull-down circuit 140 is wrapped Include the first output pull-down transistor K1.First pole of the first output pull-down transistor K1 is connected with outfan OUTPUT, and first is defeated The control pole for going out pull-down transistor K1 is connected with reset signal end RESET, second pole and the of the first output pull-down transistor K1 Two power end LVSS2 connect to receive second source voltage VSS2.In the embodiment illustrated in fig. 4, the letter of reset signal end RESET Number control first export pull-down transistor K1 opening and closing.

For example, as shown in figure 5, the embodiment of the present disclosure provide shift register 100, also including the first pull-down control circuit 150.First pole of the first output pull-down transistor K1 is connected with outfan OUTPUT, the control of the first output pull-down transistor K1 Pole is connected with the first pull-down control circuit 150, and second pole of the first output pull-down transistor K1 is configured to receive second source Voltage VSS2；First pull-down control circuit 150 is configured to control the first opening and closing for exporting pull-down transistor K1.And example Such as, second pole of the first output pull-down transistor K1 is connected to receive second source voltage VSS2 with second source end LVSS2；The One pull-down control circuit 150 with respectively with the 3rd power end VGH, pull-up node PU, the outputs of the first power end LVSS1 and first under Control pole (for example, the grid) connection of pull transistor K1.

For example, the 3rd power end VGH is configured to supply the 3rd supply voltage VH, and the 3rd supply voltage VH for example, can make The voltage (for example, 5V, 10V, 22V etc.) that N-type transistor is opened.3rd supply voltage VH is more than the first supply voltage VSS1, the Three supply voltage VH are more than second source voltage VSS2.

For example, as shown in fig. 6, the embodiment of the present disclosure provide shift register 100 in, the first pull-down control circuit 150 include the first sub- control circuit 151 and the second sub- control circuit 152.First sub- control circuit 151 and the 3rd power end VGH, First pull-down node PD1 and the second sub- control circuit 152 connect respectively；Second sub- control circuit 152 and pull-up node PU, the One pull-down node PD1 and the first power end LVSS1 connect respectively.

For example, with continued reference to Fig. 6, the first sub- control circuit 151 includes the first controlling transistor M1 and the second control crystal Pipe M2；Second sub- control circuit 152 includes the 3rd controlling transistor M3 and the 4th controlling transistor M4.The lower crystal pulling of first output The control pole of pipe K1 is connected with the first pull-down node PD1；First pole of the first controlling transistor M1 connects with the 3rd power end VGH Connect, the control pole of the first controlling transistor M1 is connected with the 3rd power end VGH, second pole and first of the first controlling transistor M1 Node N1 connects；First pole of the second controlling transistor M2 is connected with the 3rd power end VGH, the control of the second controlling transistor M2 Pole is connected with primary nodal point N1, and the second pole of the second controlling transistor M2 is connected with the first pull-down node PD1；3rd control crystal First pole of pipe M3 is connected with the first pull-down node PD1, and the control pole of the 3rd controlling transistor M3 is connected with pull-up node PU, the Second pole of three controlling transistors M3 is connected with the first power end LVSS1；First pole of the 4th controlling transistor M4 and first segment Point N1 connects, and the control pole of the 4th controlling transistor M4 is connected with pull-up node PU, the second pole of the 4th controlling transistor M4 and First power end LVSS1 connects.

For example, the first sub- control circuit 151 and the second sub- control circuit 152 can be with cooperatings adjusting the first drop-down section The voltage of point PD1, and then control the first opening and closing for exporting pull-down transistor K1.

For example, as shown in fig. 7, the embodiment of the present disclosure provide shift register 100, also including the second pull-down control circuit 160.Except the first output pull-down transistor K1, output pull-down circuit 140 also includes the second output pull-down transistor K2.Second is defeated The first pole for going out pull-down transistor K2 is connected with outfan OUTPUT, under the control pole and second of the second output pull-down transistor K2 Control circuit 160 is drawn to connect, second pole of the second output pull-down transistor K2 is configured to receive second source voltage VSS2；The Two pull-down control circuits 160 are configured to control the second opening and closing for exporting pull-down transistor K2.Again for example, the first output Second pole of pull-down transistor K1 is connected to receive second source signal V2 with second source signal end VDD2, and the second output is drop-down Second pole of transistor K2 is connected to receive the first power supply signal V1 with the first power supply signal end VDD1.For example, the first power supply letter Number end VDD1 provide the first power supply signal V1 and second source signal end VDD2 provide second source signal V2 it is reverse each other Signal.That is, when the first power supply signal V1 is high level voltage (such as the 3rd supply voltage VH), second source signal V2 is second source voltage VSS2；When the first power supply signal V1 is second source voltage VSS2, second source signal V2 is height Level voltage (such as the 3rd supply voltage VGH).The the first power supply signal V1 provided due to the first power supply signal end VDD1 and the The second source signal V2 reverse signals each other that two power supply signal end VDD2 are provided, at any time, the first power supply signal V1 and One in second source signal V2 is second source voltage VSS2.Therefore, at any time, the first output pull-down transistor K1 It is used to receive second source voltage VSS2 with the second output pull-down transistor K2.

For example, as shown in figure 8, the embodiment of the present disclosure provide shift register 100 in, the first pull-down control circuit 150 include the first sub- control circuit 151 and the second sub- control circuit 152；Second pull-down control circuit 160 includes the 3rd son control The sub- control circuit 162 of circuit 161 and the 4th.First sub- control circuit 151 and the first power supply signal end VDD1, the first pull-down node PD1 and the second sub- control circuit 152 connect respectively；Second sub- control circuit 152 and pull-up node PU, the first pull-down node PD1 and the first power end LVSS1 connect respectively；It is 3rd sub- control circuit 161 and second source signal end VDD2, second drop-down Node PD2 and the 4th sub- control circuit 162 connect respectively；4th sub- control circuit 162 and pull-up node PU, the second drop-down section Point PD2 and the first power end LVSS1 connect respectively.

For example, the 3rd sub- control circuit 161 and the 4th sub- control circuit 162 can be with cooperatings adjusting the second drop-down section The voltage of point PD2, and then control the second opening and closing for exporting pull-down transistor K2.

For example, with continued reference to Fig. 8, in the shift register 100 that the embodiment of the present disclosure is provided, the first sub- control circuit 151 include the first controlling transistor M1 and the second controlling transistor M2；Second sub- control circuit 152 includes the 3rd controlling transistor M3 and the 4th controlling transistor M4；3rd sub- control circuit 161 includes the 5th controlling transistor M5 and the 6th controlling transistor M6； 4th sub- control circuit 162 includes the 7th controlling transistor M7 and the 8th controlling transistor M8.First output pull-down transistor K1 Control pole be connected with the first pull-down node PD1, the second pole and the second source signal end of the first output pull-down transistor K1 VDD2 connects to receive second source signal V2；First pole of the first controlling transistor M1 is connected with the first power supply signal end VDD1 To receive the first power supply signal V1, the control pole of the first controlling transistor M1 is connected to receive with the first power supply signal end VDD1 One power supply signal V1, the second pole of the first controlling transistor M1 is connected with primary nodal point N1；The first of second controlling transistor M2 Pole is connected to receive the first power supply signal V1, the control pole of the second controlling transistor M2 and first with the first power supply signal end VDD1 Node N1 connects, and the second pole of the second controlling transistor M2 is connected with the first pull-down node PD1；The of 3rd controlling transistor M3 One pole is connected with the first pull-down node PD1, and the control pole of the 3rd controlling transistor M3 is connected with pull-up node PU, and the 3rd control is brilliant Second pole of body pipe M3 is connected to receive the first supply voltage VSS1 with the first power end LVSS1；4th controlling transistor M4 First pole is connected with primary nodal point N1, and the control pole of the 4th controlling transistor M4 is connected with pull-up node PU, the 4th control crystal Second pole of pipe M4 is connected to receive the first supply voltage VSS1 with the first power end LVSS1；Second output pull-down transistor K2 Control pole be connected with the second pull-down node PD2, the second pole and the first power supply signal end of the second output pull-down transistor K2 VDD1 connects to receive the first power supply signal V1；First pole of the 5th controlling transistor M5 is connected with second source signal end VDD2 To receive second source signal V2, the control pole of the 5th controlling transistor M5 is connected to receive with second source signal end VDD2 Two power supply signal V2, the second pole of the 5th controlling transistor M5 is connected with secondary nodal point N2；The first of 6th controlling transistor M6 Pole is connected to receive second source signal V2, the control pole and second of the 6th controlling transistor M6 with second source signal end VDD2 Node N2 connects, and the second pole of the 6th controlling transistor M6 is connected with the second pull-down node PD2；The of 7th controlling transistor M7 One pole is connected with the second pull-down node PD2, and the control pole of the 7th controlling transistor M7 is connected with pull-up node PU, and the 7th control is brilliant Second pole of body pipe M7 is connected to receive the first supply voltage VSS1 with the first power end LVSS1；8th controlling transistor M8 First pole is connected with secondary nodal point N2, and the control pole of the 8th controlling transistor M8 is connected with pull-up node PU, the 8th control crystal Second pole of pipe M8 is connected to receive the first supply voltage VSS1 with the first power end LVSS1.First power supply signal V1 and second Power supply signal V2 reverse signals each other, voltage when the first power supply signal V1 and second source signal V2 is low level signal is Second source voltage VSS2.

For example, as shown in figure 9, the shift register 100 that the embodiment of the present disclosure is provided also includes pull-up node pull-down circuit 170.Pull-up node pull-down circuit 170 and pull-up node PU, the first pull-down node PD1, the second pull-down node PD2 and the first power supply End LVSS1 connects respectively.

For example, as shown in figure 9, the embodiment of the present disclosure provide shift register 100 in, pull-up node pull-down circuit 170 include the first pull-down transistor F1 and the second pull-down transistor F2.First pole of the first pull-down transistor F1 and pull-up node PU connects, and the control pole of the first pull-down transistor F1 is connected with the second pull-down node PD2, second pole of the first pull-down transistor F1 It is connected to receive the first supply voltage VSS1 with the first power end LVSS1；First pole of the second pull-down transistor F2 and pull-up section Point PU connects, and the control pole of the second pull-down transistor F2 is connected with the first pull-down node PD1, and the second of the second pull-down transistor F2 Pole is connected to receive the first supply voltage VSS1 with the first power end LVSS1.

For example, Figure 10 is a kind of driver' s timing figure of shift register 100 that the embodiment of the present disclosure is provided, below with Fig. 9 Driver' s timing shown in shown shift register and Figure 10 introduces the course of work of shift register.

For example, in the driver' s timing shown in Figure 10, the voltage of the first power supply signal end VDD1 is the 3rd supply voltage VH (voltage that the 3rd power end VGH is provided), the voltage of second source signal end VDD2 is second source voltage VSS2.

For example, the 3rd supply voltage VH that the 3rd power end VGH is provided is more than second source voltage VSS2, second source electricity Pressure VSS2 is more than the first supply voltage VSS1；Again for example, the 3rd supply voltage VH is 22V, and second source voltage VSS2 is -8V, First supply voltage VSS1 is -11V.It is 22V that embodiment of the disclosure includes but is not limited to the 3rd supply voltage VH, and second is electric Voltage VSS2 in source is -8V, and the first supply voltage VSS1 is the situation of -11V, the 3rd supply voltage VH, second source voltage VSS2 With the first supply voltage VSS1 can also be other magnitudes of voltage, for example, the 3rd supply voltage VH be 10V, second source voltage VSS2 is -5V, and the first supply voltage is -8V.

For example, the voltage of t1 in the first stage, clock signal terminal CLK is second source voltage VSS2, input signal end The voltage of INPUT is the 3rd supply voltage VH, and the voltage of reset signal end RESET is second source voltage VSS2.Due to input The voltage of signal end INPUT is the 3rd supply voltage VH, and transistor seconds T2 is opened, and the voltage of pull-up node PU is the first high electricity Ordinary telegram pressure (the first high level voltage is for example equal to the 3rd supply voltage VH), storage capacitance C charges；3rd controlling transistor M3 is opened Open, the first supply voltage VSS1 that the first power end LVSS1 is provided is transferred to into the first pull-down node PD1, the first output is drop-down Transistor K1 and the second pull-down transistor F2 are turned off；7th controlling transistor M7 is opened, and the first power end LVSS1 is provided First supply voltage VSS1 is transferred to the second pull-down node PD2, the second output pull-down transistor K2 and the first pull-down transistor F1 It is turned off.

For example, in second stage t2, the voltage of clock signal terminal CLK is the 3rd supply voltage VH, input signal end INPUT Voltage be second source voltage VSS2, the voltage of reset signal end RESET is second source voltage VSS2.Due to storage capacitance The boot strap of C, when the change in voltage of clock signal terminal CLK is the 3rd supply voltage VH, storage capacitance C is by pull-up node PU Voltage lift is to the second high level voltage (the second high level voltage is for example equal to the 3rd supply voltage VH of twice), the second high electricity Ordinary telegram pressure is higher than the first high level voltage so that the first transistor T1 is more fully opened, and the first transistor T1 is by clock signal The high level voltage of end CLK is transferred to outfan OUTPUT.

For example, in phase III t3, the voltage of clock signal terminal CLK is second source voltage VSS2, input signal end The voltage of INPUT is second source voltage VSS2, and the voltage of reset signal end RESET is the 3rd supply voltage VH.Due to resetting The voltage of signal end RESET is the 3rd supply voltage VH, and third transistor T3 is opened, that the first power end LVSS1 is provided One supply voltage VSS1 is transferred to pull-up node PU；3rd controlling transistor M3 and the 7th controlling transistor M7 are closed, the second control The 3rd supply voltage VH that first power supply signal end VDD1 is provided is transferred to the first pull-down node PD1 by transistor M2 processed；Second Pull-down transistor F2 is opened, and the first supply voltage VSS1 is transferred to into pull-up node PU；First output pull-down transistor K1 is opened, The second source voltage VSS2 that second source signal end VDD2 is provided is transferred to into outfan OUTPUT.

For example, in fourth stage t4, the voltage of input signal end INPUT is second source voltage VSS2, reset signal end The voltage of RESET is second source voltage VSS2.Pull-up node PU, the first pull-down node PD1, the second pull-down node PD2 and defeated Go out to hold OUTPUT to keep and phase III t3 identical state.

For example, in phase III t3 and fourth stage t4, the grid voltage of the first transistor T1 is the first supply voltage The drain voltage of VSS1 (such as -11V), the first transistor T1 is second source voltage VSS2 (such as -8V).Now, first is brilliant The drain-to-gate voltage Vgd=VSS1-VSS2 (for example, Vgd=-3V) of body pipe T1, (i.e. Vgd=0V's) identical compared to drain-to-gate voltage Situation, the raceway groove of the drain electrode side of the first transistor T1 is less susceptible to form induction channels, makes the first transistor T1 be in pinch off shape State, so as to the threshold voltage vt h drifts reduced due to the first transistor T1 cause the risk for failing, increases first crystal pipe threshold The design redundancy of voltage drift.

It should be noted that the drain-to-gate voltage of the first transistor T1 is not limited to the situation of -3V, according to the concrete of circuit Design, can flexibly select the value of drain-to-gate voltage.

For example, the voltage of the first power supply signal end VDD1 and the voltage of second source signal end VDD2 can show in a frame Picture to another frame display picture alternate stage mutually changes.For example, the voltage of the first power supply signal end VDD1 after conversion For second source voltage VSS2, the voltage of second source signal end VDD2 is the 3rd supply voltage VH.Again for example, such as Figure 10 institutes Show, the voltage of the first power supply signal end VDD1 and the voltage of second source signal end VDD2 can be in certain in fourth stage Carve mutually conversion.

For example, when the voltage of the first power supply signal end VDD1 is second source voltage VSS2, second source signal end VDD2 Voltage be the 3rd supply voltage VH when, the exchange function of the first pull-up node PD1 and the second pull-down node PD2, first is drop-down The exchange function of the pull-down control circuit 160 of control circuit 150 and second, the first output pull-down transistor K1 and second exports drop-down The exchange function of the exchange function of transistor K2, the first pull-down transistor F1 and the second pull-down transistor F2.Shift register Operation principle and the voltage of the first power supply signal end VDD1 are that the 3rd supply voltage VH, the voltage of second source signal end VDD2 are It is similar to during second source voltage VSS2, will not be described here.

For example, the first pull-down control circuit 150 and the second pull-down control circuit 160 can control the first pull-down node PD1 Work respectively with the second pull-down node PD2, can so cause the lower crystal pulling of the outputs of the first output pull-down transistor K1 and second Pipe K2 time-sharing works, cause the first pull-down transistor F1 and the second pull-down transistor F2 time-sharing works, when reducing crystal pipe range Between in opening causing trouble probability, improve the capacity of resisting disturbance of shift register, and then improve displacement and post The reliability of storage.

For example, reversely believed each other using the voltage of the first power supply signal end VDD1 and the voltage of second source signal end VDD2 Number the characteristics of, the second source voltage VSS2 that timesharing ground provides the first power supply signal end VDD1 and second source signal end VDD2 Outfan is transferred to, the second source voltage VSS2 of outfan is distinguished with the first supply voltage VSS1 of pull-up node, from And make the presence of certain voltage difference between the control pole of the first transistor and the second pole, so as to improve first crystal pipe threshold electricity The design redundancy of pressure drift.

Embodiment of the disclosure also provides a kind of gate driver circuit 10, and as shown in figure 11, gate driver circuit 10 includes The shift register 100 that disclosure any embodiment is provided.

For example, as shown in figure 11, the gate driver circuit 10 that the embodiment of the present disclosure is provided, including multiple disclosure of cascade The shift register 100 that any embodiment is provided, in addition to the first order and afterbody shift register 100, this grade of displacement is posted The input signal end INPUT of storage 100 is connected with the outfan OUTPUT of upper level shift register 100；This grade of shift LD The reset signal end RESET of device 100 is connected with the outfan OUTPUT of next stage shift register 100.

For example, the input signal end INPUT of first order shift register is connected with the first trigger end STV1；Last The reset signal end RESET of level shift register is connected with the second trigger end STV2.

For example, when 10 forward scan of gate driver circuit, the first trigger end STV1 is first order shift register Input signal is provided, the second trigger STV2 end provides reset signal for afterbody shift register；When raster data model electricity During 10 reverse scan of road, the second trigger end STV2 provides input signal, the first triggering letter for afterbody shift register Number end STV1 provide reset signal for first order shift register.For example, when forward scan and reverse scan switch, displacement is posted The input circuit of storage and the exchange function of reset circuit.

For example, as shown in figure 11, gate driver circuit 10 includes n level shift register SR1, SR2 ... SRn, these shiftings Bit register SR1, SR2 ... SRn may each be the shift register 100 of disclosure any embodiment offer.Shift register The outfan OUTPUT of SR1, SR2 ... SRn connections corresponding with grid line G1, G2 ... Gn respectively.

It should be noted that because the gate driver circuit 10 that the embodiment of the present disclosure is provided can realize forward scan and inverse To scanning, when scanning direction switches, " upper level " and " next stage " in sequential can be converted accordingly, therefore, above-mentioned " upper one Level " and " next stage " do not imply that the upper level and next stage on scanning sequence, and refer to the upper level in physical connection with One-level.

Embodiment of the disclosure also provides a kind of display floater 1, and as shown in figure 12, display floater 1 includes that the disclosure is arbitrary The gate driver circuit 10 that embodiment is provided.

For example, as shown in figure 12, the embodiment of the present disclosure provide display floater 1 also include grid line 11, data wire 12 and Intersected the multiple pixel cells 13 for limiting by grid line 11 and data wire 12, gate driver circuit 10 is configured to be provided to grid line 11 Gate drive signal.

For example, grid line 11 can include grid line G1, G2 ... the Gn, shift register SR1, SR2 ... shown in Figure 11 Every grade of shift register is used to export a line gate drive signal to corresponding grid line G1, G2 ... Gn in SRn.

Embodiment of the disclosure also provides a kind of driving side of the shift register 100 that disclosure any embodiment is provided Method, as shown in figure 13, the driving method comprises the steps：

Step S10：First supply voltage VSS1 is write into pull-up node PU；And

Step S20：Second source voltage VSS2 is write into outfan OUTPUT, the first supply voltage VSS1 and second source Voltage VSS2 is different.

For example, when the first transistor T1 is N-type transistor, the first supply voltage VSS1 is less than second source voltage VSS2。

For example, when the first transistor T1 is P-type transistor, the first supply voltage VSS1 is more than second source voltage VSS2。

For example, the embodiment of the present disclosure is provided shift register, gate driver circuit, display floater and driving method can be with Improve the stability of circuit.

Although above having used general explanation and specific embodiment, detailed description is made to the disclosure, On the basis of the embodiment of the present disclosure, it can be made some modifications or improvements, this is to those skilled in the art apparent 's.Therefore, the these modifications or improvements on the basis of without departing from disclosure spirit, belong to what the disclosure was claimed Scope.

Claims

1. a kind of shift register, including：

Input circuit, is connected respectively with pull-up node and input signal end；

Reset circuit, is connected respectively to receive the first supply voltage with the pull-up node, reset signal end and the first power end；

Output circuit, is connected respectively with the pull-up node, clock signal terminal and outfan；And

Output pull-down circuit, is connected with the outfan, is configured to for second source voltage to write the outfan,

Wherein, first supply voltage is different from the second source voltage.

2. shift register according to claim 1, wherein,

The output circuit includes storage capacitance and the first transistor, and the first pole and the clock signal terminal of the first transistor connect Connect, the control pole of the first transistor is connected with the pull-up node, the second pole and the output of the first transistor End connection, the first end of the storage capacitance is connected with the pull-up node, the second end and the output of the storage capacitance End connection；

The input circuit includes transistor seconds, and the first pole of the transistor seconds is connected with the input signal end, institute The control pole for stating transistor seconds is connected with the input signal end, the second pole and the pull-up node of the transistor seconds Connection；And

The reset circuit includes third transistor, and the first pole of the third transistor is connected with the pull-up node, described The control pole of third transistor is connected with the reset signal end, the second pole of the third transistor and first power end Connection.

3. shift register according to claim 1 and 2, wherein, the output pull-down circuit includes that the first output is drop-down Transistor, the first pole of the first output pull-down transistor is connected with the outfan, the first output pull-down transistor Control pole be connected with the reset signal end, it is described first output pull-down transistor the second pole be connected with second source end with Receive second source voltage.

4. shift register according to claim 1 and 2, also including the first pull-down control circuit, wherein, under the output Puller circuit includes the first output pull-down transistor,

First pole of the first output pull-down transistor is connected with the outfan, the control of the first output pull-down transistor Pole processed is connected with first pull-down control circuit, and the second pole of the first output pull-down transistor is configured to receive described Second source voltage；

First pull-down control circuit is configured to control the opening and closing of the first output pull-down transistor.

5. shift register according to claim 4, wherein, first pull-down control circuit includes the first son control electricity Road and the second sub- control circuit,

The first sub- control circuit connects respectively with the 3rd power end, the first pull-down node and the second sub- control circuit Connect,

The second sub- control circuit connects respectively with the pull-up node, first pull-down node and first power end Connect.

6. shift register according to claim 5, wherein, the first sub- control circuit includes the first controlling transistor With the second controlling transistor, the second sub- control circuit includes the 3rd controlling transistor and the 4th controlling transistor,

The control pole of the first output pull-down transistor is connected with first pull-down node；

First pole of first controlling transistor is connected with the 3rd power end, the control pole of first controlling transistor It is connected with the 3rd power end, the second pole of first controlling transistor is connected with primary nodal point；

First pole of second controlling transistor is connected with the 3rd power end, the control pole of second controlling transistor It is connected with the primary nodal point, the second pole of second controlling transistor is connected with first pull-down node；

First pole of the 3rd controlling transistor is connected with first pull-down node, the control of the 3rd controlling transistor Pole is connected with the pull-up node, and the second pole of the 3rd controlling transistor is connected with first power end；

First pole of the 4th controlling transistor is connected with the primary nodal point, the control pole of the 4th controlling transistor with The pull-up node connection, the second pole of the 4th controlling transistor is connected with first power end.

7. shift register according to claim 4, also including the second pull-down control circuit, wherein, the output is drop-down Circuit also includes the second output pull-down transistor,

First pole of the second output pull-down transistor is connected with the outfan, the control of the second output pull-down transistor Pole processed is connected with second pull-down control circuit, and the second pole of the second output pull-down transistor is configured to receive described Second source voltage；

Second pull-down control circuit is configured to control the opening and closing of the second output pull-down transistor.

8. shift register according to claim 7, wherein,

First pull-down control circuit includes the first sub- control circuit and the second sub- control circuit, the second drop-down control electricity Road includes the 3rd sub- control circuit and the 4th sub- control circuit,

The first sub- control circuit and the first power supply signal end, the first pull-down node and the second sub- control circuit difference Connection,

The second sub- control circuit connects respectively with the pull-up node, first pull-down node and first power end Connect,

The 3rd sub- control circuit and second source signal end, the second pull-down node and the 4th sub- control circuit difference Connection,

The 4th sub- control circuit connects respectively with the pull-up node, second pull-down node and first power end Connect.

9. shift register according to claim 8, wherein, the first sub- control circuit includes the first controlling transistor With the second controlling transistor, the second sub- control circuit includes the 3rd controlling transistor and the 4th controlling transistor, described the Three sub- control circuits include the 5th controlling transistor and the 6th controlling transistor, and the 4th sub- control circuit includes the 7th control Transistor and the 8th controlling transistor,

The control pole of the first output pull-down transistor is connected with first pull-down node, crystal pulling under first output Second pole of pipe is connected to receive second source signal with the second source signal end；

First pole of first controlling transistor is connected to receive the first power supply signal with the first power supply signal end, and described first The control pole of controlling transistor is connected to receive first power supply signal, first control with the first power supply signal end Second pole of transistor is connected with primary nodal point；

First pole of second controlling transistor is connected to receive first power supply signal with the first power supply signal end, The control pole of second controlling transistor is connected with the primary nodal point, second pole and first of second controlling transistor Pull-down node connects；

First pole of the 3rd controlling transistor is connected with first pull-down node, the control of the 3rd controlling transistor Pole is connected with the pull-up node, and the second pole of the 3rd controlling transistor is connected to receive described first with the first power end Supply voltage；

First pole of the 4th controlling transistor is connected with the primary nodal point, the control pole of the 4th controlling transistor with The pull-up node connection, the second pole of the 4th controlling transistor is connected to receive described first with first power end Supply voltage；

The control pole of the second output pull-down transistor is connected with second pull-down node, crystal pulling under second output Second pole of pipe is connected to receive first power supply signal with the first power supply signal end；

First pole of the 5th controlling transistor is connected to receive the second source signal with the second source signal end, The control pole of the 5th controlling transistor is connected to receive the second source signal with the second source signal end, described Second pole of the 5th controlling transistor is connected with secondary nodal point；

First pole of the 6th controlling transistor is connected to receive the second source signal with the second source signal end, The control pole of the 6th controlling transistor is connected with the secondary nodal point, second pole and second of the 6th controlling transistor Pull-down node connects；

First pole of the 7th controlling transistor is connected with second pull-down node, the control of the 7th controlling transistor Pole is connected with the pull-up node, and the second pole of the 7th controlling transistor is connected to receive described first with the first power end Supply voltage；

First pole of the 8th controlling transistor is connected with the secondary nodal point, the control pole of the 8th controlling transistor with The pull-up node connection, the second pole of the 8th controlling transistor is connected to receive described first with first power end Supply voltage；

First power supply signal and second source signal reverse signal each other, first power supply signal and described second Voltage when power supply signal is low level signal is the second source voltage.

10. shift register according to claim 9, also including pull-up node pull-down circuit, with the pull-up node, institute State the first pull-down node, second pull-down node and first power end to connect respectively.

11. shift registers according to claim 10, wherein, the pull-up node pull-down circuit includes first time crystal pulling Body pipe and the second pull-down transistor,

First pole of first pull-down transistor is connected with the pull-up node, the control pole of first pull-down transistor with The second pull-down node connection, the second pole of first pull-down transistor is connected described to receive with first power end First supply voltage；

First pole of second pull-down transistor is connected with the pull-up node, the control pole of second pull-down transistor with The first pull-down node connection, the second pole of second pull-down transistor is connected described to receive with first power end First supply voltage.

12. a kind of gate driver circuits, including the shift register as described in any one of claim 1-11.

13. gate driver circuits according to claim 12, including cascade it is multiple such as any one of claim 1-11 institute The shift register stated, wherein, in addition to the first order and afterbody shift register, the input signal of this grade of shift register End is connected with the outfan of upper level shift register；The reset signal end of this grade of shift register and next stage shift register Outfan connection.

14. a kind of display floaters, including the gate driver circuit as described in claim 12 or 13.

A kind of 15. driving methods of the shift register as described in any one of claim 1-11, including：

First supply voltage is write into the pull-up node；And

The second source voltage is write into the outfan,

Wherein, first supply voltage is different from the second source voltage.