CN103956133A - shift register circuit and shift register - Google Patents
shift register circuit and shift register Download PDFInfo
- Publication number
- CN103956133A CN103956133A CN201410196024.9A CN201410196024A CN103956133A CN 103956133 A CN103956133 A CN 103956133A CN 201410196024 A CN201410196024 A CN 201410196024A CN 103956133 A CN103956133 A CN 103956133A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- input end
- shift registor
- switch
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000694 effects Effects 0.000 abstract description 17
- 230000001808 coupling effect Effects 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 68
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 68
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 52
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 52
- 239000003990 capacitor Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a shift register circuit which is provided with a plurality of shift registers. Each shift register has at least four input terminals, a pull-up circuit, a first switch, a first pull-down circuit and a second pull-down circuit. The control end of the first switch is coupled to the node. The pull-up circuit pulls up the potential of the node. The first pull-down circuit is used for pulling down the electric potential of the output end of the shift register. The second pull-down circuit is used for pulling down the potential of the node. The four input ends respectively receive different clock pulse signals to inhibit the surge generated at the node due to the coupling effect of the parasitic capacitance of the first switch and avoid the positive bias stress effect generated by the two transistors of the first pull-down circuit and the second pull-down circuit.
Description
Technical field
The present invention is about a kind of shift scratch circuit and shift registor, espespecially a kind of coupling effect (coupling effect) and positive bias stress (positive bias stress that alleviates transistorized stray capacitance; PBS) shift scratch circuit of effect and shift registor.
Background technology
Generally speaking, display panel includes multiple pixels, gate driver circuit and source electrode drive circuit.Gate driver circuit comprises multistage shift registor, is used to provide multiple gate drive signals, to control the open and close of pixel.Source electrode drive circuit is in order to write data signal to the pixel being unlocked.In addition, display panel often adopts gate driver circuit substrate technology (gate driver on array at present; GOA), to provide pixel required gate drive signal.Different from traditional gate drivers, its processing procedure of circuit because of employing GOA can be incorporated in the processing procedure of the thin film transistor (TFT) array (TFT array) of display panel, therefore can reduce the production cost of panel.
Please refer to Fig. 1 and Fig. 2.Fig. 1 is the circuit diagram of the shift registor 100 of prior art.Fig. 2 is the sequential chart of the shift registor 100 of Fig. 1.Shift registor 100 comprises four switch T1a to T1d.Wherein, switch T1a and T1c receive respectively input signal G
n-1and G
n+1, and input signal G wherein
n-1and G
n+1come from the output terminal of previous stage and rear one-level shift registor.The first end of switch T1b receives clock signal CK, and the control end of switch T1b is coupled to node Q
n, and the second end of switch T1b is coupled to the output terminal of shift registor 100 with output signal output G
n.The first end of switch T1c and T1d is respectively coupled to node Q
nand the output terminal of shift registor 100, and the second end of switch T1c and T1d is all coupled to system voltage end VSS.Wherein the current potential of system voltage end VSS can be identical with grid electronegative potential VGL.In addition input signal G,
n+1be sent to the control end of switch T1c and T1d, with the opening and closing of gauge tap T1c and T1d.In addition, another clock signal XCK is in order to control the operation of previous stage and rear one-level shift registor, and clock signal XCK and clock signal CK can switch between grid noble potential VGH and grid electronegative potential VGL.
At period T
aduring this time, switch T1a is because of input signal G
n-1be unlocked in grid noble potential VGH, and cause node Q
ncurrent potential be pulled to grid noble potential VGH, and cause the unlatching of switch T1b.In addition, switch T1c and T1d are because of input signal G
n+1be closed in grid electronegative potential VGL.Because of switch T1b be unlocked and clock signal CK in grid electronegative potential VGL, therefore the output signal G that the output terminal of shift registor 100 is exported
ncan be in grid electronegative potential VGL.
At period T
bduring this time, switch T1a, T1c and T1d are because of input signal G
n-1and G
n+1all be closed in grid electronegative potential VGL, and cause node Q
nin floating.In addition, because the current potential of clock signal CK is grid noble potential VGH, and due to the coupling effect of the stray capacitance of switch T1b, and make node Q
ncurrent potential be promoted to the VGH of about twice, and make output signal G
ncurrent potential be grid noble potential VGH.
At period T
cduring this time, switch T1a is because of input signal G
n-1be closed in grid electronegative potential VGL, and switch T1c and T1d are because of input signal G
n+1be unlocked in grid noble potential VGH.Node Q
ncurrent potential be pulled down to grid electronegative potential VGL because switch T1c is unlocked, and output signal G
ncurrent potential be also pulled down to grid electronegative potential VGL because switch T1d is unlocked.
But, because of the coupling effect (coupling effect) of the stray capacitance (parasitic capacitor) of switch T1b, the input signal G exporting at the output terminal of previous stage shift registor
n-1before being not yet again pulled to grid noble potential VGH by grid electronegative potential VGL, because the current potential of clock signal CK still can switch between grid noble potential VGH and grid electronegative potential VGL, therefore easily at node Q
nproduce surging (glitch), and and then cause the output signal G of shift registor 100
nwaveform incorrect.In addition, because switch T1c and T1d are using grid electronegative potential VGL as its low level signal, therefore switch T1c and T1d easily produce positive bias stress (positive bias stress; PBS) effect, is just being offset and switch T1c and T1d its critical voltage after operating for a long time can be produced, and causes switch T1c and T1d driving force to decline.
Summary of the invention
One embodiment of the invention provide a kind of shift registor.Described shift registor comprises signal end, first input end, the second input end, the 3rd input end, four-input terminal, output terminal, pull-up circuit, the first switch, the first pull-down circuit and the second pull-down circuit.Signal end receives input signal.First input end receives the first clock signal.The second input end receives the second clock signal.The 3rd input end receives the 3rd clock signal.Four-input terminal receives the 4th clock signal.Pull-up circuit and signal end and first input end couple, and in order to foundation the first clock signal, the electric connection between control signal end and node.The first switch and the second input end, node and output terminal couple, and in order to the current potential according to node, control the electric connection between the second input end and output terminal.The first pull-down circuit and the 3rd input end, output terminal and four-input terminal couple, and in order to foundation the 3rd clock signal, the electric connection between control output end and four-input terminal.The second pull-down circuit and node and first input end couple, and in order to according to the 4th clock signal or the 5th clock signal, control the electric connection between node and first input end.
One embodiment of the invention provide a kind of shift scratch circuit.Described shift scratch circuit comprises multiple shift registors.Each shift registor signal end, first input end, the second input end, the 3rd input end, four-input terminal, output terminal, pull-up circuit, the first switch, the first pull-down circuit, the second pull-down circuit and the 3rd pull-down circuit.Pull-up circuit and signal end, node and first input end couple, and in order to the current potential according to first input end, the electric connection between control signal end and node.The first switch and the second input end, node and output terminal couple, and in order to the current potential according to node, control the electric connection between the second input end and output terminal.The first pull-down circuit and the 3rd input end, output terminal and four-input terminal couple, and in order to the current potential according to the 3rd input end, the electric connection between control output end and four-input terminal.The second pull-down circuit and node, first input end and four-input terminal couple, and in order to the current potential according to four-input terminal, control the electric connection between node and first input end.The 3rd pull-down circuit and node, the 3rd input end and four-input terminal couple, and in order to the current potential according to the 3rd input end, control the electric connection between node and four-input terminal.Wherein first input end, the second input end, the 3rd input end and four-input terminal receive respectively different clock signals.
One embodiment of the invention provide a kind of shift scratch circuit.Described shift scratch circuit comprises multiple shift registors.Each shift registor signal end, first input end, the second input end, the 3rd input end, four-input terminal, the 5th input end, output terminal, pull-up circuit, the first switch, the first pull-down circuit and the second pull-down circuit.Pull-up circuit and signal end, node and first input end couple, and in order to the current potential according to first input end, the electric connection between control signal end and node.The first switch and the second input end, node and output terminal couple, and in order to the current potential according to node, control the electric connection between the second input end and output terminal.The first pull-down circuit and the 3rd input end, output terminal and four-input terminal couple, and in order to the current potential according to the 3rd input end, the electric connection between control output end and four-input terminal.The second pull-down circuit and node, first input end and the 5th input end couple, and in order to the current potential according to the 5th input end, control the electric connection between node and first input end.Wherein first input end, the second input end, the 3rd input end, four-input terminal and the 5th input end receive respectively different clock signals.
By the shift registor of the embodiment of the present invention, because the switch of each pull-down circuit is all using clock signal as its low level signal, therefore can be at the switch of each pull-down circuit because operating and be subject under the impact of positive bias stress (PBS) effect for a long time, the switch of pull-down circuit is imposed to periodic reverse blas stress (NBS) effect, so that critical voltage (Vth) is produced to recovery effect, improve driving force decline problem.In addition, the switch of the second pull-down circuit can in time be opened slightly or fully open, therefore can suppress to result from because of the coupling effect of the stray capacitance of the first switch the surging of the control end of the first switch.
Brief description of the drawings
Fig. 1 is the circuit diagram of the shift registor of prior art;
Fig. 2 is the sequential chart of the shift registor of Fig. 1;
Fig. 3 is the circuit diagram of the shift registor of one embodiment of the invention;
Fig. 4 is the schematic diagram of the shift scratch circuit of one embodiment of the invention;
Fig. 5 is the sequential chart of the shift scratch circuit of Fig. 4;
Fig. 6 is the circuit diagram of the shift registor of another embodiment of the present invention;
Fig. 7 is the schematic diagram of the shift scratch circuit of another embodiment of the present invention.
Wherein, Reference numeral;
100,300,300_5,500_5 shift registor
300_1,500_1 shift registor, the first shift registor
300_2,500_2 shift registor, the second shift registor
300_3,500_3 shift registor, the 3rd shift registor
300_4,500_4 shift registor, the 4th shift registor
310 pull-up circuits
320 first switches
330 first pull-down circuits
340,540 second pull-down circuits
350 the 3rd pull-down circuits
400,700 shift scratch circuits
C1 electric capacity, the first electric capacity
C2 electric capacity, the second electric capacity
CK, XCK clock signal
CK1 clock signal, the second clock signal
CK_1 clock signal, the 6th clock signal
CK2 clock signal, the 5th clock signal
CK_2 clock signal, the 3rd clock signal
CK3 clock signal, the 4th clock signal
CK_3 clock signal, the 7th clock signal
CK4 clock signal, the 8th clock signal
CK_4 clock signal, the first clock signal
G
noutput signal
G
n-1, G
1to G
5input signal
G
n+1input signal, output signal
IN signal end
IN1 first input end
IN2 the second input end
IN3 the 3rd input end
IN4 four-input terminal
IN5 the 5th input end
Q
nnode
Q
n+1the node of rear one-level shift registor
Out output terminal
SP start signal
T1a, T1e switch
T1b switch, the first switch
T1c switch, the 3rd switch
T1d switch, second switch
T1 period, the first period
T2, T4, T6, T
a, T
b, T
cperiod
T3 period, the second period
T5 period, the 3rd period
T7 period, the 4th period
T
pcycle
VGH grid noble potential
The grid noble potential of 2VGH twice
VGL grid electronegative potential
VGL1 first grid electronegative potential
VGL2 second grid electronegative potential
VSS system voltage end
Embodiment
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Please refer to Fig. 3, the circuit diagram of the shift registor 300 that Fig. 3 is one embodiment of the invention.Shift registor 300 comprises signal end IN, first input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4, output terminal Out, pull-up circuit 310, switch T1b, the first pull-down circuit 330, the second pull-down circuit 340 and the 3rd pull-down circuit 350.First input end IN1, the second input end IN2, the 3rd input end IN3 and four-input terminal IN4 receive respectively different clock signal CK_4, CK1, CK_2 and CK3, and the input signal G that signal end IN exports in order to receive the output terminal of previous stage shift registor
n-1.
Pull-up circuit 310 and signal end IN, node Q
nand first input end IN1 couples, and in order to the current potential according to first input end IN1, control signal end IN and node Q
nbetween electric connection.Switch T1b and the second input end IN2, node Q
nand output terminal Out couples, and in order to according to node Q
ncurrent potential, control the electric connection between the second input end IN2 and output terminal Out.The first pull-down circuit 330 and the 3rd input end IN3, output terminal Out and four-input terminal IN4 couple, and in order to the current potential according to the 3rd input end IN3, the electric connection between control output end Out and four-input terminal IN4.The second pull-down circuit 340 and node Q
n, first input end IN1 and four-input terminal IN4 couple, and in order to the current potential according to four-input terminal IN4, control node Q
nand the electric connection between first input end IN1.The 3rd pull-down circuit 350 and node Q
n, the 3rd input end IN3 and four-input terminal IN4 couple, and in order to the current potential according to the 3rd input end IN3, control node Q
nand the electric connection between four-input terminal IN4.Wherein first input end IN1, the second input end IN2, the 3rd input end IN3 and four-input terminal IN4 receive respectively different clock signal CK_4, CK1, CK_2 and CK3.
In an embodiment of the present invention, pull-up circuit 310 comprises switch T1a, and wherein the first end of switch T1a is coupled to signal end IN, and the second end of switch T1a is coupled to node Q
n, and the control end of switch T1a is coupled to first input end IN1.Switch T1a is according to clock signal CK_4, control signal end IN and node Q
nbetween electric connection.Moreover the first pull-down circuit 330 can comprise capacitor C 1 and switch T1d, wherein capacitor C 1 is coupled to node Q
nand between output terminal Out.The first end of switch T1d is coupled to output terminal Out, and the second end of switch T1d is coupled to four-input terminal IN4, and the control end of switch T1d is coupled to the 3rd input end IN3.Switch T1d is according to clock signal CK_2, the electric connection between control output end Out and four-input terminal IN4.In addition, the second pull-down circuit 340 comprises switch T1e, and wherein the first end of switch T1e is coupled to node Q
n, the second end of switch T1e is coupled to first input end IN1, and the control end of switch T1e is coupled to four-input terminal IN4.Switch T1e, according to clock signal CK3, controls node Q
nand the electric connection between first input end IN1.In addition, the 3rd pull-down circuit 350 can comprise capacitor C 2 and switch T1c, and wherein capacitor C 2 is coupled to node Q
nand the 3rd between input end IN3.The first end of switch T1c is coupled to node Q
n, the second end of switch T1c is coupled to the 4th o'clock input end IN4, and the control end of switch T1c is coupled to the 3rd input end IN3.T1c, according to clock signal CK_2, controls node Q
nand the electric connection between four-input terminal IN4.Because switch T1c and T1d are using clock signal CK3 as its low level signal, and switch T1e is using clock signal CK_4 as its low level signal, therefore can be subject to positive bias stress (positive bias stress because of operation for a long time at switch T1c, T1d and T1e; PBS), under the impact of effect, switch T1c, T1d and T1e are imposed to periodic reverse blas stress (negative bias stress; NBS) effect, therefore the critical voltage of switch T1c, T1d and T1e has reply effect, also therefore the driving force of switch T1c, T1d and T1e can be enhanced.
Shift registor 300 can be used for the gate drivers of display panel, and gate driver circuit can comprise multistage shift registor 300, is used to provide multiple signals, to control the open and close of pixel of display panel.Please refer to Fig. 4 and Fig. 5.Fig. 4 is the schematic diagram of the shift scratch circuit 400 of one embodiment of the invention, and the sequential chart of the shift scratch circuit 400 that Fig. 5 is Fig. 4.Shift scratch circuit 400 includes multiple shift registors (as 300_1 to 300_5).Wherein, the circuit framework of each shift registor 300_1 to 300_5 is identical with the shift registor of Fig. 3 300 circuit frameworks.Shift registor 300_1 to 300_5 can be respectively by output terminal Out by output signal G
1to G
5export corresponding gate line (or claiming sweep trace) to, to open in order the pixel coupling from the different gate lines of display panel.The signal end IN of shift registor 300_2 to 300_5 can receive respectively the output signal G of its previous stage shift registor 300_1 to 300_4
1to G
4, the signal end IN of shift registor 300_1 receives start signal SP.In addition, the first input end IN1 of shift registor 300_1 and shift registor 300_5, the second input end IN2, the 3rd input end IN3 and four-input terminal IN4 receive respectively clock signal CK_4, CK1, CK_2 and CK3; First input end IN1, the second input end IN2, the 3rd input end IN3 and the four-input terminal IN4 of shift registor 300_2 receive respectively clock signal CK_1, CK2, CK_3 and CK4; First input end IN1, the second input end IN2, the 3rd input end IN3 and the four-input terminal IN4 of shift registor 300_3 receive respectively clock signal CK_2, CK3, CK_4 and CK1; And the first input end IN1 of shift registor 300_4, the second input end IN2, the 3rd input end IN3 and four-input terminal IN4 receive respectively clock signal CK_3, CK4, CK_1 and CK2.Wherein the current potential of clock signal CK1, CK2, CK3 and CK4 can switch between grid noble potential VGH and first grid electronegative potential VGL1, the current potential of clock signal CK_1, CK_2, CK_3 and CK_4 can switch between grid noble potential VGH and second grid electronegative potential VGL2, and second grid electronegative potential VGL2 can be lower than first grid electronegative potential VGL1.In an embodiment of the present invention, grid noble potential VGH is positive 20 volts, and first grid electronegative potential VGL1 is negative 10 volts, and second grid electronegative potential VGL2 is negative 13 volts, but the present invention is not as limit.
In addition, each clock signal CK1 to CK4 can be every one-period T
pbe promoted to grid noble potential VGH by first grid electronegative potential VGL1, and each clock signal CK_1 to CK_4 can be every one-period T
pbe promoted to grid noble potential VGH by second grid electronegative potential VGL2.Clock signal CK1 has similar sequential to CK_1, and clock signal CK2 has similar sequential to CK_2, and clock signal CK3 has similar sequential to CK_3, and clock signal CK4 has similar sequential to CK_4.In detail, clock signal CK1 is promoted to the time point of grid noble potential VGH by first grid electronegative potential VGL1 and is reduced to the time point of first grid electronegative potential VGL1 by grid noble potential VGH, can is promoted to the time point of grid noble potential VGH and is reduced to the time point of second grid electronegative potential VGL2 by grid noble potential VGH consistent by second grid electronegative potential VGL2 with clock signal CK_1.Similarly, clock signal CK2 is promoted to the time point of grid noble potential VGH by first grid electronegative potential VGL1 and is reduced to the time point of first grid electronegative potential VGL1 by grid noble potential VGH, can is promoted to the time point of grid noble potential VGH and is reduced to the time point of second grid electronegative potential VGL2 by grid noble potential VGH consistent by second grid electronegative potential VGL2 with clock signal CK_2.Clock signal CK3 is promoted to the time point of grid noble potential VGH by first grid electronegative potential VGL1 and is reduced to the time point of first grid electronegative potential VGL1 by grid noble potential VGH, can is promoted to the time point of grid noble potential VGH and is reduced to the time point of second grid electronegative potential VGL2 by grid noble potential VGH consistent by second grid electronegative potential VGL2 with clock signal CK_3.Clock signal CK4 is promoted to the time point of grid noble potential VGH by first grid electronegative potential VGL1 and is reduced to the time point of first grid electronegative potential VGL1 by grid noble potential VGH, can is promoted to the time point of grid noble potential VGH and is reduced to the time point of second grid electronegative potential VGL2 by grid noble potential VGH consistent by second grid electronegative potential VGL2 with clock signal CK_4.
Moreover, when clock signal CK1 to CK4 is different, be grid noble potential VGH, and clock signal CK1 to CK4 is grid noble potential VGH when different.Taking Fig. 5 as example, clock signal CK4, CK1, CK2 and CK3 are grid noble potential VGH at period T1, T3, T5 and T7 respectively in order, and clock signal CK_4, CK_1, CK_2 and CK_3 are grid noble potential VGH at period T1, T3, T5 and T7 respectively in order.
In addition, because shift scratch circuit 400 operates according to eight clock signal CK1 to CK4 and CK_1 to CK_4, therefore shift scratch circuit 400 can be described as eight phases (eight phase) shift scratch circuit.Four clock signals that input end IN1 to IN4 receives of N shift registor of shift scratch circuit 400, the clock signal that can receive with four input end IN1 to IN4 of (N+4) individual shift registor is identical, and wherein N is positive integer.For example, first input end IN1, the second input end IN2, the 3rd input end IN3 and the four-input terminal IN4 of first shift registor 300_1 receive clock signal CK_4, CK1, CK_2 and CK3 respectively, and the clock signal that the first input end IN1 of the 5th shift registor 300_5, the second input end IN2, the 3rd input end IN3 and four-input terminal IN4 receive can be also clock signal CK_4, CK1, CK_2 and CK3.
For characteristic and the advantage of shift registor 300 can be clearly described, refer again to Fig. 3 and Fig. 5.During period T1, the input signal G that shift registor 300 receives
n-1with clock signal CK_4 be grid noble potential VGH, and the switch T1a of pull-up circuit 310 is unlocked, and causes node Q
ncurrent potential be grid noble potential VGH.In addition, because clock signal CK3 and CK_2 are respectively in first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and clock signal CK_4 is grid noble potential VGH, and switch T1e, T1c and T1d are closed.In addition, because clock signal CK1 is in first grid electronegative potential VGL1, and switch T1b is unlocked, therefore output signal G
ncurrent potential can be first grid electronegative potential VGL1.In addition, because clock signal CK3 is first grid electronegative potential VGL1, and clock signal CK_4 is grid noble potential VGH, therefore the pressure reduction between the gate-to-source of switch T1e can be great negative value, and switch T1e can closely be closed.
During period T2, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK3 and CK_2 are respectively in first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and switch T1e, T1c and T1d are closed.Therefore, node Q
ncurrent potential can be because of node Q
nmaintain grid noble potential VGH in suspension joint (floating) state.In addition, because the current potential of clock signal CK1 is still first grid electronegative potential VGL1, therefore output signal G
ncurrent potential can maintain first grid electronegative potential VGL1.
During period T3, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK_2 is in second grid electronegative potential VGL2, and switch T1c and T1d are closed.Moreover because clock signal CK1 is in grid noble potential VGH, and switch T1b is unlocked, and makes output signal G
ncurrent potential be promoted to grid noble potential VGH.In addition, node Q
ncurrent potential because of the coupling effect of the stray capacitance of switch T1b and the coupling effect of capacitor C 1, and be promoted to the twice (being 2VGH) of grid noble potential VGH.In addition, because clock signal CK3 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and because of node Q
ncurrent potential be 2VGH, therefore switch T1e can be opened slightly, and have electric current from node Q
nflow to first input end IN1 through switch T1e.
During period T4, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK_2 is second grid electronegative potential VGL2, and switch T1c and T1d are closed.In addition, because clock signal CK1 is pulled down to first grid electronegative potential VGL1, and make node Q
ncurrent potential be pulled down to grid noble potential VGH from the grid noble potential 2VGH of twice because of the coupling effect of the stray capacitance of switch T1b.Moreover, because clock signal CK1 is in first grid electronegative potential VGL1, and node Q
ncurrent potential be grid noble potential VGH, therefore switch T1b can be unlocked, and make output signal G
ncurrent potential be pulled down to first grid electronegative potential VGL1.In addition, because clock signal CK3 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and because of node Q
ncurrent potential be VGH, therefore switch T1e can be opened slightly, and have electric current from node Q
nflow to first input end IN1 through switch T1e.
During period T5, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK_2 is grid noble potential VGH, and switch T1c and T1d are unlocked, and make node Q
ncurrent potential be pulled down to first grid electronegative potential VGL1, and make output signal G
ncurrent potential maintain first grid electronegative potential VGL1.Moreover, because of node Q
ncurrent potential be first grid electronegative potential VGL1, therefore switch T1b can be closed.In addition, because clock signal CK3 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), therefore switch T1e can be opened slightly.Again because of node Q
ncurrent potential be the second grid electronegative potential VGL2 of first grid electronegative potential VGL1 higher than first input end IN1, and have extremely slight electric current from node Q
nflow to first input end IN1 through switch T1e.
During period T6, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK_2 is second grid electronegative potential VGL2, and switch T1c and T1d are closed.In addition, because the current potential of clock signal CK_2 is pulled down to second grid electronegative potential VGL2 from grid noble potential VGH, therefore node Q
ncurrent potential can decline slightly because of the coupling effect of capacitor C 2.Switch T1b is because of node Q
ncurrent potential be closed lower than first grid electronegative potential VGL1, and output signal G
ncurrent potential still maintain first grid electronegative potential VGL1.In addition, because clock signal CK3 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and switch T1e can be opened slightly.
During period T7, the input signal G that shift registor 300 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK_2 is in second grid electronegative potential VGL2, and switch T1c and T1d are closed.Moreover, because clock signal CK3 is in grid noble potential VGH, therefore switch T1e can fully be opened, and make node Q
ncurrent potential can be pulled down to second grid electronegative potential VGL2.Output signal G
ncurrent potential still maintain first grid electronegative potential VGL1.In addition the node Q of rear one-level shift registor,
n+1waveform and the output signal G of current potential
n+1waveform can be respectively and node Q
nwaveform and the output signal G of current potential
nwaveform similar, repeat no more at this.
As shown in the above description, during period T3 to T6, the switch T1e in shift registor 300 can be opened slightly, and during period T7, switch T1e can fully be opened.Therefore the input signal G, exporting at the output terminal of previous stage shift registor
n-1before being not yet again pulled to grid noble potential VGH by first grid electronegative potential VGL1, although clock signal CK1 still can switch between grid noble potential VGH and first grid electronegative potential VGL1, but because of the effect of switch T1e, and can effectively avoid the node Q of shift registor 300
nthe surging at place, therefore can guarantee that shift registor 300 can export the output signal G with precision waveform
n.
In an embodiment of the present invention, the 3rd pull-down circuit 350 of shift registor 300 can be omitted, and the control end of the switch T1e of the second pull-down circuit 340 changes to receive clock signal CK2.Please refer to Fig. 6, the circuit diagram of the shift registor 500 that Fig. 6 is another embodiment of the present invention.Shift registor 500 comprises signal end IN, first input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4, the 5th input end IN5, output terminal Out, pull-up circuit 310, switch T1b, the first pull-down circuit 330 and the second pull-down circuit 540.First input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 receive respectively different clock signal CK_4, CK1, CK_2, CK3 and CK2, and the input signal G that signal end IN exports in order to receive the output terminal of previous stage shift registor
n-1.
The function of pull-up circuit 310, switch T1b and first pull-down circuit 330 of shift registor 500 and mode of operation are identical with pull-up circuit 310, switch T1b and first pull-down circuit 330 of shift registor 300, therefore repeat no more.In addition the second pull-down circuit 540 and node Q of shift registor 500,
n, first input end IN1 and the 5th input end IN5 couple, and in order to the current potential according to the 5th input end IN5, control node Q
nand the electric connection between first input end IN1.In an embodiment of the present invention, the second pull-down circuit 540 comprises switch T1e.The first end of switch T1e is coupled to node Q
n, the second end of switch T1e is coupled to first input end IN1, and the control end of switch T1e is coupled to the 5th input end IN5.Switch T1e, according to clock signal CK2, controls node Q
nand the electric connection between first input end IN1.Because switch T1d and T1e are respectively using clock signal CK3 and CK_4 as its low level signal, therefore can be subject under the impact of positive bias stress (PBS) effect because of operation for a long time at switch T1d and T1e, switch T1d and T1e are imposed to periodic reverse blas stress (NBS) effect, therefore the critical voltage of switch T1d and T1e has reply effect, also therefore the driving force of switch T1d and T1e can be enhanced.
Shift registor 500 can be used for the gate drivers of display panel, and gate driver circuit can comprise multistage shift registor 500, is used to provide multiple signals, to control the open and close of pixel of display panel.Please refer to Fig. 7 and Fig. 5.Fig. 7 is the schematic diagram of the shift scratch circuit 700 of one embodiment of the invention.Shift scratch circuit 700 includes multiple shift registors (as 500_1 to 500_5).Wherein, the circuit framework of each shift registor 500_1 to 500_5 is identical with the shift registor of Fig. 6 500 circuit frameworks.Shift registor 500_1 to 500_5 can be respectively by output terminal Out by output signal G
1to G
5export corresponding gate line (or claiming sweep trace) to, to open in order the pixel coupling from the different gate lines of display panel.The signal end IN of shift registor 500_2 to 500_5 can receive respectively the output signal G of its previous stage shift registor 500_1 to 500_4
1to G
4, the signal end IN of shift registor 500_1 receives start signal SP.In addition, the first input end IN1 of shift registor 500_1 and shift registor 500_5, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 receive respectively clock signal CK_4, CK1, CK_2, CK3 and CK2.First input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 of shift registor 500_2 receive respectively clock signal CK_1, CK2, CK_3, CK4 and CK3.First input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 of shift registor 500_3 receive respectively clock signal CK_2, CK3, CK_4, CK1 and CK4.First input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 of shift registor 500_4 receive respectively clock signal CK_3, CK4, CK_1, CK2 and CK1.
Because shift scratch circuit 700 operates according to eight clock signal CK1 to CK4 and CK_1 to CK_4, therefore shift scratch circuit 700 is also a kind of eight phase shift buffering circuits.Five clock signals that input end IN1 to IN5 receives of N shift registor of shift scratch circuit 700, the clock signal that can receive with five input end IN1 to IN5 of (N+4) individual shift registor is identical, and wherein N is positive integer.For example, first input end IN1, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 of first shift registor 500_1 receive respectively clock signal CK_4, CK1, CK_2, CK3 and CK2, and the clock signal that the first input end IN1 of the 5th shift registor 500_5, the second input end IN2, the 3rd input end IN3, four-input terminal IN4 and the 5th input end IN5 receive can be also clock signal CK_4, CK1, CK_2, CK3 and CK2.
Refer again to Fig. 6 and Fig. 5.During period T1, the input signal G that shift registor 500 receives
n-1with clock signal CK_4 be grid noble potential VGH, and the switch T1a of pull-up circuit 310 is unlocked, and causes node Q
ncurrent potential be grid noble potential VGH.In addition, because clock signal CK3 and CK_2 are respectively in first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and switch T1d is closed.Moreover because clock signal CK_4 is grid noble potential VGH, and the current potential of clock signal CK2 is first grid electronegative potential VGL1, therefore the pressure reduction between the gate-to-source of switch T1e can be great negative value, and switch T1e can closely be closed.In addition, because clock signal CK1 is in first grid electronegative potential VGL1, and switch T1b is unlocked, therefore output signal G
ncurrent potential can be first grid electronegative potential VGL1.
During period T2, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK3 and CK_2 are respectively in first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and switch T1d is closed.Moreover, because the current potential of clock signal CK2 is first grid electronegative potential VGL1, therefore switch T1e can be closed.Therefore, node Q
ncurrent potential can be because of node Q
nmaintain grid noble potential VGH in floating.In addition, because the current potential of clock signal CK1 is still first grid electronegative potential VGL1, therefore output signal G
ncurrent potential can maintain first grid electronegative potential VGL1.
During period T3, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK_2 is in second grid electronegative potential VGL2, and switch T1d is closed.Moreover because clock signal CK1 is in grid noble potential VGH, and switch T1b is unlocked, and makes output signal G
ncurrent potential be promoted to grid noble potential VGH.In addition, node Q
ncurrent potential because of the coupling effect of the stray capacitance of switch T1b and the coupling effect of capacitor C 1, and be promoted to the twice (being 2VGH) of grid noble potential VGH.In addition, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and because of node Q
ncurrent potential be 2VGH, therefore switch T1e can be opened slightly, and have electric current from node Q
nflow to first input end IN1 through switch T1e.
During period T4, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK_2 is second grid electronegative potential VGL2, and switch T1d is closed.In addition, because clock signal CK1 is pulled down to first grid electronegative potential VGL1, and make node Q
ncurrent potential be pulled down to grid noble potential VGH from the grid noble potential 2VGH of twice because of the coupling effect of the stray capacitance of switch T1b.Moreover, because clock signal CK1 is in first grid electronegative potential VGL1, and node Q
ncurrent potential be grid noble potential VGH, therefore switch T1b can be unlocked, and make output signal G
ncurrent potential be pulled down to first grid electronegative potential VGL1.In addition, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and because of node Q
ncurrent potential be VGH, therefore switch T1e can be opened slightly, and have electric current from node Q
nflow to first input end IN1 through switch T1e.
During period T5, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK and CK_2 is grid noble potential VGH, and switch T1d and T1e are unlocked, and make node Q
ncurrent potential be pulled down to second grid electronegative potential VGL2, and make output signal G
ncurrent potential maintain near first grid electronegative potential VGL1.Moreover, because of node Q
ncurrent potential be second grid electronegative potential VGL2, therefore switch T1b can be closed.
During period T6, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because the current potential of clock signal CK_2 is second grid electronegative potential VGL2, and switch T1d is closed.In addition, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and switch T1e can be opened slightly, and make node Q
ncurrent potential maintain second grid electronegative potential VGL2, output signal G
ncurrent potential maintain near first grid electronegative potential VGL1.
During period T7, the input signal G that shift registor 500 receives
n-1be respectively first grid electronegative potential VGL1 and second grid electronegative potential VGL2 with clock signal CK_4, and the switch T1a of pull-up circuit 310 is closed.In addition, because clock signal CK_2 is in second grid electronegative potential VGL2, and switch T1d is closed.Moreover, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (approximately 3 volts), and switch T1e can be opened slightly, and make node Q
ncurrent potential maintain second grid electronegative potential VGL2, output signal G
ncurrent potential maintain near first grid electronegative potential VGL1.In addition the node Q of rear one-level shift registor,
n+1waveform and the output signal G of current potential
n+1waveform can be respectively and node Q
nwaveform and the output signal G of current potential
nwaveform similar, repeat no more at this.
As shown in the above description, during period T3, T4, T6 and T7, the switch T1e in shift registor 500 can be opened slightly, and during period T5, switch T1e can fully be opened.Therefore the input signal G, exporting at the output terminal of previous stage shift registor
n-1before being not yet again pulled to grid noble potential VGH by first grid electronegative potential VGL1, although clock signal CK1 still can switch between grid noble potential VGH and first grid electronegative potential VGL1, but because of the effect of switch T1e, and can effectively avoid the node Q of shift registor 500
nthe surging at place, therefore can guarantee that shift registor 500 can export the output signal G with precision waveform
n.
In addition, in the above description, clock signal CK1, CK_1, CK2, CK_2, CK3, CK_3, CK4, CK_4 also can be called the second clock signal, the 6th clock signal, the 5th clock signal, the 3rd clock signal, the 4th clock signal, the 7th clock signal, the 8th clock signal and the first clock signal.Shift registor 300_1 and 500_1 also can be described as the first shift registor.Shift registor 300_2 and 500_2 also can be described as the second shift registor.Shift registor 300_3 and 500_3 also can be described as the 3rd shift registor.Shift registor 300_4 and 500_4 also can be described as the 4th shift registor.Capacitor C 1 also can be described as the first electric capacity, and capacitor C 2 also can be described as the second electric capacity.Switch T1b, T1c and T1d also can be called the first switch, the 3rd switch and second switch.In addition, period T1, T3, T5 and T7 also can be called the first period, the second period, the 3rd period and the 4th period.In addition, the G in graphic
n+1refer in the prior art " input signal " of shift registor 100, refer in embodiments of the present invention " output signal " of rear one-level shift registor, spy is explained.
In sum, by the shift registor of the embodiment of the present invention, because the switch of each pull-down circuit is all using clock signal as its low level signal, therefore can be at the switch of each pull-down circuit because operating and be subject under the impact of positive bias stress (PBS) effect for a long time, the switch of pull-down circuit is imposed to periodic reverse blas stress (NBS) effect, so that critical voltage (Vth) is produced to recovery effect, improve driving force decline problem.In addition, the switch of the second pull-down circuit can in time be opened slightly or fully open, therefore can suppress to result from because of the coupling effect of the stray capacitance of the first switch the surging of the control end of the first switch.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. a shift registor, is characterized in that, comprises:
One signal end, receives an input signal;
One first input end, receives one first clock signal;
One second input end, receives one second clock signal;
One the 3rd input end, receives one the 3rd clock signal;
One four-input terminal, receives one the 4th clock signal;
One output terminal;
One pull-up circuit, couples with this signal end and this first input end, and in order to according to this first clock signal, controls the electric connection between this signal end and a node;
One first switch, couples with this second input end, this node and this output terminal, and in order to the current potential according to this node, controls the electric connection between this second input end and this output terminal;
One first pull-down circuit, couples with the 3rd input end, this output terminal and this four-input terminal, and in order to according to the 3rd clock signal, controls the electric connection between this output terminal and this four-input terminal; And
One second pull-down circuit, couples with this node and this first input end, and in order to according to the 4th clock signal or one the 5th clock signal, controls the electric connection between this node and this first input end.
2. shift registor according to claim 1, is characterized in that, this first pull-down circuit comprises:
One first electric capacity, is coupled between this node and this output terminal; And
One second switch, a first end of this second switch couples this output terminal, and one second end of this second switch is coupled to this four-input terminal, and a control end of this second switch couples the 3rd input end.
3. shift registor according to claim 1, is characterized in that, this second pull-down circuit is according to the electric connection between this this node of four clock signals control and this first input end.
4. shift registor according to claim 3, is characterized in that, separately comprises:
One the 3rd pull-down circuit, couples with this node, the 3rd input end and this four-input terminal, and in order to according to the 3rd clock signal, controls the electric connection between this node and this four-input terminal.
5. shift registor according to claim 4, is characterized in that, the 3rd pull-down circuit comprises:
One second electric capacity, is coupled between this node and the 3rd input end; And
One the 3rd switch, a first end of the 3rd switch couples this node, and one second end of the 3rd switch couples this four-input terminal, and a control end of the 3rd switch couples the 3rd input end.
6. shift registor according to claim 1, it is characterized in that, this first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are respectively in one first period, one second period, one the 3rd period and one the 4th period are a grid noble potential, and this first period, this second period, the 3rd period and the 4th order of period on time shaft are sequentially this first period, this second period, the 3rd period and the 4th period, and this first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are this high grid potential when different.
7. shift registor according to claim 6, it is characterized in that, more comprise one the 5th input end, in order to receive this five clock signal, wherein this second pull-down circuit is separately coupled to the 5th input end, with the electric connection according between this this node of five clock signals control and this first input end, and the 5th clock signal is this high grid potential in the 3rd period.
8. according to the shift registor described in claim 6 or 7, it is characterized in that, this second clock signal and the 4th clock signal switch between this grid noble potential and a first grid electronegative potential, this first clock signal and the 3rd clock signal switch between this high grid potential and a second grid electronegative potential, and this first grid electronegative potential is higher than this second grid electronegative potential.
9. a shift scratch circuit, comprises multiple shift registors, it is characterized in that, each shift registor comprises:
One signal end;
One first input end;
One second input end;
One the 3rd input end;
One four-input terminal;
One output terminal;
One pull-up circuit, couples with this signal end, a node and this first input end, and in order to the current potential according to this first input end, controls the electric connection between this signal end and this node;
One first switch, couples with this second input end, this node and this output terminal, and in order to the current potential according to this node, controls the electric connection between this second input end and this output terminal;
One first pull-down circuit, couples with the 3rd input end, this output terminal and this four-input terminal, and in order to the current potential according to the 3rd input end, controls the electric connection between this output terminal and this four-input terminal;
One second pull-down circuit, couples with this node, this first input end and this four-input terminal, and in order to the current potential according to this four-input terminal, controls the electric connection between this node and this first input end; And
One the 3rd pull-down circuit, couples with this node, the 3rd input end and this four-input terminal, and in order to the current potential according to the 3rd input end, controls the electric connection between this node and this four-input terminal;
Wherein this first input end, this second input end, the 3rd input end and this four-input terminal receive respectively different clock signals.
10. shift scratch circuit according to claim 9, is characterized in that, those shift registors comprise one first shift registor, one second shift registor, one the 3rd shift registor and one the 4th shift registor;
Wherein this signal end of this first shift registor receives a start signal, this first input end of this first shift registor receives one first clock signal, this second input end of this first shift registor receives one second clock signal, the 3rd input end of this first shift registor receives one the 3rd clock signal, and this four-input terminal of this first shift registor receives one the 4th clock signal;
Wherein this signal end of this second shift registor couples this output terminal of this first shift registor, this first input end of this second shift registor receives one the 6th clock signal, this second input end of this second shift registor receives one the 5th clock signal, the 3rd input end of this second shift registor receives one the 7th clock signal, and this four-input terminal of this second shift registor receives one the 8th clock signal;
Wherein this signal end of the 3rd shift registor couples this output terminal of this second shift registor, this first input end of the 3rd shift registor receives the 3rd clock signal, this second input end of the 3rd shift registor receives the 4th clock signal, the 3rd input end of the 3rd shift registor receives this first clock signal, and this four-input terminal of the 3rd shift registor receives this second clock signal; And
Wherein this signal end of the 4th shift registor couples this output terminal of the 3rd shift registor, this first input end of the 4th shift registor receives the 7th clock signal, this second input end of the 4th shift registor receives the 8th clock signal, the 3rd input end of the 4th shift registor receives the 6th clock signal, and this four-input terminal of the 4th shift registor receives the 5th clock signal.
11. shift scratch circuits according to claim 9, is characterized in that, the 3rd pull-down circuit comprises:
One second electric capacity, is coupled between this node and the 3rd input end; And
One the 3rd switch, a first end of the 3rd switch couples this node, and one second end of the 3rd switch couples this four-input terminal, and a control end of the 3rd switch couples the 3rd input end.
12. 1 kinds of shift scratch circuits, comprise multiple shift registors, it is characterized in that, and each shift registor comprise:
One signal end;
One first input end;
One second input end;
One the 3rd input end;
One four-input terminal;
One the 5th input end;
One output terminal;
One pull-up circuit, couples with this signal end, a node and this first input end, and in order to the current potential according to this first input end, controls the electric connection between this signal end and this node;
One first switch, couples with this second input end, this node and this output terminal, and in order to the current potential according to this node, controls the electric connection between this second input end and this output terminal;
One first pull-down circuit, couples with the 3rd input end, this output terminal and this four-input terminal, and in order to the current potential according to the 3rd input end, controls the electric connection between this output terminal and this four-input terminal; And
One second pull-down circuit, couples with this node, this first input end and the 5th input end, and in order to the current potential according to the 5th input end, controls the electric connection between this node and this first input end;
Wherein this first input end, this second input end, the 3rd input end, this four-input terminal and the 5th input end receive respectively different clock signals.
13. shift scratch circuits according to claim 12, is characterized in that, those shift registors comprise one first shift registor, one second shift registor, one the 3rd shift registor and one the 4th shift registor;
Wherein this signal end of this first shift registor receives a start signal, this first input end of this first shift registor receives one first clock signal, this second input end of this first shift registor receives one second clock signal, the 3rd input end of this first shift registor receives one the 3rd clock signal, this four-input terminal of this first shift registor receives one the 4th clock signal, and the 5th input end of this first shift registor receives one the 5th clock signal;
Wherein this signal end of this second shift registor couples this output terminal of this first shift registor, this first input end of this second shift registor receives one the 6th clock signal, this second input end of this second shift registor receives the 5th clock signal, the 3rd input end of this second shift registor receives one the 7th clock signal, this four-input terminal of this second shift registor receives one the 8th clock signal, and the 5th input end of this second shift registor receives the 4th clock signal;
Wherein this signal end of the 3rd shift registor couples this output terminal of this second shift registor, this first input end of the 3rd shift registor receives the 3rd clock signal, this second input end of the 3rd shift registor receives the 4th clock signal, the 3rd input end of the 3rd shift registor receives this first clock signal, this four-input terminal of the 3rd shift registor receives this second clock signal, and the 5th input end of the 3rd shift registor receives the 8th clock signal; And
Wherein this signal end of the 4th shift registor couples this output terminal of the 3rd shift registor, this first input end of the 4th shift registor receives the 7th clock signal, this second input end of the 4th shift registor receives the 8th clock signal, the 3rd input end of the 4th shift registor receives the 6th clock signal, this four-input terminal of the 4th shift registor receives the 5th clock signal, and the 5th input end of the 4th shift registor receives this second clock signal.
14. according to the shift scratch circuit described in claim 9,11 or 12, it is characterized in that, this first pull-down circuit comprises:
One first electric capacity, is coupled between this node and this output terminal; And
One second switch, a first end of this second switch couples this output terminal, and one second end of this second switch is coupled to this four-input terminal, and a control end of this second switch couples the 3rd input end.
15. according to the shift scratch circuit described in claim 10 or 13, it is characterized in that, this first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are respectively in one first period, one second period, one the 3rd period and one the 4th period are a grid noble potential, the 8th clock signal, the 6th clock signal, the 5th clock signal and the 7th clock signal are respectively in this first period, this second period, the 3rd period and the 4th period are this grid noble potential, and this first period, this second period, the 3rd period and the 4th order of period on time shaft are sequentially this first period, this second period, the 3rd period and the 4th period, this first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are this grid noble potential when different, and the 5th clock signal, the 6th clock signal, the 7th clock signal and the 8th clock signal are this noble potential when different.
16. shift scratch circuits according to claim 15, it is characterized in that, this second clock signal, the 4th clock signal, the 5th clock signal and the 8th clock signal switch between this grid noble potential and a first grid electronegative potential, this first clock signal, the 3rd clock signal, the 6th clock signal and the 7th clock signal switch between this grid noble potential and a second grid electronegative potential, and this first grid electronegative potential is higher than this second grid electronegative potential.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103104773 | 2014-02-13 | ||
| TW103104773A TWI505276B (en) | 2014-02-13 | 2014-02-13 | Shift register circuit and shift register |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103956133A true CN103956133A (en) | 2014-07-30 |
| CN103956133B CN103956133B (en) | 2016-10-05 |
Family
ID=51333399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410196024.9A Active CN103956133B (en) | 2014-02-13 | 2014-05-09 | shift register circuit and shift register |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103956133B (en) |
| TW (1) | TWI505276B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485134A (en) * | 2014-09-10 | 2015-04-01 | 友达光电股份有限公司 | Shift register circuit |
| CN104715733A (en) * | 2015-04-09 | 2015-06-17 | 京东方科技集团股份有限公司 | Shifting register unit, driving circuit, method, array substrate and display device |
| CN105741745A (en) * | 2016-05-12 | 2016-07-06 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display panel |
| WO2016123968A1 (en) * | 2015-02-06 | 2016-08-11 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| WO2016155057A1 (en) * | 2015-03-31 | 2016-10-06 | 深圳市华星光电技术有限公司 | Shift register circuit |
| CN106448606A (en) * | 2016-11-23 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (gate driver on array) driving circuit |
| CN107093399A (en) * | 2017-02-16 | 2017-08-25 | 友达光电股份有限公司 | shift register circuit |
| CN113936585A (en) * | 2021-11-08 | 2022-01-14 | 福建华佳彩有限公司 | GIP circuit and method for reducing display abnormity |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161134B (en) * | 2015-10-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Shift register cell and its operating method, shift register |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1755753A (en) * | 2004-09-29 | 2006-04-05 | 胜华科技股份有限公司 | High stability displacement circuit using amorphous silicon thin film transistor |
| CN1921016A (en) * | 2005-08-22 | 2007-02-28 | 三星Sdi株式会社 | Shift register circuit |
| CN101145398A (en) * | 2006-09-12 | 2008-03-19 | 三星Sdi株式会社 | Shift register and organic light emitting display using the same |
| US20100245298A1 (en) * | 2009-03-24 | 2010-09-30 | Yung-Chih Chen | Shift register capable of reducing coupling effect |
| US20100309191A1 (en) * | 2009-06-04 | 2010-12-09 | Je-Hao Hsu | Shift register and a liquid crystal display device having the same |
| CN102419949A (en) * | 2011-09-02 | 2012-04-18 | 友达光电股份有限公司 | Shift register circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5258582B2 (en) * | 2007-01-31 | 2013-08-07 | 株式会社糖鎖工学研究所 | Trehalose compound, method for producing the same, and immunostimulant containing the compound |
| CN101369460B (en) * | 2008-10-15 | 2012-08-22 | 友达光电股份有限公司 | Shift buffer |
| TWI400686B (en) * | 2009-04-08 | 2013-07-01 | Au Optronics Corp | Shift register of lcd devices |
| TWI410944B (en) * | 2009-06-10 | 2013-10-01 | Au Optronics Corp | Shift register of a display device |
| TWI397259B (en) * | 2010-05-10 | 2013-05-21 | Au Optronics Corp | Shift register circuit |
| TWI437823B (en) * | 2010-12-16 | 2014-05-11 | Au Optronics Corp | Shift register circuit |
| TWI415052B (en) * | 2010-12-29 | 2013-11-11 | Au Optronics Corp | Switch device and shift register circuit using the same |
-
2014
- 2014-02-13 TW TW103104773A patent/TWI505276B/en active
- 2014-05-09 CN CN201410196024.9A patent/CN103956133B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1755753A (en) * | 2004-09-29 | 2006-04-05 | 胜华科技股份有限公司 | High stability displacement circuit using amorphous silicon thin film transistor |
| CN1921016A (en) * | 2005-08-22 | 2007-02-28 | 三星Sdi株式会社 | Shift register circuit |
| CN101145398A (en) * | 2006-09-12 | 2008-03-19 | 三星Sdi株式会社 | Shift register and organic light emitting display using the same |
| US20100245298A1 (en) * | 2009-03-24 | 2010-09-30 | Yung-Chih Chen | Shift register capable of reducing coupling effect |
| US20100309191A1 (en) * | 2009-06-04 | 2010-12-09 | Je-Hao Hsu | Shift register and a liquid crystal display device having the same |
| CN102419949A (en) * | 2011-09-02 | 2012-04-18 | 友达光电股份有限公司 | Shift register circuit |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104485134A (en) * | 2014-09-10 | 2015-04-01 | 友达光电股份有限公司 | Shift register circuit |
| CN104485134B (en) * | 2014-09-10 | 2017-12-26 | 友达光电股份有限公司 | Shift register circuit |
| WO2016123968A1 (en) * | 2015-02-06 | 2016-08-11 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| US10417983B2 (en) | 2015-02-06 | 2019-09-17 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and display apparatus |
| WO2016155057A1 (en) * | 2015-03-31 | 2016-10-06 | 深圳市华星光电技术有限公司 | Shift register circuit |
| GB2549646A (en) * | 2015-03-31 | 2017-10-25 | Shenzhen China Star Optoelect | Shift register circuit |
| GB2549646B (en) * | 2015-03-31 | 2020-06-24 | Shenzhen China Star Optoelect | Shift register circuit |
| WO2016161768A1 (en) * | 2015-04-09 | 2016-10-13 | 京东方科技集团股份有限公司 | Shift register unit, driver circuit, driving method, array substrate, and display device |
| CN104715733A (en) * | 2015-04-09 | 2015-06-17 | 京东方科技集团股份有限公司 | Shifting register unit, driving circuit, method, array substrate and display device |
| US10068658B2 (en) | 2015-04-09 | 2018-09-04 | Boe Technology Group Co., Ltd. | Shift register unit, driving circuit and method, array substrate and display apparatus |
| CN105741745A (en) * | 2016-05-12 | 2016-07-06 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display panel |
| CN106448606A (en) * | 2016-11-23 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (gate driver on array) driving circuit |
| CN107093399A (en) * | 2017-02-16 | 2017-08-25 | 友达光电股份有限公司 | shift register circuit |
| CN113936585A (en) * | 2021-11-08 | 2022-01-14 | 福建华佳彩有限公司 | GIP circuit and method for reducing display abnormity |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI505276B (en) | 2015-10-21 |
| CN103956133B (en) | 2016-10-05 |
| TW201532058A (en) | 2015-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10803823B2 (en) | Shift register unit, gate driving circuit, and driving method | |
| CN103956133A (en) | shift register circuit and shift register | |
| US10438676B2 (en) | Bidirectional shift register units, bidirectional shift registers, and display panels | |
| JP6328153B2 (en) | Shift register, display device, gate drive circuit, and drive method | |
| US10540923B2 (en) | Shift register, method for driving same, gate driving circuit | |
| CN103280200B (en) | Shift register unit, gate drive circuit and display device | |
| US9928797B2 (en) | Shift register unit and driving method thereof, gate driving apparatus and display apparatus | |
| WO2017107295A1 (en) | Goa circuit applicable to in cell-type touch display panel | |
| CN106782282A (en) | Shift register, gate driving circuit, display panel and driving method | |
| CN102270434A (en) | Display driving circuit | |
| CN106935168B (en) | Shift register and display device | |
| CN111684528B (en) | Shift register and driving method thereof, grid driving circuit and display device | |
| CN105206244A (en) | GOA circuit and liquid crystal display | |
| JP2020517994A (en) | Scan drive circuit | |
| US11410608B2 (en) | Shift register circuitry, gate driving circuit, display device, and driving method thereof | |
| CN104282255A (en) | Shifting register, gate drive circuit, driving method of gate drive circuit and displaying device | |
| CN105336291A (en) | Shift register unit, driving method thereof and display device | |
| CN106782280A (en) | Shift register and grid drive circuit | |
| CN106448536A (en) | Shifting register, grid driving circuit, display panel and driving method | |
| KR102056674B1 (en) | Gate shift register and method for driving the same | |
| EP3570269B1 (en) | Goa circuit and liquid crystal display | |
| CN108154856B (en) | Grid scanning driving circuit | |
| CN107564459A (en) | Shift register cell, gate driving circuit, display device and driving method | |
| CN106611582A (en) | Shift register, grid driving circuit, display panel and driving method | |
| CN110189681B (en) | Shifting register unit, driving method, grid driving circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |