CN106598485A - Microcontroller and low-power consumption EEPROM interface circuit - Google Patents
Microcontroller and low-power consumption EEPROM interface circuit Download PDFInfo
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- CN106598485A CN106598485A CN201611038637.5A CN201611038637A CN106598485A CN 106598485 A CN106598485 A CN 106598485A CN 201611038637 A CN201611038637 A CN 201611038637A CN 106598485 A CN106598485 A CN 106598485A
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- eeprom
- microcontroller
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- 230000001934 delay Effects 0.000 claims description 13
- 238000003860 storage Methods 0.000 abstract description 7
- 230000003111 delayed effect Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a microcontroller and a low-power consumption EEPROM interface circuit thereof. The microcontroller comprises a clock module, an EEPROM storage, an EEPROM interface control module, a code option module and a microcontroller core, wherein the microcontroller core is connected with the clock module and the EEPROM storage respectively, the clock module is also connected with the EEPROM storage that is also connected with the storage and the code option module respectively. According to the microcontroller provided by the invention, power consumption of the EEPROM storage can be saved by performing low-power consumption read time sequence control on the EEPROM storage by using the EEPROM interface control module, and thus the chip of the microcontroller is applicable to a requirement on low-power consumption application. According to the microcontroller provided by the invention, the scheme can be applicable to EEPROM design projects with different types and different performance by changing delay control information of a delay control unit in the chip of the microcontroller, and has the advantages of wide application range and high practicability.
Description
Technical field
The present invention relates to MCU technical fields, specifically a kind of microcontroller and its low-power consumption EEPROM interface circuit.
Background technology
Microcontroller chip has a wide range of applications as a kind of general control chip.In some applications, it is right
The power consumption requirements of microcontroller are very strict.The present invention proposes a kind of microcontroller and its EEPROM interface circuit arrangement, in chip
In the reading sequencing contro for carrying out low-power consumption to eeprom memory by EEPROM interface management module, EEPROM can be saved
The power consumption of memorizer, so that microcontroller chip is applied to low-power consumption application requirement.
The content of the invention
It is an object of the invention to provide a kind of microcontroller and its low-power consumption EEPROM interface circuit, to solve the above-mentioned back of the body
The problem proposed in scape technology.
For achieving the above object, the present invention provides following technical scheme：
A kind of microcontroller and its low-power consumption EEPROM interface circuit, including clock module, eeprom memory, EEPROM interface
Control module, code options module and microcontroller core, the microcontroller core connects respectively clock module and EEPROM
Memorizer, clock module is also connected with eeprom memory, and eeprom memory is also respectively connected with memorizer and code options module.
As the further scheme of the present invention：The EEPROM interface control module include 3 delays time to control units, two
Phase inverter and two and door.
Compared with prior art, the invention has the beneficial effects as follows：The present invention passes through EEPROM interface management module pair
Eeprom memory carries out the reading sequencing contro of low-power consumption, can save the power consumption of eeprom memory, so that microcontroller
Chip is applied to low-power consumption application requirement.The present invention can also pass through the time delay for changing delays time to control unit in microcontroller chip
Control information, enables scheme to be applied to the design object of the EEPROM of different type and different performance, with the suitability it is wide,
Practical advantage.
Description of the drawings：
Fig. 1 is the entire block diagram of the present invention；
Fig. 2 is the block diagram of EEPROM interface control module.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Refer to Fig. 1-2, a kind of microcontroller of present invention description and its low-power consumption EEPROM interface circuit, including clock mould
Block, eeprom memory, EEPROM interface control module, code options module and microcontroller core, in the microcontroller
Core connects respectively clock module and eeprom memory, and clock module is also connected with eeprom memory, and eeprom memory also divides
Lian Jie not memorizer and code options module.
EEPROM interface control module includes 3 delays time to control units, two phase inverters and two and door.
The operation principle of this programme:As shown in Figure 1.Microcontroller includes clock module（CLOCK）, EEPROM deposits
Reservoir, EEPROM interface control module（EEPROM_INTF）, code options module（OPTION）, microcontroller core（MCU_
CORE）.Clock module（CLOCK）It is responsible for producing the work clock required for chip operation.When microcontroller core request is read
When being stored in the corresponding content in a certain address in EEPROM, microcontroller core（MCU_CORE）EEPROM is effectively read in output please
Seek signal（e2c_rd）, while exporting corresponding reading address signal（e2c_adr）.When EEPROM interface control module（EEPROM_
INTF）Detect and effectively read EEPROM request signals（e2c_rd）When, the low-power consumption produced needed for eeprom memory is connect
Mouthful sequential, reads back the value of appropriate address unit from EEPROM, and by the value read back（e2c_din）It is transported to microcontroller
Kernel（MCU_CORE）.Code options module（OPTION）It is responsible for configuration of overall importance to chip to be controlled.In the design, this
The time delay of a little each delays time to control units configured during control information are included for EEPROM interface module in control chip of overall importance
Control information（dly_ctrl1、dly_ctrl2、dly_ctrl3）.
When EEPROM interface control module (EEPROM_INTF) is responsible for the interface needed for regulation management reading eeprom memory
Sequence.The temporal model that EEPROM interface control module reads EEPROM is as shown in Figure 2.E2c_cs believes for the gating of eeprom memory
Number；E2c_rd is EEPROM read request pulse signals；E2c_adr is EEPROM read request address signals；E2c_dout is
EEPROM reads return data signal.When reading EEPROM, interface sequence has to meet the gating signal of eeprom memory
(e2c_cs) relative to EEPROM read request pulse signals (e2c_rd) setup time requirement, while also to meet EEPROM
The gating signal (e2c_cs) of memorizer will relative to the sequential of the retention time of EEPROM read request pulse signals (e2c_rd)
Ask.Read three kinds of power consumption modes that eeprom memory operation is related to EEPROM storages.When the gating signal of eeprom memory
For low level state (e2c_cs=0) when, eeprom memory be in standby patterns.When the gating of eeprom memory is believed
When number being low level state (e2c_rd=1) for high effective status (e2c_cs=1) and EEPROM read requests pulse signal,
Eeprom memory is in read patterns.When eeprom memory gating signal be high effective status (e2c_cs=1) and
When EEPROM read requests pulse signal is low level state (e2c_rd=0), eeprom memory is in static patterns.It is different
The eeprom memory that provides of IP providers in power consumption, performance have difference.When EEPROM is in standby patterns, work(
Consumption is minimum.The power consumption of static patterns is bigger than standby pattern, less than read mode power consumption.In microcontroller chip design
In, in order to be conducive to chip in Digital Logic design, the dutycycle of microcontroller core work clock (clk_core) is general
For 50%.In the design of general microcontroller chip, when microcontroller is in running status, can be by eeprom memory
Gating signal always remain as high effective status, while using microcontroller core work clock (clk_core) as
EEPROM read request pulse signals (e2c_rd).In this design, when microcontroller is in running status, EEPROM
Memorizer is alternately in the higher read patterns of power consumption and static patterns.
The design principle of EEPROM interface control module is as shown in Figure 2.EEPROM interface management module is according to code options
Module（OPTION）The delays time to control information of the delays time to control unit for transmitting（dly_ctrl1、dly_ctrl2、dly_
ctrl3）To EEPROM interface control module（EEPROM_INTF）The output time delay of middle delay unit is controlled.Microcontroller
Core clock clk_core is through delays time to control unit 1（DELAY_CELL_1）Afterwards, a time delayed signal clk_core_ is exported
Dly1, a time delayed signal clk_core_dly1 are dly1 relative to the delay time of microcontroller core clock clk_core,
Delays time to control information can be passed through（dly_ctrl1）Delay time is regulated and controled for dly1.Time delayed signal clk_core_
Dly1 is through delays time to control unit 2（DELAY_CELL_2）Afterwards, secondary delay signal clk_core_dly2, secondary delay are exported
Delay times of the signal clk_core_dly2 with respect to a time delayed signal clk_core_dly1 is dly2, can pass through time delay control
Information processed（dly_ctrl2）Delay time is regulated and controled for dly2.Secondary delay signal clk_core_dly2 is through time delay control
Unit processed 3（DELAY_CELL_3）Afterwards, three time delayed signal clk_core_dly3, three time delayed signal clk_core_ are exported
Delay times of the dly3 with respect to secondary delay signal clk_core_dly2 is dly3, can pass through delays time to control information（DELAY_
CELL_3）Delay time is regulated and controled for dly3.As shown in Fig. 2 secondary delay signal clk_core_dly2 is through anti-phase
After device is negated, the input of two inputs and door is connected to together with microcontroller core clock clk_core, the output with door is believed
Number as read eeprom memory read request pulse signal（e2c_rd）To drive eeprom memory interface.Three time delays are believed
Number clk_core_dly3 after phase inverter is negated, be connected to together with microcontroller core clock clk_core two inputs with
The input of door, with the output signal of door as eeprom memory gating signal（e2c_cs）To drive eeprom memory
Interface.By changing delays time to control information（dly_ctrl1、dly_ctrl2、dly_ctrl3）To EEPROM interface control module
（EEPROM_INTF）The output time delay of middle delay unit is controlled, and can make read request pulse signal（e2c_rd）Meet arteries and veins
The requirement of minimum pulse width duration is wider than, while it is less to make its pulsewidth try one's best, can be made during eeprom memory is read,
Eeprom memory is only in the read power consumption modes that power consumption is of a relatively high in the relatively short time.Also, by reading
Take eeprom memory data successfully return after, by the gating signal of eeprom memory（e2c_cs）Close, so that
Eeprom memory is only in the of a relatively high static power consumption modes of power consumption in the relatively short time, in remaining time,
Eeprom memory can substantially reduce the work(of microcontroller all in the relatively low standby power consumption modes of power consumption
Consumption.
Claims (2)
1. a kind of microcontroller and its low-power consumption EEPROM interface circuit, including clock module, eeprom memory, EEPROM connect
Mouth control module, code options module and microcontroller core, it is characterised in that the microcontroller core connects respectively clock
Module and eeprom memory, clock module is also connected with eeprom memory, eeprom memory be also respectively connected with memorizer and
Code options module.
2. a kind of microcontroller according to claim 1 and its low-power consumption EEPROM interface circuit, it is characterised in that described
EEPROM interface control module includes 3 delays time to control units, two phase inverters and two and door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611038637.5A CN106598485A (en) | 2016-11-23 | 2016-11-23 | Microcontroller and low-power consumption EEPROM interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611038637.5A CN106598485A (en) | 2016-11-23 | 2016-11-23 | Microcontroller and low-power consumption EEPROM interface circuit |
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| Publication Number | Publication Date |
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| CN106598485A true CN106598485A (en) | 2017-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611038637.5A Pending CN106598485A (en) | 2016-11-23 | 2016-11-23 | Microcontroller and low-power consumption EEPROM interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170483A (en) * | 2017-06-01 | 2017-09-15 | 深圳市博巨兴实业发展有限公司 | A kind of low-power consumption ROM interface circuits in MCU chip |
| CN110488673A (en) * | 2019-06-26 | 2019-11-22 | 珠海格力电器股份有限公司 | A kind of data processing module and data processing method of low-power consumption mode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371869A (en) * | 1991-04-03 | 1994-12-06 | Samsung Electronics Co., Ltd. | Micro-controller unit for selectively accessing an internal memory or an external extended memory using a read/write terminal |
| CN101114521A (en) * | 2007-08-28 | 2008-01-30 | 钜泉光电科技（上海）有限公司 | Power consumption controlling method and system of flash memory |
| CN201853473U (en) * | 2010-06-30 | 2011-06-01 | 福建捷联电子有限公司 | Display capable of automatically burning EDID when being started for first time |
-
2016
- 2016-11-23 CN CN201611038637.5A patent/CN106598485A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371869A (en) * | 1991-04-03 | 1994-12-06 | Samsung Electronics Co., Ltd. | Micro-controller unit for selectively accessing an internal memory or an external extended memory using a read/write terminal |
| CN101114521A (en) * | 2007-08-28 | 2008-01-30 | 钜泉光电科技（上海）有限公司 | Power consumption controlling method and system of flash memory |
| CN201853473U (en) * | 2010-06-30 | 2011-06-01 | 福建捷联电子有限公司 | Display capable of automatically burning EDID when being started for first time |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170483A (en) * | 2017-06-01 | 2017-09-15 | 深圳市博巨兴实业发展有限公司 | A kind of low-power consumption ROM interface circuits in MCU chip |
| CN110488673A (en) * | 2019-06-26 | 2019-11-22 | 珠海格力电器股份有限公司 | A kind of data processing module and data processing method of low-power consumption mode |
| CN110488673B (en) * | 2019-06-26 | 2021-04-20 | 珠海零边界集成电路有限公司 | Data processing module and data processing method in low power consumption mode |
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Application publication date: 20170426 |