CN207134139U - A kind of low-power consumption ROM interface circuits in MCU chip - Google Patents

A kind of low-power consumption ROM interface circuits in MCU chip Download PDF

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Publication number
CN207134139U
CN207134139U CN201720625412.3U CN201720625412U CN207134139U CN 207134139 U CN207134139 U CN 207134139U CN 201720625412 U CN201720625412 U CN 201720625412U CN 207134139 U CN207134139 U CN 207134139U
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rom
mcu
power consumption
rom interface
chip
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万上宏
叶媲舟
涂柏生
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Shenzhen Bojuxing Microelectronics Technology Co., Ltd.
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SHENZHEN BOJUXING INDUSTRIAL DEVELOPMENT Co Ltd
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Abstract

The utility model is the low-power consumption ROM interface circuits in a kind of MCU chip, including MCU kernels, ROM interface control modules, ROM memory, chip configuration control module and clock module, the MCU kernels connect ROM interface control modules and clock module respectively, and ROM interface control modules are also respectively connected with memory, chip configuration control module and clock module.The utility model proposes the low-power consumption ROM interface circuit schemes in a kind of MCU chip, the reading SECO for carrying out low-power consumption to ROM memory by ROM interface administration modules in the chips, the power consumption of ROM memory can be saved, so that MCU chip is applied to low-power consumption application requirement.The utility model can also enable scheme to be applied to the ROM of different type and different performance design object by changing the delays time to control information of delays time to control unit in MCU chip, have applicability it is wide, it is practical the advantages of.

Description

A kind of low-power consumption ROM interface circuits in MCU chip
Technical field
It the utility model is related to a kind of interface circuit, the low-power consumption ROM interface circuits in specifically a kind of MCU chip.
Background technology
MCU chip has to be widely applied very much.Program storage inside many MCU chips all uses low cost ROM memory.Application of the in the market for MCU chip needs varied, is directed to that those are very sensitive for cost, simultaneously For the application scenario of a relatively high to MCU chip power consumption requirements, the designer of MCU chip is by inside MCU chip Met difficulty in ROM power consumption controls.This is the application scenario of low-power consumption, for MCU chip, accesses internal ROM memory Power consumption may exceed application scenario permission size.The utility model proposes the low-power consumption ROM in a kind of MCU chip to connect Mouth circuit arrangement, the reading SECO for passing through ROM interface administration modules and low-power consumption being carried out to ROM memory in the chips, energy The power consumption of ROM memory is enough saved, so that MCU chip is applied to low-power consumption application requirement.The utility model can also pass through Change the delays time to control information of delays time to control unit in MCU chip, scheme is applied to different type and different performance ROM design object, have applicability it is wide, it is practical the advantages of.
Utility model content
The purpose of this utility model is in the low-power consumption ROM interface circuits in a kind of MCU chip is provided, to solve the above-mentioned back of the body The problem of being proposed in scape technology.
To achieve the above object, the utility model provides following technical scheme:
A kind of low-power consumption ROM interface circuits in MCU chip, including MCU kernels, ROM interface control modules, ROM storage Device, chip configuration control module and clock module, the MCU kernels connect ROM interface control modules and clock module respectively, ROM interface control modules are also respectively connected with memory, chip configuration control module and clock module.
As further technical scheme of the present utility model:The ROM interface control modules include delays time to control unit A, Delays time to control unit B and delays time to control unit C, delays time to control unit A input connection delay control signal clk_mcu are defeated Go out end connection and door Y1 input, the input connection delay control signal clk_mcu_d1 of delays time to control unit B, output end NOT gate F1, NOT gate F1 output end connection and door Y1 another input are connected, delays time to control unit C input connection is prolonged When control signal clk_mcu_d2, output end connection NOT gate F2, NOT gate F2 output end connection and door Y2 another input, Delay control signal clk_mcu is connected with door Y2 another input.
Compared with prior art, the beneficial effects of the utility model are:The utility model proposes low in a kind of MCU chip Power consumption ROM interface circuit schemes, in the chips by ROM interface administration modules to ROM memory carry out low-power consumption reading when Sequence controls, and the power consumption of ROM memory can be saved, so that MCU chip is applied to low-power consumption application requirement.The utility model is also Scheme can be enable to be applied to different type and not by changing the delays time to control information of delays time to control unit in MCU chip With the ROM of performance design object, have applicability it is wide, it is practical the advantages of.
Brief description of the drawings
Fig. 1 is MCU system block diagram.
Fig. 2 is ROM interface control module block diagrams.
Fig. 3 is ROM temporal model schematic diagram.
Embodiment
The technical scheme in the embodiment of the utility model will be clearly and completely described below, it is clear that described Embodiment is only the utility model part of the embodiment, rather than whole embodiments.Based on the implementation in the utility model Example, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, is belonged to The scope of the utility model protection.
Refering to Fig. 1-3;In the utility model embodiment, the low-power consumption ROM interface circuits in a kind of MCU chip, including MCU Kernel, ROM interface control modules, ROM memory, chip configuration control module and clock module, the MCU kernels connect respectively ROM interface control modules and clock module, ROM interface control modules be also respectively connected with memory, chip configuration control module and Clock module.
ROM interface control modules include delays time to control unit A, delays time to control unit B and delays time to control unit C, delay control Unit A processed input connection delay control signal clk_mcu, output end connection and door Y1 input, delays time to control unit B Input connection delay control signal clk_mcu_d1, output end connection NOT gate F1, NOT gate F1 output end connection with door Y1 Another input, delays time to control unit C input connection delay control signal clk_mcu_d2, output end connection NOT gate F2, NOT gate F2 output end connection and door Y2 another input, delays time to control letter is connected with door Y2 another input Number clk_mcu.
Operation principle of the present utility model is:Include clock module inside MCU chip(CLOCK), ROM memory, ROM connect Mouth control module(ROM_INTF), chip configuration control module(CONFIG), MCU kernels(MCU_CORE).Clock module (CLOCK)It is responsible for producing the work clock required for chip operation.A certain address in ROM is stored in when MCU kernel requests are read During corresponding content, MCU kernels(MCU_CORE)Output is effective to read ROM request signals(rom_rd), while corresponding to output Read address signal(rom_adr).When ROM interface control modules(ROM_INTF)Detect effective reading ROM request signals(rom_ rd)When, the low-power consumption interface sequence needed for ROM memory will be produced, the value of appropriate address unit is read back from ROM, and The value that will be read back(rom_din)It is transported to MCU kernels(MCU_CORE).Chip configuration control module(CONFIG)It is responsible for chip Configuration of overall importance is controlled.In the design, these configuration control information of overall importance include being used for ROM interfaces in control chip The delays time to control information of each delays time to control unit in module(cfg_dly1、cfg_dly2、cfg_dly3).
ROM interface control modules(ROM_INTF)It is responsible for the interface sequence needed for regulation management reading ROM memory.ROM connects The temporal model that mouth control module reads ROM is as shown in Figure 3.Rom_cs is the gating signal of ROM memory;Rom_rd reads for ROM Ask pulse signal;Rom_adr is ROM read request address signals;Rom_dout is that ROM reads return data signal.When reading ROM, The gating signal (rom_cs) that interface sequence has to meet ROM memory is relative to ROM read requests pulse signal (rom_rd) Settling time requirement, while also to meet the gating signal (rom_cs) of ROM memory relative to ROM read request pulses The timing requirements of the retention time of signal (rom_rd).Read three kinds of power consumption modes that ROM memory operation is related to ROM storages. When the gating signal of ROM memory is low level state (rom_cs=0), ROM memory is in standby patterns.Work as ROM The gating signal of memory is high effective status (rom_cs=1) and ROM read requests pulse signal is low level state(rom_rd= 1)When, ROM memory is in read patterns.When the gating signal of ROM memory is read for high effective status (rom_cs=1) and ROM Request pulse signal is low level state(rom_rd=0)When, ROM memory is in static patterns.Different IP providers carry The ROM memory of confession has difference in power consumption, performance.When ROM is in standby patterns, power consumption is minimum.Static patterns Power consumption is bigger than standby pattern, smaller than read mode power consumption.In MCU chip design, patrolled to be advantageous to numeral in chip The design collected, MCU Core Operational clocks(clk_mcu)Dutycycle be generally 50%.In the design of in general MCU chip, when When MCU is in running status, the gating signal of ROM memory can be always remained as to high effective status, while use MCU kernels Work clock(clk_mcu)As ROM read request pulse signals(rom_rd).In this design, when MCU is in operation During state, ROM memory is alternately in the higher read patterns of power consumption and static patterns.
The utility model proposes a kind of low-power consumption Managed Solution of MCU chip, in MCU chip design, passes through MCU chip Internal ROM interface administration modules, the power consumption mode management of intelligence can be carried out to ROM memory.When reading ROM memory, Meet the MCU calculation process speed of application requirement, and meet the premise of the constraint of the interface sequence required by ROM memory Under, by making ROM memory inside the as far as possible short time in the read patterns that power consumption is higher, inside the as far as possible long time The standby pattern relatively low in power consumption, so that the total power consumption of MCU chip is lower, makes MCU chip can apply to power consumption It is required that lower application scenario.
The design principle of ROM interface control modules is as shown in Figure 2.ROM interface administration modules configure control mould according to chip Block(CONFIG)The delays time to control information of the delays time to control unit transmitted(cfg_dly1、cfg_dly2、cfg_dly3)It is right ROM interface control modules(ROM_INTF)The output delay of middle delay unit is controlled.MCU core clocks clk_mcu passes through Delays time to control unit 1(DELAY_C1)Afterwards, time delayed signal a clk_mcu_dly1, a time delayed signal clk_mcu_ are exported Dly1 is dly1 relative to MCU core clocks clk_mcu delay time, can pass through delays time to control information(cfg_dly1)It is right Delay time is that dly1 is regulated and controled.One time time delayed signal clk_mcu_dly1 passes through delays time to control unit 2(DELAY_C2)Afterwards, Export with respect to one time time delayed signal clk_mcu_ of secondary delay signal clk_mcu_dly2, secondary delay signal clk_mcu_dly2 Dly1 delay time is dly2, can pass through delays time to control information(cfg_dly2)It is that dly2 regulates and controls to delay time. Secondary delay signal clk_mcu_dly2 passes through delays time to control unit 3(DELAY_C3)Afterwards, time delayed signal clk_ three times is exported Mcu_dly3, three times time delayed signal clk_mcu_dly3 be with respect to secondary delay signal clk_mcu_dly2 delay time Dly3, delays time to control information can be passed through(DELAY_C3)It is that dly3 regulates and controls to delay time.As shown in Fig. 2 secondary prolong When signal clk_mcu_dly2 after phase inverter negates, two inputs and door are connected to together with MCU core clocks clk_mcu Input, the output signal with door is as the read request pulse signal for reading ROM memory(rom_rd)To drive ROM memory to connect Mouthful.Time delayed signal clk_mcu_dly3 is connected to two after phase inverter negates together with MCU core clocks clk_mcu three times Input and the input of door, with the gating signal of the output signal of door as ROM memory(rom_cs)To drive ROM memory Interface.By changing delays time to control information(cfg_dly1、cfg_dly2、cfg_dly3)To ROM interface control modules(ROM_ INTF)The output delay of middle delay unit is controlled, and can make read request pulse signal(rom_rd)Meet that pulsewidth is more than most The requirement of small pulsewidth duration, while it is smaller its pulsewidth is tried one's best, and can make during ROM memory is read, ROM memory is only In the read power consumption modes that power consumption is of a relatively high in the relatively short time.Also, by reading the number of ROM memory After successfully returning, by the gating signal of ROM memory(rom_cs)Close, so that ROM memory is only relatively short In the static power consumption modes that power consumption is of a relatively high in time, in remaining time, ROM memory is relatively low all in power consumption Standby power consumption modes, therefore MCU power consumption can be substantially reduced.

Claims (2)

1. the low-power consumption ROM interface circuits in a kind of MCU chip, including MCU kernels, ROM interface control modules, ROM memory, Chip configuration control module and clock module, it is characterised in that the MCU kernels connect respectively ROM interface control modules and when Clock module, ROM interface control modules are also respectively connected with memory, chip configuration control module and clock module.
2. the low-power consumption ROM interface circuits in a kind of MCU chip according to claim 1, it is characterised in that the ROM Interface control module includes delays time to control unit (A), delays time to control unit (B) and delays time to control unit (C), delays time to control unit (A) input connection delay control signal clk_mcu, output end connection and the input of door (Y1), delays time to control unit (B) Input connection delay control signal clk_mcu_d1, output end connection NOT gate (F1), NOT gate (F1) output end connection with Another input of door (Y1), the input connection delay control signal clk_mcu_d2 of delays time to control unit (B), output end Connect NOT gate (F2), the output end connection of NOT gate (F2) and another input of door (Y2), another input with door (Y2) End connection delay control signal clk_mcu.
CN201720625412.3U 2017-06-01 2017-06-01 A kind of low-power consumption ROM interface circuits in MCU chip Active CN207134139U (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Address after: 518051 Shenzhen Nanshan District, Guangdong Province, Guangdong Province, Yuehai Street High-tech Zone Community Science and Technology South Road 18 Shenzhen Bay Science and Technology Eco-Park 12 Skirt Building 732

Patentee after: Shenzhen Bojuxing Microelectronics Technology Co., Ltd.

Address before: 518000 4th Floor, New Material Port D(4) Building, No.2 Changyuan New Material Port, Zhongxin Road, Nanshan District, Shenzhen City, Guangdong Province

Patentee before: Shenzhen Bojuxing Industrial Development Co., Ltd.