CN106597261A - Wafer test system - Google Patents
Wafer test system Download PDFInfo
- Publication number
- CN106597261A CN106597261A CN201611264465.3A CN201611264465A CN106597261A CN 106597261 A CN106597261 A CN 106597261A CN 201611264465 A CN201611264465 A CN 201611264465A CN 106597261 A CN106597261 A CN 106597261A
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- China
- Prior art keywords
- test
- wafer
- data
- display
- chip
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a wafer test system. The wafer test system comprises a test unit, a control unit, a data storage unit and a display and interaction unit, wherein the test unit is used for testing wafers and storing test data into the data storage unit, the control unit is used for extracting test data of a designated wafer from the data storage unit according to an instruction received by the display and interaction unit and controlling the display and interaction unit for displaying the specific test data of the designated test wafer through one-two-dimensional images according to a designated display mode. The wafer test system is advantaged in that a problem that the specific test information of a test wafer can not be conveniently acquired by a traditional wafer test system in the prior art is solved.
Description
Technical field
The present invention relates to technical field of integrated circuits, and in particular to a kind of wafer test system.
Background technology
The main purpose of wafer sort is to carry out electric function test to the chip in wafer, and bad cDNA microarray is gone out
Come, while according to electrical bad type underproof product classification, there is provided carry out data analysis and work to wafer fabrication
Skill is improved.
At present, in IC wafers industrialization test, wherein, a kind of mode is that correspondence chip is represented by color not
Same failure type, such as green are all to pass through, red to fail for contact, and yellow is disabler etc., is finally reflected in drafting
Wafer two dimensional image on；Another way, directly adopts green and passes through for correspondence chip testing, and redness is surveyed for correspondence chip
Examination does not pass through, and is finally reflected on the two dimensional image of the wafer of drafting.
Above method all there is a problem of common, i.e. whether the corresponding chip of two dimensional image that can only find out wafer is tested
Pass through, at most will appreciate that its failure type, but specifically which test does not pass through, its test value is how many and design mark
Standard the specific information such as differs and cannot intuitively obtain.To obtain these specifying informations, need to remember from the test of magnanimity
Make a look up in record, be inconvenient.
The content of the invention
To solve the problems, such as that traditional wafer test system cannot easily obtain the concrete test information of wafer sort, this
It is bright there is provided a kind of wafer test system.
The invention provides a kind of wafer test system, including test cell, control unit, data storage cell and display
With interactive unit；The test cell is used to test wafer, and test data is stored in into the data storage cell；
Described control unit extracts the test wafer specified according to the instruction that receives with interactive unit is shown from data storage cell
Test data, and control to show test crystalline substance that this specifies is shown by a two dimensional image according to specified display pattern with interactive unit
Round concrete test data.
Optionally, the concrete test data is the concrete test value of nominative testing project..
Optionally, described display is with the display pattern of interactive unit：In X-Y scheme corresponding with specified test wafer
As upper, the concrete test value of the nominative testing project of the test wafer specified is shown on each chip image.
Optionally, described display is with the display pattern of interactive unit：In X-Y scheme corresponding with specified test wafer
As upper, the corresponding chip testing that designated color is shown on each chip image to represent the test wafer specified passes through or surveys
Examination does not pass through, and when putting the fixed chip image of fingertip, the display can show that the chip image specified is corresponding with interactive unit
The information of all test events of chip.
Optionally, it is described to show as follows with the display pattern of interactive unit：Described control unit is brilliant by multiple same class testings
Round two dimensional image is overlapped process, and the same coordinate chip of all similar test wafers is tested and do not passed through, then this coordinate
Chip shows designated color.
Optionally, also including a data processing unit, the data processing unit is whole for entering row format to test data
Reason, and the test data after arrangement is stored in into data storage cell.
Optionally, the test data after the data processing unit is arranged, comprising following information：Test event type, survey
The lot number of examination wafer, wafer are numbered, test time started, test end time, test event highest and minimum limit value, concrete core
The coordinate of piece and the concrete test value of nominative testing project.
Optionally, the test cell is that wafer permits Acceptance Tests board.
Optionally, the test cell is chip probe tester table.
Optionally, the display includes display, mouse and keyboard with interactive unit.
Optionally, the display includes a touch-screen with interactive unit.
Optionally, the data storage cell is server.
Optionally, the data storage cell includes operational memory cell and redundant memory cell, and the work storage is single
Unit exchanges for normal data storage, and the redundant memory cell is backed up in realtime the data of operational memory cell.
The wafer test system provided using the present invention, the instruction that control unit is received according to display with interactive unit, from
The test data of the test wafer specified is extracted in data storage cell, and controls to show with interactive unit according to specified display mould
Formula shows the concrete test data of the test wafer specified by a two dimensional image, and the test data of wafer can intuitively show
In display and interactive unit, the tedious steps searched from magnanimity test data are eliminated, improve data analysis efficiency.
Description of the drawings
Fig. 1 is the intention of the wafer test system that the embodiment of the present invention one is provided；
Fig. 2 is that the display wafer image of the wafer test system that the embodiment of the present invention one is provided is intended to；
Fig. 3 is the display wafer image schematic diagram of the wafer test system that the embodiment of the present invention two is provided；
The description of symbols of 1～accompanying drawing of accompanying drawing 3 is as follows：
101- test cells；102- control units；103- data storage cells；104- data processing units；105- shows
With interactive unit；201st, the corresponding two dimensional image of 301- test wafers；202nd, 302- chip images.
Specific embodiment
The method that board proposed by the present invention is disposed extremely is described in detail below in conjunction with the drawings and specific embodiments.
According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is using very
Simplified form and non-accurately ratio is used, only to purpose that is convenient, lucidly aiding in illustrating the embodiment of the present invention.
<Embodiment one>
The invention provides a kind of wafer test system, as shown in figure 1, including test cell 101, control unit 102, number
According to memory cell 103 and display and interactive unit 105；The test cell 101 is used to test wafer, and will test number
According to being stored in the data storage cell 103；The instruction that described control unit 102 is received according to display with interactive unit 105, from
The test data of the test wafer specified is extracted in data storage cell 103, and controls to show with interactive unit 105 according to specified
Display pattern shows the concrete test data of the test wafer specified by a two dimensional image.
The wafer test system of the present embodiment also includes a data processing unit 104, the logarithm of the data processing unit 104
Form collator is carried out according to the test data in memory cell 103, and the test data after arrangement is stored in into data storage cell
103.Specifically, the test data after arrangement, comprising following information：Test event type, the lot number of test wafer, wafer are compiled
Number, test time started, test end time, test event highest and minimum limit value, the coordinate of concrete chip and specifying survey
The concrete test value of examination project.It is understood that reduced data can cover the data before arranging；Reduced data
Also the non-storage region of data storage cell 103 can be stored in.The data processing unit 104 of the present embodiment is a server, can be with
It is understood by, the processing unit is alternatively a single-chip microcomputer.
The test cell 101 of the present embodiment is that wafer permits Acceptance Tests board, it is to be understood that test cell 101 also may be used
Being chip probe tester table.Data storage cell 103 is a server, specifically, can include workspace server and standby
Part server, workspace server is used for normal data storage and exchanges, and the backup server is backed up in realtime workspace server
In data.It is understood that memory cell also can only include workspace server, memory cell is alternatively flash memory, hard disk.Survey
Examination unit 101 can be connected with memory cell by wired or wireless mode, such as, by modes such as data wire, wifi, bluetooths
It is attached, memory cell is transmitted and be stored in the test data of test cell 101.
The display of the present embodiment includes display screen, keyboard and mouse with interactive unit 105, and control unit 102 is a computer
Main frame.Show with interactive unit 105 by keyboard and mouse input instruction, control unit 102 can be deposited according to instruction from data
Extract in the database of storage unit 103 in nominative testing project, it is intended that the test data of all chips of wafer, and control to show
Shown with interactive unit 105.It is understood that display and interactive unit 105 can also be touch screens, control unit
102 can also have other to select, a such as server.
As shown in Fig. 2 the present embodiment display pattern is, a two dimensional image corresponding with test wafer is drawn on screen
201, the chip of test wafer is corresponded by coordinate with the chip image 202 in two dimensional image, the institute of test wafer
The test data for having chip includes its coordinate value, it is intended that the specific test data of test event is directly displayed at respective coordinates
On chip image 202 (numeral 1 is specific test data in figure).Other regions of screen, can show this test wafer
Other test information, such as wafer lot number, wafer numbering, test time started, test end time, test event title, test
One or more in project highest and minimum limit value etc..In the present embodiment, the origin of coordinates is X-axis and the intersection point of Y-axis, Ke Yili
Solution is that the origin of coordinates also may be selected other points, and the coordinate of chip changes therewith.
<Embodiment two>
The present embodiment is to show different from the display pattern of interactive unit 105 with the difference of embodiment one.
As shown in figure 3, the present embodiment display pattern is, a two dimensional image corresponding with test wafer is drawn on screen
301, the chip of test wafer is corresponded by coordinate with the chip image 302 in two dimensional image, and chip testing passes through,
Then corresponding chip image 302 is shown in green；Chip testing does not pass through, then corresponding chip image 302 is shown in red.This
Without selecting technical routine, as long as there is a test event not pass through, then control unit 102 judges this chip to survey to display pattern
Try not passing through, and control display to show redness in this chip image 302 with interactive unit.It is understood that other can be used
Different colours represent chip testing and pass through and do not pass through.Of course for specific chip failure type is intuitively given expression to, alternatively
Different failure types specifies concrete color, then expresses on the two dimensional image of re-test wafer.
Further, when a certain chip image 302 using the corresponding two dimensional image 301 of mouse hit testing wafer, screen
The test data of all test events of the corresponding chip of chip image 302 of click can be shown on curtain.Detailed process is to control
Unit processed 102 is numbered with test wafer and is clicked on the coordinate of chip and carries out data extraction as keyword, and all information cases are pre-
Order form and be shown in display and interactive unit.Specifically, test data can include wafer lot number, wafer numbering, click on chip
Coordinate, click on chip test the time started, click on chip test the end time, the yield analysis of test wafer, test
Project name, test event parameter value, the highest of test event and minimum limit value etc..It is understood that click on chip showing
Information can carry out classification according to chip coordinate and test event and show, display can become apparent from；When display and interactive unit
105 when being touch screen, click directly on chip image 302 and mouse click on play the role of it is same.
<Embodiment three>
The present embodiment is that the display is that control is single with the display pattern of interactive unit 105 with the difference of embodiment two
The two dimensional image of multiple similar test wafers is overlapped process by unit 102, and the same coordinate chip of all test wafers is surveyed
Examination does not pass through, then this coordinate chip shows designated color.This kind of display pattern can quickly analyze the common fail map of wafer
Shape, to determine the failure cause of test wafer.When clicking on chip image by mouse, multiple similar test wafers can be also shown
With the test information of all test events of chip corresponding with chip image is clicked on.
The wafer test system provided using the present invention, the instruction that control unit is received according to display with interactive unit, from
The test data of the test wafer specified is extracted in data storage cell, and controls to show with interactive unit according to specified display mould
Formula shows the concrete test data of the test wafer specified by a two dimensional image, and the test data of wafer can intuitively show
In display and interactive unit, the tedious steps searched from magnanimity test data are eliminated, improve data analysis efficiency.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (13)
1. a kind of wafer test system, it is characterised in that including test cell, control unit, data storage cell and show with
Interactive unit；The test cell is used to test wafer, and test data is stored in into the data storage cell；Institute
Control unit is stated according to the instruction shown with interactive unit reception, the survey of the test wafer specified is extracted from data storage cell
Data are tried, and control display that the test wafer specified is shown by a two dimensional image according to specified display pattern with interactive unit
Concrete test data.
2. wafer test system as claimed in claim 1, it is characterised in that the concrete test data is nominative testing project
Concrete test value.
3. wafer test system as claimed in claim 2, it is characterised in that the display is with the display pattern of interactive unit：
On two dimensional image corresponding with specified test wafer, the specified survey of the test wafer specified is shown on each chip image
The concrete test value of examination project.
4. wafer test system as claimed in claim 2, it is characterised in that the display is with the display pattern of interactive unit：
On two dimensional image corresponding with specified test wafer, designated color is shown on each chip image to represent the survey that this is specified
The corresponding chip testing of examination wafer passes through or test does not pass through, when putting the fixed chip image of fingertip, the display with interact list
Unit can show the information of all test events of the corresponding chip of the chip image specified.
5. wafer test system as claimed in claim 2, it is characterised in that the display pattern of the display and interactive unit is such as
Under：The two dimensional image of multiple similar test wafers is overlapped process by described control unit, all similar test wafers it is same
One coordinate chip is tested and not passed through, then this coordinate chip shows designated color.
6. the wafer test system as described in any one in Claims 1 to 5, it is characterised in that also including a data processing
Unit, the data processing unit is used to carry out test data form collator, and the test data after arrangement is stored in into number
According to memory cell.
7. such as claim 6 wafer test system, it is characterised in that the test data after the data processing unit arrangement, bag
Containing following information：Test event type, the lot number of test wafer, wafer numbering, test time started, test end time, survey
The concrete test value of examination project highest and minimum limit value, the coordinate of concrete chip and nominative testing project.
8. the wafer test system as described in any one in Claims 1 to 5, it is characterised in that the test cell is crystalline substance
The fair Acceptance Tests board of circle.
9. the wafer test system as described in any one in Claims 1 to 5, it is characterised in that the test cell is core
Piece probe test board.
10. the wafer test system as described in any one in Claims 1 to 5, it is characterised in that the display with interact it is single
Unit includes display, mouse and keyboard.
11. wafer test systems as described in any one in Claims 1 to 5, it is characterised in that the display with interact it is single
Unit includes a touch-screen.
12. wafer test systems as described in any one in Claims 1 to 5, it is characterised in that the data storage cell
For server.
13. wafer test systems as described in any one in Claims 1 to 5, it is characterised in that the data storage cell
Including operational memory cell and redundant memory cell, the operational memory cell is described standby for the exchange of normal data storage
Part memory cell is backed up in realtime the data of operational memory cell.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611264465.3A CN106597261A (en) | 2016-12-30 | 2016-12-30 | Wafer test system |
| PCT/CN2017/114373 WO2018121184A1 (en) | 2016-12-30 | 2017-12-04 | Wafer test system |
| GB1819585.9A GB2567968A (en) | 2016-12-30 | 2017-12-04 | Wafer test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611264465.3A CN106597261A (en) | 2016-12-30 | 2016-12-30 | Wafer test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106597261A true CN106597261A (en) | 2017-04-26 |
Family
ID=58581651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611264465.3A Pending CN106597261A (en) | 2016-12-30 | 2016-12-30 | Wafer test system |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN106597261A (en) |
| GB (1) | GB2567968A (en) |
| WO (1) | WO2018121184A1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018121184A1 (en) * | 2016-12-30 | 2018-07-05 | 上海华岭集成电路技术股份有限公司 | Wafer test system |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
| CN110146798A (en) * | 2019-03-29 | 2019-08-20 | 福建省福联集成电路有限公司 | The automatic analysis method and system of a kind of pair of failure core particles |
| CN110579702A (en) * | 2019-09-20 | 2019-12-17 | 紫光宏茂微电子(上海)有限公司 | Display method and device for chip test, storage medium and terminal |
| CN110879931A (en) * | 2018-09-05 | 2020-03-13 | 长鑫存储技术有限公司 | Visual memory chip repair analysis program inspection method and device |
| CN110967609A (en) * | 2018-09-29 | 2020-04-07 | 合肥晶合集成电路有限公司 | Monitoring system and monitoring method |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
| CN112612755A (en) * | 2020-12-03 | 2021-04-06 | 海光信息技术股份有限公司 | Chip test information display method and device, electronic equipment and storage medium |
| CN112989141A (en) * | 2021-03-15 | 2021-06-18 | 上海华力微电子有限公司 | Method and system for inquiring interrupted wafer batch LOT |
| CN114429113A (en) * | 2022-01-12 | 2022-05-03 | 上海华虹宏力半导体制造有限公司 | Method for automatically distinguishing and classifying MPW product test data |
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| GB2567968A (en) * | 2016-12-30 | 2019-05-01 | Sino Ic Tech Co Ltd | Wafer test system |
| WO2018121184A1 (en) * | 2016-12-30 | 2018-07-05 | 上海华岭集成电路技术股份有限公司 | Wafer test system |
| CN108400100A (en) * | 2018-02-27 | 2018-08-14 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test parameters setting method |
| CN110879931A (en) * | 2018-09-05 | 2020-03-13 | 长鑫存储技术有限公司 | Visual memory chip repair analysis program inspection method and device |
| CN110879931B (en) * | 2018-09-05 | 2022-04-05 | 长鑫存储技术有限公司 | Visual memory chip repair analysis program inspection method and device |
| CN110967609A (en) * | 2018-09-29 | 2020-04-07 | 合肥晶合集成电路有限公司 | Monitoring system and monitoring method |
| CN110967609B (en) * | 2018-09-29 | 2022-02-08 | 合肥晶合集成电路股份有限公司 | Monitoring system and monitoring method |
| CN110146798B (en) * | 2019-03-29 | 2021-04-09 | 福建省福联集成电路有限公司 | Automatic analysis method and system for failure core particles |
| CN110146798A (en) * | 2019-03-29 | 2019-08-20 | 福建省福联集成电路有限公司 | The automatic analysis method and system of a kind of pair of failure core particles |
| CN110579702A (en) * | 2019-09-20 | 2019-12-17 | 紫光宏茂微电子(上海)有限公司 | Display method and device for chip test, storage medium and terminal |
| CN111983412B (en) * | 2020-07-21 | 2021-12-31 | 深圳米飞泰克科技有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
| CN111983412A (en) * | 2020-07-21 | 2020-11-24 | 深圳安博电子有限公司 | Monitoring system, monitoring method, monitoring terminal and storage medium |
| CN112612755A (en) * | 2020-12-03 | 2021-04-06 | 海光信息技术股份有限公司 | Chip test information display method and device, electronic equipment and storage medium |
| CN112989141A (en) * | 2021-03-15 | 2021-06-18 | 上海华力微电子有限公司 | Method and system for inquiring interrupted wafer batch LOT |
| CN112989141B (en) * | 2021-03-15 | 2024-05-28 | 上海华力微电子有限公司 | Method and system for inquiring and interrupting LOT of wafer batch |
| CN114429113A (en) * | 2022-01-12 | 2022-05-03 | 上海华虹宏力半导体制造有限公司 | Method for automatically distinguishing and classifying MPW product test data |
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| Publication number | Publication date |
|---|---|
| WO2018121184A1 (en) | 2018-07-05 |
| GB2567968A (en) | 2019-05-01 |
| GB201819585D0 (en) | 2019-01-16 |
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Application publication date: 20170426 |