GB2567968A - Wafer test system - Google Patents

Wafer test system Download PDF

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Publication number
GB2567968A
GB2567968A GB1819585.9A GB201819585A GB2567968A GB 2567968 A GB2567968 A GB 2567968A GB 201819585 A GB201819585 A GB 201819585A GB 2567968 A GB2567968 A GB 2567968A
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GB
United Kingdom
Prior art keywords
test
wafer
display
data
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB1819585.9A
Other versions
GB201819585D0 (en
Inventor
Lou Bin
Zhang Zhiyong
Qi Jianhua
Wang Jin
Ling Jianbo
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Sino IC Technology Co Ltd
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Sino IC Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sino IC Technology Co Ltd filed Critical Sino IC Technology Co Ltd
Publication of GB201819585D0 publication Critical patent/GB201819585D0/en
Publication of GB2567968A publication Critical patent/GB2567968A/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates

Abstract

A wafer test system, comprising: a test unit (101), a control unit (102), a data storage unit (103), and a display and interaction unit (105). The test unit is used for testing wafers and storing test data in the data storage unit (103); the control unit (102) extracts test data of a specified test wafer from the data storage unit (103) according to an instruction received by the display and interaction unit (105), and controls the display and interaction unit (105) to display specific test data of the specified test wafer by means of a one-dimensional or two-dimensional image (201, 301) in a specified display mode. The wafer test system resolves that problem of being unable to obtain specific test information of a test wafer conveniently by a conventional wafer test system.

Description

WAFER TEST SYSTEM
TECHNICAL FIELD
The present invention relates to the technical field of integrated circuits, and in particular, to a wafer test system.
BACKGROUND
The main objective of a wafer test is to test electrical functions of chips in a wafer to screen defective chips, classify unqualified products according to the types of electric defects, and provide those to the wafer manufacturer for data analysis and process improvement.
At present, in integrated circuit wafer industrialization tests, one way is to represent different failure types of corresponding chips by colors, for example, green represents complete success, red represents a contact failure, and yellow represents a function failure, and finally illustrate those colors on a two-dimensional image of the wafer. The other way is to directly use green to represent that the test of the corresponding chips has passed and red to represent that the test of the corresponding chips has not passed, and finally illustrate the colors on a two-dimensional image of the wafer.
The above methods both have a problem that, it is only reflected from the two-dimensional image of the wafer whether the test of the chips has passed, and at most also reflecting the failure type. However, the specific information, e.g., which test is not passed, what the test value is, and how much the difference from the design standard is, cannot be obtained intuitively. To obtain the specific information, a search from a large number of test records is required, resulting in great inconvenience.
SUMMARY OF THE INVENTION
To solve the problem that a conventional wafer test system cannot conveniently obtain specific test information of wafer tests, the present invention provides a wafer test system.
The present invention provides a wafer test system, including a test unit, a control unit, a data storage unit, and a display and interaction unit. The test unit is configured to test wafers and store test data in the data storage unit; the control unit is configured to extract the test data of a designated test wafer from the data storage unit according to an instruction received by the display and interaction unit, and control the display and interaction unit to display, according to a designated display mode, specific test data of the designated test wafer by means of a two-dimensional image.
Optionally, the specific test data is a specific test value of a designated test item.
Optionally, the display mode of the display and interaction unit includes: displaying the specific test value of the designated test item of the designated test wafer on each chip image in the two-dimensional image corresponding to the designated test wafer.
Optionally, the display mode of the display and interaction unit includes: displaying a designated color on each chip image in the two-dimensional image corresponding to the designated test wafer in order to represent pass or failure of a test of a corresponding chip of the designated test wafer, and when the display and interaction unit detects a touch of a designated chip image, displaying information of all test items of the chip corresponding to the designated chip image.
Optionally, the display mode of the display and interaction unit includes: superimposing, by the control unit, the two-dimensional images of multiple test wafers of a same type, and displaying a chip of a certain coordinate with a designated color if the chip of the certain coordinate in each of the multiple test wafers of the same type has failed the test.
Optionally, the wafer test system may further include a data processing unit, configured to perform format arrangement on the test data and store the arranged test data in the data storage unit.
Optionally, the test data arranged by the data processing unit includes the following information: types of test items, batch number of the test wafers, wafer numbers, test start time, test end time, highest and lowest limit values of the test items, coordinates of individual chips, and specific test values of a designated test item.
Optionally, the test unit is a wafer acceptance test equipment.
Optionally, the test unit is a chip probe test equipment.
Optionally, the display and interaction unit includes a display, a mouse, and a keyboard.
Optionally, the display and interaction unit includes a touch screen.
Optionally, the data storage unit is a server.
Optionally, the data storage unit includes a working storage unit and a backup storage unit; the working storage unit is configured for normal data storage and exchange, and the backup storage unit backs up the data of the working storage unit in real time.
By using the wafer test system according to the present invention, the control unit extracts the test data of the designated test wafer from the data storage unit according to the instruction received by the display and interaction unit, and controls the display and interaction unit to display the specific test data of the designated test wafer by means of a two-dimensional image in a designated display mode, and therefore, the test data of the wafer can be intuitively displayed on the display and interaction unit, the tedious step of search from massive test data is eliminated, and data analysis efficiency is improved.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic diagram of a wafer test system according to embodiment of the present invention;
FIG. 2 is a schematic diagram showing a wafer image with a wafer test system according to embodiment 1 of the present invention;
FIG. 3 is a schematic diagram showing a wafer image with a wafer test system according to embodiment 2 of the present invention;
LIST OF REFERENCE NUMERALS:
101- Test unit
102- Control unit
103- Data storage unit
104- Data processing unit
105- Display and interaction unit
201, 301-Two-dimensional image corresponding to a test wafer
202, 302-Chip image
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The wafer test system proposed by present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and the claims. It should be noted that the accompanying drawings are all presented in a very simplified form and not precisely drawn to scale, with the only purpose of facilitating conveniently and clearly describing the embodiments of the present invention.
<Embodiment 1>
The present invention provides a wafer test system, as shown in FIG. 1, including a test unit 101, a control unit 102, a data storage unit 103, and a display and interaction unit 105. The test unit 101 is configured to test wafers and store test data in the data storage unit 103. The control unit 102 extracts the test data of a designated test wafer from the data storage unit 103 according to an instruction received by the display and interaction unit 105, and controls the display and interaction unit 105 to display the specific test data of the designated test wafer by means of a two-dimensional image in a designated display mode.
The wafer test system of the embodiment further includes a data processing unit 104. The data processing unit 104 performs format arrangement on the test data in the data storage unit 103 and stores the arranged test data in the data storage unit 103. Specifically, the arranged test data includes the following information: the types of the test items, the batch number of the test wafers, wafer numbers, test start time, test end time, the highest and lowest limit values of the test items, the coordinates of specific chips, and the specific test value of the designated test item. It can be understood that the arranged data may cover the unarranged data; and the arranged data may also be stored in a non-storage area of the data storage unit 103. The data processing unit 104 of the embodiment is a server. It can be understood that the processing unit may also be a single chip microcomputer.
The test unit 101 of the embodiment is a wafer acceptance test equipment. It can be understood that the test unit 101 may also be a chip probe test equipment. The data storage unit 103 is a server, and may specifically include a working server and a backup server. The working server is configured for normal data storage and exchange, and the backup server backs up the data in the working server in real time. It can be understood that the storage unit may also include the working server only, and the storage unit may also be a flash memory, a hard disk or the like. The test unit 101 may be connected with the storage unit in a wired or wireless manner, for example, by means of a data cable, wifi, Bluetooth or the like. The test data of the test unit 101 is transmitted and stored in the storage unit.
The display and interaction unit 105 of the embodiment includes a display screen, a keyboard, and a mouse. The control unit 102 is a computer host. The display and interaction unit 105 inputs an instruction by means of the keyboard and the mouse. The control unit 102 can extract the test data of all the chips of the designated wafer in the designated test items from a database of the data storage unit 103 according to the instruction, and control the display and interaction unit 105 to display the data. It can be understood that the display and interaction unit 105 may also be a touch screen, and the control unit 102 may also have other options, such as a server.
As shown in FIG. 2, the display mode of the embodiment is that: a two-dimensional image 201 corresponding to the test wafer is drawn on the screen. The chips of the test wafer are in one-to-one correspondence with chip images 202 in the two-dimensional image via coordinates. The test data of all the chips of the test wafer includes the coordinates of the chips. The specific test data of the designated test items is directly displayed on the chip image 202 at corresponding coordinates (the number 1 in the figure refers to the specific test data). Other parts of the screen may display other test information of the test wafer, such as one or more of the batch number of the wafers, wafer numbers, test start time, test end time, the names of the test items, and the highest and lowest limited values of the test items, etc. In the embodiment, the origin of coordinates is an intersection of X and Y axes. It can be understood that the origin of coordinates may also select other points, as long as the coordinates of the chip can be changed accordingly.
<Embodiment 2>
The embodiment differs from embodiment 1 in that the display mode of the display and interaction unit 105 is different.
As shown in FIG. 3, the display mode of the embodiment is that: a two-dimensional image 301 corresponding to the test wafer is drawn on the screen. The chips of the test wafer are in one-to-one correspondence with chip images 302 in the two-dimensional image via coordinates. If the tests of the chips are passed, the corresponding chip images 302 are displayed in green; and if the tests of the chips are not passed, the corresponding chip images 302 are displayed in red. This display mode does not need to select a designated item. As long as the test of one test item is not passed, the control unit 102 determines that the test of the chip is not passed, and controls the display and interaction unit to display red at the chip image 302. It can be understood that other different colors may be used to represent that the tests of the chips are passed or not passed. Certainly, in order to intuitively express specific chip failure types, specific colors can also be designated for different failure types and then expressed on the two-dimensional image of the test wafer.
Furthermore, when a certain chip image 302 in the two-dimensional image 301 corresponding to the test wafer is clicked with the mouse, the test data of all the test items of the chip corresponding to the clicked chip image 302 is displayed on the screen. The specific process is that: the control unit 102 performs data extraction by using test wafer numbers and the coordinates of a clicked chip as keywords, and displays all the information on the display and interaction unit 105 in a predetermined format. Specifically, the test data may include the batch number of the wafers, wafer numbers, the coordinates of the clicked chip, the test start time of the clicked chip, the test end time of the clicked chip, yield analysis of the test wafers, the names of the test items, parameter values of the test items, and the highest and lowest limit values of the test items, etc. It can be understood that the information displayed by the clicked chip can be displayed in a classified manner according to the coordinates of the chip and the test items, so that the display is clearer. When the display and interaction unit 105 is a touch screen, directly clicking the chip image 302 has the same effect as clicking the image with the mouse.
<Embodiment 3>
The embodiment differs from embodiment 2 in that the display mode of the display and interaction unit 105 is that: the control unit 102 superimposes the two-dimensional images of multiple test wafers of the same type, and if none of the tests of chips at the same coordinates of all the test wafers is passed, the chips at the coordinates display a designated color. This display mode enables quick analysis of a common failure pattern of the wafer, so as to determine the cause of the failure of the test wafer. When the chip image is clicked with the mouse, the test information of all the test items of the chip in the multiple test wafers of the same type corresponding to the clicked chip image can also be displayed.
By using the wafer test system according to the present invention, the control unit extracts the test data of the designated test wafer from the data storage unit according to the instruction received by the display and interaction unit, and controls the display and interaction unit to display specific test data of the designated test wafer by means of a two-dimensional image in a designated display mode, and therefore, the test data of the wafer can be intuitively displayed on the display and interaction unit, the complicated step of search from massive test data is eliminated, and data analysis efficiency is improved.
The foregoing description describes only preferred embodiments of the present invention, but does not limit the scope of the present invention in any sense. All changes and modifications made by persons of ordinary kill in the art according to the foregoing disclosure fall within the scope of protection of the claims.

Claims (13)

1. A wafer test system, comprising a test unit, a control unit, a data storage unit, and a display and interaction unit, wherein the test unit is configured to test wafers and store test data in the data storage unit; the control unit is configured to extract the test data of a designated test wafer from the data storage unit according to an instruction received by the display and interaction unit, and control the display and interaction unit to display, according to a designated display mode, specific test data of the designated test wafer by means of a two-dimensional image.
2. The wafer test system according to claim 1, wherein the specific test data is a specific test value of a designated test item.
3. The wafer test system according to claim 2, wherein the display mode of the display and interaction unit comprises; displaying the specific test value of the designated test item of the designated test wafer on each chip image in the two-dimensional image corresponding to the designated test wafer.
4. The wafer test system according to claim 2, wherein the display mode of the display and interaction unit comprises; displaying a designated color on each chip image in the two-dimensional image corresponding to the designated test wafer in order to represent pass or failure of a test of a corresponding chip of the designated test wafer, and when the display and interaction unit detects a touch of a designated chip image, displaying information of all test items of the chip corresponding to the designated chip image.
5. The wafer test system according to claim 2, wherein the display mode of the display and interaction unit comprises; superimposing, by the control unit, the two-dimensional images of multiple test wafers of a same type, and displaying a chip of a certain coordinate with a designated color if the chip of the certain coordinate in each of the multiple test wafers of the same type has failed the test.
6. The wafer test system according to any one of claims 1-5, further comprising a data processing unit, configured to perform format arrangement on the test data and store the arranged test data in the data storage unit.
7. The wafer test system according to 6, wherein the test data arranged by the data processing unit comprises: types of test items, batch number of the test wafers, wafer numbers, test start time, test end time, highest and lowest limit values of the test items, coordinates of individual chips, and specific test values of a designated test item.
8. The wafer test system according to any one of claims 1-5, wherein the test unit is a wafer acceptance test equipment.
9. The wafer test system according to any one of claims 1-5, wherein the test unit is a chip probe test equipment.
10. The wafer test system according to any one of claims 1-5, wherein the display and interaction unit comprises a display, a mouse, and a keyboard.
11. The wafer test system according to any one of claims
1-5, wherein the display and interaction unit comprises a touch screen.
12. The wafer test system according to any one of claims
1-5, wherein the data storage unit is a server.
13. The wafer test system according to any one of claims
1-5, wherein the data storage unit comprises a working storage unit and a backup storage unit; the working storage unit is configured for normal data storage and exchange, and the backup storage unit is configured to back up data of the working storage unit in real time.
International application No.
INTERNATIONAL SEARCH REPORT
GB1819585.9A 2016-12-30 2017-12-04 Wafer test system Withdrawn GB2567968A (en)

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CN201611264465.3A CN106597261A (en) 2016-12-30 2016-12-30 Wafer test system
PCT/CN2017/114373 WO2018121184A1 (en) 2016-12-30 2017-12-04 Wafer test system

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GB2567968A true GB2567968A (en) 2019-05-01

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CN108400100A (en) * 2018-02-27 2018-08-14 上海华岭集成电路技术股份有限公司 A kind of wafer test parameters setting method
CN110879931B (en) * 2018-09-05 2022-04-05 长鑫存储技术有限公司 Visual memory chip repair analysis program inspection method and device
CN110967609B (en) * 2018-09-29 2022-02-08 合肥晶合集成电路股份有限公司 Monitoring system and monitoring method
CN110146798B (en) * 2019-03-29 2021-04-09 福建省福联集成电路有限公司 Automatic analysis method and system for failure core particles
CN110579702A (en) * 2019-09-20 2019-12-17 紫光宏茂微电子(上海)有限公司 Display method and device for chip test, storage medium and terminal
CN111983412B (en) * 2020-07-21 2021-12-31 深圳米飞泰克科技有限公司 Monitoring system, monitoring method, monitoring terminal and storage medium
CN112612755B (en) * 2020-12-03 2023-05-26 海光信息技术股份有限公司 Chip test information display method and device, electronic equipment and storage medium
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WO2018121184A1 (en) 2018-07-05
GB201819585D0 (en) 2019-01-16

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