CN106571301B - Method for forming fin field effect transistor - Google Patents
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- CN106571301B CN106571301B CN201510658332.3A CN201510658332A CN106571301B CN 106571301 B CN106571301 B CN 106571301B CN 201510658332 A CN201510658332 A CN 201510658332A CN 106571301 B CN106571301 B CN 106571301B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Abstract
A method for forming a fin field effect transistor comprises the following steps: providing a substrate, wherein a plurality of discrete fin parts are formed on the surface of the substrate; forming initial hard masks on the top surface and the side wall surface of the fin part and the surface of the substrate; patterning the initial hard mask to form a hard mask layer, wherein the hard mask layer exposes the top surface and the side wall surface of part of the fin part; performing an ion implantation process on the exposed fin part by taking the hard mask layer as a mask; and removing the hard mask layer. The invention improves the shadow effect problem in the ion implantation process, thereby improving the electrical performance of the formed fin field effect transistor.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor.
Background
With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET fets has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor and the like.
However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE) is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the electrical performance of the finfet formed by the prior art needs to be improved.
Disclosure of Invention
The invention aims to provide a method for forming a fin field effect transistor, which is used for improving the electrical performance of the fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a substrate, wherein a plurality of discrete fin parts are formed on the surface of the substrate; forming initial hard masks on the top surface and the side wall surface of the fin part and the surface of the substrate; patterning the initial hard mask to form a hard mask layer, wherein the hard mask layer exposes the top surface and the side wall surface of part of the fin part; performing an ion implantation process on the exposed fin part by taking the hard mask layer as a mask; and removing the hard mask layer.
Optionally, the material of the initial hard mask includes silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride.
Optionally, the initial hard mask is formed by an atomic layer deposition process.
Optionally, the initial hard mask is made of silicon nitride, and the process parameters for forming the initial hard mask by using the atomic layer deposition process include: the flow rate of the silicon source gas is 20sccm to 2000sccm, the flow rate of the nitrogen source gas is 10sccm to 1000sccm, the pressure of the reaction chamber is 1 mTorr to 50 Torr, and the temperature of the reaction chamber is 350 ℃ to 600 ℃.
Optionally, the thickness of the initial hard mask is 3 nm to 10 nm; the thickness of the hard mask layer is 3 to 10 nanometers.
Optionally, the process step of forming the hard mask layer includes: forming a graphic layer on the surface of the initial hard mask, wherein the graphic layer exposes part of the surface of the initial hard mask; etching the initial hard mask by taking the graphic layer as a mask to form the hard mask layer; and removing the graph layer.
Optionally, the material of the pattern layer includes photoresist.
Optionally, before forming the initial hard mask, the method further includes: and forming a shielding layer on the top surface and the side wall surface of the fin part.
Optionally, the material of the shielding layer is silicon oxide.
Optionally, the thickness of the shielding layer is 2 nm to 10 nm.
Optionally, the shielding layer is formed by an atomic layer deposition process.
Optionally, after removing the hard mask layer, the shielding layer is removed.
Optionally, the implanted ions of the ion implantation process are N-type ions or P-type ions.
Optionally, the process parameters of the ion implantation process include: the implantation angle is 0-20 deg. and the ion implantation concentration is 1E13atom/cm3～1E18/atom/cm3The implantation energy range is 2Kev to 20 Kev.
Optionally, after removing the hard mask layer, annealing the fin portion.
Optionally, the forming of the fin portion includes: providing an initial substrate; forming a patterned sacrificial layer on the surface of the initial substrate; forming a side wall layer next to the sacrificial layer on the surface of the initial substrate; removing the sacrificial layer; and etching to initially form a fin part by taking the side wall layer as a mask, wherein the etched initial substrate is a substrate.
Optionally, an isolation layer is formed on the surface of the substrate between adjacent fins, the isolation layer is located on the surface of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin.
Optionally, the method further comprises the steps of: and forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the side wall surface and the top surface of the fin part.
Optionally, before the gate structure is formed, the fin portion is cleaned.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the method for forming the fin field effect transistor, initial hard masks are formed on the top surface and the side wall surface of the fin portion and the surface of the substrate, then the initial hard masks are patterned to form a hard mask layer, and the hard mask layer exposes the top surface and the side wall surface of part of the fin portion; and then, taking the hard mask layer as a mask, and carrying out an ion implantation process on the exposed fin part. Compared with the ion implantation process with the photoresist as the mask, the top of the photoresist is at least higher than the top surface of the fin part under the influence of the photoetching process, and the hard mask layer is not limited by the top surface of the fin part, so that the thickness of the hard mask layer required by the ion implantation process with the hard mask layer as the mask is obviously smaller than the thickness of the photoresist, the hard mask layer has weak blocking effect on ion beams in the ion implantation process, the shadow effect problem in the ion implantation process is reduced and even avoided, ions can be fully implanted into the fin part which is not covered by the hard mask layer, and the electrical performance of the fin field effect transistor is improved.
Furthermore, an atomic layer deposition process is adopted to form an initial hard mask, the atomic layer deposition process has high step coverage capacity, so that the initial hard mask can well cover the corner between the fin part and the isolation layer, the coverage of the subsequently formed hard mask layer on the corner between the fin part and the isolation layer is good, and ion implantation of the corner by an ion implantation process is avoided. Moreover, the thickness consistency of the initial hard mask formed by the atomic layer deposition process is good, and the thickness consistency of the corresponding subsequently formed hard mask layer is also higher, so that the protection effect of the hard mask layer on the fin part is strong, and ions are prevented from being implanted into an unexpected area.
Furthermore, before the initial hard mask is formed, a shielding layer covering the top and the side wall surface of the fin portion is formed, the shielding layer can play a role in protecting the fin portion, ion beams of an ion implantation process are prevented from directly bombarding the top and the side wall of the fin portion, implantation damage caused by the ion implantation process is reduced, and the electrical performance of the fin field effect transistor is further improved.
Drawings
Fig. 1 to 2 are schematic cross-sectional views illustrating a finfet formation process according to an embodiment of the present invention;
fig. 3 to 13 are schematic cross-sectional views illustrating a finfet formation process according to another embodiment of the present invention.
Detailed Description
As can be seen from the background art, the electrical performance of the finfet formed in the prior art needs to be improved.
As a result of research on a method for forming a finfet, referring to fig. 1, a substrate 100 is provided, after a plurality of discrete fins 101 are formed on the substrate 100, ion implantation is usually performed on the fins 101, and the fins 101 are doped to improve electrical properties of the finfet, such as threshold voltage (Vt), saturation current (Idsat), and the like.
The process steps for doping the fin 101 include: referring to fig. 2, an initial photoresist layer covering the surface of the substrate 100 and the fin 101 is formed; carrying out exposure treatment on the initial photoresist layer; cleaning the exposed initial photoresist layer by using a developing solution to form a patterned photoresist layer 102, and exposing a part of the fin part 101 and the surface of the substrate 100; and performing ion implantation on the exposed fin portion 101 by using the patterned photoresist layer 102 as a mask.
However, the fin field effect transistor formed by the method has low electrical performance. Further research aiming at the formation method of the fin field effect transistor shows that the fin part is a protruding structure positioned on the surface of the substrate, and the top of the patterned photoresist layer is higher than that of the fin part under the limitation of the photoetching process, so that the thickness of the patterned photoresist layer required by ion implantation of the fin part is thicker, and the patterned photoresist layer has a larger depth-to-width ratio; when the exposed fin portion is ion-implanted using the patterned photoresist layer as a mask, due to the blocking Effect of the patterned photoresist layer, implanted ions are difficult to implant into a partial region of the fin portion, or the ion distribution in the exposed fin portion after ion implantation is uneven, which is a so-called Shadow Effect (Shadow Effect), and the Shadow Effect may cause the electrical performance of the fin field Effect transistor to be low. In particular, when the ion proceeding direction of the ion implantation process is not perpendicular to the top surface of the patterned photoresist layer, i.e., the implantation angle of the ion implantation process is non-zero, the shadow effect of the ion implantation process is more significant.
In order to solve the problems, the invention provides a method for forming a fin field effect transistor, which comprises the steps of providing a substrate, wherein a plurality of discrete fin parts are formed on the surface of the substrate; forming initial hard masks on the top surface and the side wall surface of the fin part and the surface of the substrate; patterning the initial hard mask to form a hard mask layer, wherein the hard mask layer exposes the top surface and the side wall surface of part of the fin part; performing an ion implantation process on the exposed fin part by taking the hard mask layer as a mask; and removing the hard mask layer. The invention improves or avoids the shadow effect in the ion implantation process, so that the ions in the ion implantation process can be fully implanted into the fin part which is not covered by the hard mask layer, and the electrical property of the fin field effect transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 13 are schematic structural diagrams illustrating a finfet formation process according to another embodiment of the present invention.
Referring to fig. 3, a substrate 200 and a number of discrete fins 201 on a surface of the substrate 200 are provided.
The substrate 200 may be a silicon substrate or a silicon-on-insulator substrate, and the substrate 200 may also be a germanium substrate, a silicon-germanium substrate, a gallium arsenide substrate, or a silicon-on-insulator substrate.
The material of the fin 201 includes silicon, germanium, silicon carbide, or gallium arsenide. In this embodiment, the material of the fin 201 is the same as that of the substrate 200.
In one embodiment, the process steps for forming the substrate 200 and the fin 201 include: providing an initial substrate; forming a graphical hard mask layer on the surface of the initial substrate; and etching the initial substrate by taking the patterned hard mask layer as a mask, taking the etched initial substrate as a substrate 200, and forming a plurality of discrete fin parts 201 on the surface of the substrate 200.
The forming process of the graphical hard mask layer comprises the following steps: a Self-aligned Double patterning (SADP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (Self-aligned Double patterning) process. The double patterning process includes a LELE (Litho-Etch-Litho-Etch) process or a LLE (Litho-Litho-Etch) process.
In this embodiment, the process steps for forming the substrate 200 and the fin portion 201 include: providing an initial substrate; forming a plurality of discrete sacrificial layers on the surface of the initial substrate; forming a side wall film covering the surface of the initial substrate and the surface of the sacrificial layer; etching back the side wall film, and etching to remove the side wall film on the top surface of the sacrificial layer and part of the initial substrate surface to form a side wall layer close to the side wall of the sacrificial layer; removing the sacrificial layer; etching the initial substrate by taking the side wall layer as a mask to form a plurality of discrete fin parts 201, wherein the etched initial substrate is taken as a substrate 200; and removing the side wall layer.
With continued reference to fig. 3, an isolation layer 202 is formed on the surface of the substrate 200 between the adjacent fins 201, and the top surface of the isolation layer 202 is lower than the top surface of the fins 201.
The isolation layer 202 is used for serving as an isolation structure of the fin field effect transistor in the following, isolating the fin portions 201 of adjacent regions, and preventing unnecessary electrical connection between the adjacent fin portions 201; the isolation layer 202 is made of silicon oxide or silicon oxynitride.
As an example, the process steps for forming the isolation layer 202 include: forming an isolation film on the surface of the substrate 200 and the surface of the fin 201, wherein the top surface of the isolation film is higher than the top surface of the fin 201; the isolation layer is etched back to form an isolation layer 202, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.
In this embodiment, the isolation film is formed by using a Flowable Chemical Vapor Deposition (FCVD) process, so that the filling effect of the formed isolation layer 202 at the corner between the substrate 200 and the fin 201 is good.
Referring to fig. 4, a shielding layer 203 is formed covering the top surface and sidewall surfaces of the fin 201.
In this embodiment, the shielding layer 203 is also located on the surface of the isolation layer 202.
The role of the shielding layer 203 includes: the fin 201 is protected, the fin 201 is prevented from being damaged in the subsequent hard mask layer forming process, the characteristic dimension of the fin 201 is kept unchanged, and therefore the electrical performance of the formed fin field effect transistor is improved. Moreover, when an ion implantation process is subsequently performed on a part of the fin portion 201, the shielding layer 203 can also function as an ion implantation buffer layer, so that implantation damage to the fin portion 201 caused by the ion implantation process is avoided. Meanwhile, the subsequent process step of removing the photoresist material by using an ashing process or a wet photoresist removal process is included, and the shielding layer 203 can prevent the fin 201 from being exposed in an environment of the ashing process and the wet photoresist removal process, so that the fin 201 is prevented from being damaged.
Since the shielding layer 203 is removed later, the process for removing the shielding layer 203 is required to have no adverse effect on the fin 201, and therefore the material of the shielding layer 203 should be a material that is easy to remove, and the process for removing the shielding layer 203 has a large etching selectivity ratio for the shielding layer 203 and the fin 201. For this reason, in this embodiment, the material of the shielding layer 203 is silicon oxide.
In order to avoid or reduce the consumption of the material of the fin 201 caused by the process for forming the shielding layer 203, the shielding layer 203 is formed by a deposition process, and the gas containing the material atoms of the fin 201 is provided as a main source gas by the deposition process, so that the amount of the oxygen source gas for oxidizing the material of the fin 201 can be greatly reduced, and the consumption of the material of the fin 201 can be reduced.
In this embodiment, the fin 201 is made of silicon, and the main source gas provided by the deposition process is a silicon source gas including SiH4Or SiH2Cl2。
The shielding layer 203 is formed by adopting a chemical vapor deposition process or an atomic layer deposition process, and the thickness of the shielding layer 203 is 2 to 10 nanometers.
Referring to fig. 5, an initial hard mask 204 is formed on the top and sidewall surfaces of the fin 201 and the surface of the substrate 200.
In this embodiment, since the shielding layer 203 is formed on the top surface and the sidewall surface of the fin 201 and the substrate 200, the initial hard mask 204 is located on the surface of the shielding layer 203.
And patterning the initial hard mask 204 to form hard mask layers on the top surfaces and the side wall surfaces of the partial fins 201, wherein the hard mask layers are masks for performing an ion implantation process on the residual fins 201. Therefore, the initial hard mask layer 204 has a higher material hardness, and the hard mask layer formed subsequently has a higher material hardness, so that the formed hard mask layer can block ions from being implanted into an undesired region in the subsequent ion implantation process.
The thickness of the initial hard mask 204 should not be too thick, otherwise, the problem of the shadow effect in the ion implantation process performed subsequently still remains, that is, the hard mask layer formed by patterning the initial hard mask 204 still has a stronger effect of blocking the ion implantation to an undesired region under the condition that the thickness of the initial hard mask 204 is relatively thin.
For this purpose, the initial hard mask 204 is made of silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride.
The thickness of the initial hard mask layer 204 is 3 nm to 10 nm, so that the subsequently formed hard mask layer has a sufficient function of blocking ion implantation, and the shadow effect problem in the ion implantation process is avoided.
The initial hard mask 204 is formed by an atomic layer deposition process, which has the following advantages: because the ald process has a high step-coverage capability, the initial hard mask 204 can well cover the corner between the fin 201 and the isolation layer 202, so that the subsequently formed hard mask layer has good coverage on the corner between the fin 201 and the isolation layer 202, and ion implantation of the corner by an ion implantation process is avoided. Moreover, the initial hard mask layer 204 formed by the atomic layer deposition process has good thickness consistency, and the subsequently formed hard mask layer also has higher thickness consistency, so that the subsequently formed hard mask layer has strong protection effect on the fin portion 201.
In this embodiment, the initial hard mask 204 is made of silicon nitride, and the process parameters for forming the initial hard mask 204 by using the atomic layer deposition process include: the flow rate of the silicon source gas is 20sccm to 2000sccm, the flow rate of the nitrogen source gas is 10sccm to 1000sccm, the pressure of the reaction chamber is 1 mTorr to 50 Torr, and the temperature of the reaction chamber is 350 ℃ to 600 ℃.
Referring to fig. 6, a pattern layer 205 is formed to cover a portion of the top and sidewalls of the fin 201.
In this embodiment, since the shielding layer 203 is formed on the top and the sidewall surface of the fin 201, the pattern layer 205 is located on the surface of the shielding layer 203 on the top and the sidewall surface of a portion of the fin 201.
The pattern layer 205 is a mask for subsequent patterning of the initial hard mask 204, and defines the fin 201 to be subjected to the ion implantation process.
In this embodiment, the material of the pattern layer 205 is a photoresist, and the process for forming the pattern layer 205 includes: forming a photoresist film covering the surface of the shielding layer 203; carrying out exposure treatment on the photoresist film; and developing the exposed photoresist film, and removing the photoresist film on the top and the side wall of part of the fin portion 201 to form the pattern layer 205.
Referring to fig. 7, the initial hard mask 204 (see fig. 6) is patterned to form a hard mask layer 214, and the hard mask layer 214 exposes a portion of the top surface and sidewall surfaces of the fin 201.
In this embodiment, since the shielding layer 203 is formed on the top and the sidewall of the fin 201, the hard mask layer 214 exposes a portion of the shielding layer 203 on the top and the sidewall of the fin 201.
Specifically, the pattern layer 205 is used as a mask, and the exposed initial hard mask 204 is removed by etching through a dry etching process to form the hard mask layer 214.
In the dry etching process, the shielding layer 203 located on the top of the fin portion 201 and the surface of the sidewall plays a role in protecting the fin portion 201, so that the fin portion 201 is prevented from being exposed in the dry etching process environment, the fin portion 201 is prevented from being damaged by etching, and the fin portion 201 keeps good lattice quality.
As can be seen from the foregoing analysis of the initial hard mask 204, the hard mask layer 214 has a good thickness uniformity, the hard mask layer 214 has a relatively high hardness, and the hard mask layer 214 has a good coverage property on the corner between the fin 201 and the isolation layer 202.
The hard mask layer 214 is made of silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride. In this embodiment, the hard mask layer 214 is made of silicon nitride.
The thickness of the hard mask layer 214 is 3 to 10 nanometers, so that the hard mask layer 214 provides a sufficient protection effect for the fin portion 201, and ion implantation in a subsequent ion implantation process to an undesired region is avoided; moreover, the thickness of the hard mask layer 214 is relatively thin, and in the subsequent ion implantation process, the concentration of ions implanted into the fin portion 201 which is not covered by the hard mask layer 214 is uniformly distributed, so that the shadow effect problem is avoided.
Referring to fig. 8, the graphic layer 205 (refer to fig. 7) is removed.
In this embodiment, the pattern layer 205 is made of a photoresist, and the pattern layer 205 is removed by a wet stripping or ashing process.
In the process of removing the pattern layer 205, the shielding layer 203 protects the fin portion 201 not covered by the hard mask layer 214, and the fin portion 201 not covered by the hard mask layer 214 is prevented from being exposed in the process of removing the pattern layer 205, so that unnecessary damage to the fin portion 201 due to the process of removing the pattern layer 205 is avoided.
Referring to fig. 9, an ion implantation process is performed on the exposed fin 201 using the hard mask layer 214 as a mask.
In this embodiment, the top and the sidewall of the fin 201 not covered by the hard mask layer 214 are subjected to an ion implantation process, so that the threshold voltage or the saturation current of the fin field effect transistor can be improved, and the formed fin field effect transistor can meet the process requirements.
In one embodiment, the ions implanted by the ion implantation process are N-type ions, and the N-type ions include phosphorus, arsenic or antimony. In another embodiment, the implanted ions of the ion implantation process are P-type ions, and the P-type ions include boron, gallium or indium.
In order to avoid the tailing phenomenon of the channeling effect on the ion implantation distribution during the ion implantation process, an off-axis implantation method is generally adopted, that is, an included angle is formed between the ion beam advancing direction of the ion implantation process and the surface of the substrate 200, and the included angle is generally an acute angle and is called an implantation angle (tilt).
In this embodiment, the implantation angle of the ion implantation process is 0 to 20 degrees.
Because the thickness of the hard mask layer 214 for performing the ion implantation process in this embodiment is relatively thin, the hard mask layer 214 has a weak blocking effect on the ion beam in the ion implantation process, and even if the ion implantation process has a non-zero implantation angle, the hard mask layer 214 does not block the progress of the ion beam, so that the shadow effect problem does not occur in the fin 201, and ions can be sufficiently implanted into the fin 201 not covered by the hard mask layer 214, thereby improving the electrical performance of the fin field effect transistor.
In this embodiment, the process parameters of the ion implantation process include: the implantation angle is 0-20 deg. and the ion implantation concentration is 1E13atom/cm3～1E18/atom/cm3The implantation energy range is 2Kev to 20 Kev.
In the ion implantation process, the shielding layer 203 is formed on the top surface and the sidewall surface of the fin 201, and the shielding layer 203 prevents ion beams in the ion implantation process from directly bombarding the surface of the fin 201, so that implantation damage to the fin 201 is reduced.
Referring to fig. 10, the hard mask layer 214 (refer to fig. 9) is removed.
The hard mask layer 214 is removed by a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process.
In this embodiment, the hard mask layer 214 is made of silicon nitride, the hard mask layer 214 is removed by a wet etching process, etching liquid of the wet etching process is phosphoric acid solution, the mass percentage of phosphoric acid in the solution is 65% to 85%, and the solution temperature is 120 ℃ to 200 ℃.
After removing the hard mask layer 214, the method further comprises the steps of: the fin portion 201 is annealed, ions injected into the fin portion 201 are activated, the concentration of the injected ions in the fin portion 201 is redistributed, and the annealing can also repair lattice damage in the fin portion 201.
Referring to fig. 11, the shielding layer 203 (refer to fig. 10) is removed.
And removing the shielding layer 203 by adopting a dry etching process, a wet etching process or a process combining the dry etching process and the wet etching process.
As an example, the etching liquid of the wet etching process is a hydrofluoric acid solution (DHF: Dilute HF), wherein the volume ratio of water to hydrofluoric acid in hydrofluoric acid is 50:1 to 1000: 1.
As another embodiment, the shielding layer 203 is removed by etching using a dry etching process, the dry etching process is performed by a SiCoNi etching system, and etching gas of the dry etching process includes NH3And HF, in some embodiments, the etching gas includes NH3And HF, and may also include inert gases, e.g. N2He or Ar.
As another embodiment, the shielding layer 203 is removed by a combined process of dry etching and wet etching, for example, the shielding layer 203 is removed by etching through a dry etching process followed by a wet etching process.
The wet etching process or the dry etching process has a high etching rate on silicon oxide, and hardly etches silicon, so that the process of removing the shielding layer 203 does not have adverse effects on the fin portion 201, and the fin portion 201 still maintains a good characteristic dimension after the shielding layer 203 is removed.
After removing the shielding layer 203, the method further comprises the steps of: and cleaning the fin parts 201 and the isolation layer 202, and removing impurities on the surfaces of the fin parts 201 and the isolation layer 202 to provide a good interface foundation for the subsequent formation of a gate structure.
The method also comprises the following steps: and forming a gate structure crossing the fin 201, wherein the gate structure covers part of the top and the side wall surface of the fin 201. Specifically, the forming process of the gate structure comprises the following steps:
referring to fig. 12, a gate dielectric film 208 is formed to cover the top surface and sidewall surface of the fin 201.
The gate dielectric film 208 provides a process foundation for the subsequent formation of a gate dielectric layer in the gate structure.
The gate dielectric film 208 is made of silicon oxide, silicon nitride or a high-k gate dielectric material, the high-k gate dielectric material refers to a material having a relative dielectric constant greater than that of silicon oxide, and the high-k gate dielectric material includes LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3、Al2O3Or Si3N4。
In this embodiment, the gate dielectric film 208 is made of Al2O3The gate dielectric film 208 is formed by a physical vapor deposition process.
Referring to fig. 13, a gate electrode film 209 is formed on the surface of the gate dielectric film 208.
The gate electrode film 209 provides a process basis for the subsequent formation of a gate electrode layer.
The gate electrode film 209 is made of polysilicon, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, or WSi.
In this embodiment, the gate electrode film 209 is made of Al.
The subsequent process steps further comprise: patterning the gate electrode film 209 to form a gate electrode layer; patterning the gate dielectric film 208 to form a gate dielectric layer, wherein a stacked structure of the gate dielectric layer and a gate electrode layer positioned on the top surface of the gate dielectric layer forms a gate structure of the fin field effect transistor, the gate structure crosses over the fin portion 201, and the gate structure also covers part of the top surface and the side wall surface of the fin portion 201; and doping the fin parts 201 on the two sides of the gate structure, forming a source region in the fin part 201 on one side of the gate structure, and forming a drain region in the fin part 201 on the other side of the gate structure.
In the embodiment, when the fin portion 201 is subjected to the ion implantation process, the problem of the shadow effect in the ion implantation process is avoided, so that the electrical performance of the fin field effect transistor is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method for forming a fin field effect transistor (FinFET) is characterized by comprising the following steps:
providing a substrate, wherein a plurality of discrete fin parts are formed on the surface of the substrate;
forming initial hard masks on the top surface and the side wall surface of the fin part and the surface of the substrate;
patterning the initial hard mask to form a hard mask layer, wherein the hard mask layer exposes the top surface and the side wall surface of part of the fin part;
performing an ion implantation process on the exposed fin part by taking the hard mask layer as a mask;
removing the hard mask layer;
the thickness of the initial hard mask is 3-10 nanometers, and the material of the initial hard mask comprises silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxycarbonitride, so that the formed hard mask layer can block ions from being implanted into an undesired region and avoid a shadow effect in a subsequent ion implantation process;
before forming the initial hard mask, the method further comprises the following steps: forming shielding layers on the top surface and the side wall surface of the fin part;
the process for forming the hard mask layer comprises the following steps: forming a graphic layer on the surface of the initial hard mask, wherein the graphic layer exposes part of the surface of the initial hard mask; etching the initial hard mask by taking the graphic layer as a mask to form the hard mask layer; removing the graph layer; the material of the pattern layer comprises photoresist.
2. The method of claim 1, wherein the initial hardmask is formed using an atomic layer deposition process.
3. The method of claim 2, wherein the initial hard mask is formed of silicon nitride, and the atomic layer deposition process is performed to form the initial hard mask according to process parameters including: the flow rate of the silicon source gas is 20sccm to 2000sccm, the flow rate of the nitrogen source gas is 10sccm to 1000sccm, the pressure of the reaction chamber is 1 mTorr to 50 Torr, and the temperature of the reaction chamber is 350 ℃ to 600 ℃.
4. The method of claim 1, wherein the hard mask layer has a thickness of 3 nm to 10 nm.
5. The method of claim 4, wherein the material of the shield layer is silicon oxide.
6. The method of claim 4, wherein the shield layer has a thickness of 2 nm to 10 nm.
7. The method of claim 4, wherein the shield layer is formed using an atomic layer deposition process.
8. The method of claim 4, wherein the mask layer is removed after the hard mask layer is removed.
9. The method of claim 1, wherein the ions implanted by the ion implantation process are N-type ions or P-type ions.
10. The method of claim 1, wherein the process parameters of the ion implantation process comprise: the implantation angle is 0-20 deg. and the ion implantation concentration is 1E13atom/cm3～1E18/atom/cm3The implantation energy range is 2Kev to 20 Kev.
11. The method of claim 1, wherein the fin is annealed after the hard mask layer is removed.
12. The method of claim 1, wherein the fin formation step comprises: providing an initial substrate; forming a patterned sacrificial layer on the surface of the initial substrate; forming a side wall layer next to the sacrificial layer on the surface of the initial substrate; removing the sacrificial layer; and etching to initially form a fin part by taking the side wall layer as a mask, wherein the etched initial substrate is a substrate.
13. The method of claim 1, wherein an isolation layer is formed on a surface of the substrate between adjacent fins, the isolation layer being on a sidewall surface of the fin, and a top surface of the isolation layer being lower than a top surface of the fin.
14. The method of forming a fin field effect transistor of claim 1, further comprising: and forming a grid electrode structure crossing the fin part, wherein the grid electrode structure covers part of the side wall surface and the top surface of the fin part.
15. The method of claim 14, wherein the fin is cleaned prior to forming the gate structure.
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