CN106549037A - A kind of high voltage bearing technotron - Google Patents
A kind of high voltage bearing technotron Download PDFInfo
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- CN106549037A CN106549037A CN201611051954.0A CN201611051954A CN106549037A CN 106549037 A CN106549037 A CN 106549037A CN 201611051954 A CN201611051954 A CN 201611051954A CN 106549037 A CN106549037 A CN 106549037A
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- technotron
- doped
- high voltage
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- 238000002955 isolation Methods 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 230000006835 compression Effects 0.000 claims description 9
- 238000007906 compression Methods 0.000 claims description 9
- 210000002615 epidermis Anatomy 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to technical field of semiconductors, more particularly to a kind of technotron, including P type substrate；N-type lightly doped district；P-type doped region；P-type heavily doped region；The heavily doped drain region of N-type and source region；The first dielectric isolation layer that silicon face between the drain region and the p-type doped region is formed；The second dielectric isolation layer that silicon face between the source region and the p-type doped region is formed, first dielectric isolation layer is formed in on fluted silicon face, the first dielectric isolation layer upper part covers doped polysilicon layer, and the polysilicon layer is drawn by through hole and is electrically connected with grid.The pressure performance of technotron of the present invention effectively improves.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of technotron.
Technical background
With the quick evolution of semiconductor technologies so that for example computer and its periphery digital product etc. also increasingly update.
Can the application integrated circuit semiconductor technology of computer and its periphery digital product be fast-developing, be to provide high-quality digital product
Key factor.
Technotron (JFET) is one of modal semiconductor devices, including N-channel technotron and P ditches
Road technotron, in practical application, that conventional is N-channel JFET.Technotron is little due to device size, has
Better than the advantage of MOSFET, the direction for contributing to semiconductor devices further towards high density, miniaturization is developed.
Traditional technotron is pressure by PN junction, improves pressure mode and relies primarily on the concentration for reducing knot,
But under current processing procedure, pressure degree is still limited, it is impossible to make high voltage bearing technotron, and reduce the concentration of knot
Easily cause the problems such as device current is too little, stability is poor.
The content of the invention
It is an object of the invention to provide a kind of high voltage bearing technotron.
For achieving the above object, the present invention is employed the following technical solutions：
A kind of high voltage bearing technotron, including：P type substrate, the P type substrate is used as backgate；Serve as a contrast in the p-type
N-type lightly doped district is formed in the upper epidermis at bottom；The p-type doped region formed in the upper epidermis of the N-type lightly doped district, the P
Type doped region is used as positive grid；The p-type heavily doped region formed in the upper epidermis of the p-type doped region；In the N-type lightly doped district
Two ends formed the heavily doped drain region of N-type and source region, positive grid are near the source region；The drain region and the p-type doped region it
Between silicon face formed the first dielectric isolation layer；Second of silicon face formation between the source region and the p-type doped region
Dielectric isolation layer, the silicon face between the drain region and the p-type doped region form n groove, and n is positive integer, and described first
Dielectric isolation layer is formed in on fluted silicon face, and the first dielectric isolation layer upper part covers DOPOS doped polycrystalline silicon
Layer, technotron cover insulating medium layer with the surface of the P type substrate opposite side, and grid is by through hole by p-type weight
Doped region is drawn, and source electrode and drain electrode are drawn by source region and drain region by through hole respectively, and the polysilicon layer is drawn by through hole
Go out and be electrically connected with grid.
Preferably, groove number n is more than 2.
Preferably, the distance between described groove is being sequentially reduced from p-type doped region side to drain region side.
Preferably, p-type lightly doped district is formed under the first dielectric isolation layer between the polysilicon layer and drain region.
Preferably, the polysilicon layer is also formed in the p-type doped region between the first dielectric isolation layer and p-type heavily doped region
On.
Preferably, the polysilicon layer is contacted with p-type heavily doped region.
Preferably, the corresponding N-type lightly doped district in the drain region side forms low-doped resistance to compression layer with P type substrate intersection.
Preferably, the low-doped resistance to compression layer is n-type doping of the doping content less than N-type lightly doped district.
Preferably, the low-doped resistance to compression layer is p-type doping of the doping content less than P type substrate.
Preferably, first dielectric isolation layer and second layer material is dielectrically separated from for silica.
Relative to prior art, the invention has the advantages that：
First dielectric isolation layer of technotron of the present invention upper part covers polysilicon layer, and polysilicon layer passes through through hole
Draw and be electrically connected with grid, when being worked due to technotron, grid opposite drain and source potential are low, polysilicon layer
It is electrically connected with the grid of electronegative potential, exhausts the N-type lightly doped district under the first dielectric isolation layer, increases the crushing resistance of FET
Can, while increasing the carrier concentration of N-type lightly doped district, lower conducting resistance；
First dielectric isolation layer is formed in on fluted silicon face, on the one hand increasing N-type lightly doped district quilt
The area for exhausting, on the other hand, when groove number is multiple, drain electrode applies high voltage, when the depletion region between groove is connected,
The compressive property of FET can further be increased.
Description of the drawings
FET cross-sectional views of the Fig. 1 for first embodiment of the invention；
FET cross-sectional views of the Fig. 2 for second embodiment of the invention；
Fig. 3 is third embodiment of the invention technotron cross-sectional view；
Fig. 4 is fourth embodiment of the invention technotron cross-sectional view.
Specific embodiment
For a better understanding of the present invention, below in conjunction with the accompanying drawings and embodiment the invention will be described further, implement
Example is only limitted to explain the present invention, not to any restriction of present invention composition.First embodiment
As shown in figure 1, the high voltage bearing technotron of the present embodiment, including：P type substrate 10, the P type substrate 10
As backgate；N-type lightly doped district 20 is formed in the upper epidermis of the P type substrate 10；In the upper table of the N-type lightly doped district 20
The p-type doped region 30 formed in layer, the p-type doped region 30 is used as positive grid；Formed in the upper epidermis of the p-type doped region 30
P-type heavily doped region 31；The heavily doped drain region 21 of N-type formed at the two ends of the N-type lightly doped district 20 and source region 22, positive grid
Near the source region 22；The first dielectric isolation layer 41 that silicon face between the drain region 21 and the p-type doped region 30 is formed；
The second dielectric isolation layer 42 that silicon face between the source region 22 and the p-type doped region 30 is formed, the described in the present embodiment
One dielectric isolation layer 41 and 42 material of the second dielectric isolation layer are silica, the drain region 21 and the p-type doped region 30 it
Between silicon face formed n groove 50, n is positive integer, and first dielectric isolation layer 41 is formed in the silicon table with groove 50
On face, 41 upper part of the first dielectric isolation layer covers doped polysilicon layer 60, ties with 10 opposite side of the P type substrate
Type FET surface covers insulating medium layer 70, and postivie grid drawn by p-type heavily doped region 31 by through hole, source electrode and drain electrode
Drawn by source region 22 and drain region 21 by through hole respectively, the polysilicon layer 60 is drawn by through hole and electrically connected with postivie grid
Connect.
When being worked due to technotron, grid opposite drain and source potential are low, polysilicon layer 60 and electronegative potential
Grid be electrically connected with, exhaust the N-type lightly doped district 20 the first dielectric isolation layer 41 under, the compressive property of increase FET,
Electronics in N-type lightly doped district 20 is dislodged near the depletion layer under the first dielectric isolation layer 41 simultaneously, increases N-type lightly doped district
Carrier concentration in 20, lowers conducting resistance.
50 number of the present embodiment groove is 3, and drain electrode applies high voltage, when the depletion region between groove is connected, can enter one
Step increases the compressive property of FET；Near drain region, 21 side current potential is high, and the distance between groove 50 described in the present embodiment is from P
30 side of type doped region is sequentially reduced to 21 side of drain region, can be effectively increased the compressive property of FET.
Second embodiment
As shown in Fig. 2 the present embodiment is on the basis of first embodiment, between the polysilicon layer 60 and drain region 21
P-type lightly doped district 80 is formed under one dielectric isolation layer 41, p-type doped region 80 forms pn-junction with N-type lightly doped district 20, and drain region 21 adds
During high voltage, further increase the compressive property of FET.
3rd embodiment
As shown in figure 3, relative to first embodiment, the polysilicon layer 60 is also formed in the first dielectric isolation layer 41 and P
On p-type doped region 30 between type heavily doped region 31, Electric Field Distribution on p-type doped region 30 can be caused more uniform, improve field
The compressive property of effect pipe, described in the present embodiment, polysilicon layer 60 is contacted with p-type heavily doped region 30, preferably uniform p-type doping
Electric Field Distribution in area 30.
Fourth embodiment
As shown in figure 4, relative to first embodiment, the corresponding N-type lightly doped district in 21 side of drain region described in the present embodiment 20
Low-doped resistance to compression layer 90 is formed with 10 intersection of P type substrate, the low-doped resistance to compression layer 90 can be gently mixed less than N-type for doping content
The n-type doping in miscellaneous area 20, alternatively doping content are adulterated less than the p-type of P type substrate 10, by forming low-doped resistance to compression layer 90,
The pn-junction for strengthening 21 side N-type lightly doped district 20 of drain region with P type substrate 10 exhausts, and then the compressive property of increase FET.
Claims (10)
1. a kind of high voltage bearing technotron, including：P type substrate, the P type substrate is used as backgate；In the P type substrate
Upper epidermis in formed N-type lightly doped district；The p-type doped region formed in the upper epidermis of the N-type lightly doped district, the p-type
Doped region is used as positive grid；The p-type heavily doped region formed in the upper epidermis of the p-type doped region；In the N-type lightly doped district
The heavily doped drain region of N-type and source region that two ends are formed, positive grid are near the source region；Between the drain region and the p-type doped region
Silicon face formed the first dielectric isolation layer；Second of silicon face formation between the source region and the p-type doped region is exhausted
Edge separation layer, it is characterised in that：Silicon face between the drain region and the p-type doped region forms n groove, and n is positive integer,
First dielectric isolation layer is formed in on fluted silicon face, and the first dielectric isolation layer upper part covers doping
Polysilicon layer, the surface of technotron and the P type substrate opposite side cover insulating medium layer, grid by through hole by
P-type heavily doped region is drawn, and source electrode and drain electrode are drawn by source region and drain region by through hole respectively, and the polysilicon layer is by logical
Draw and be electrically connected with grid in hole.
2. high voltage bearing technotron according to claim 1, it is characterised in that：Groove number n is more than 2.
3. high voltage bearing technotron according to claim 1, it is characterised in that：The distance between described groove exists
It is sequentially reduced from p-type doped region side to drain region side.
4. high voltage bearing technotron according to claim 1, it is characterised in that：The polysilicon layer and drain region it
Between the first dielectric isolation layer under formed p-type lightly doped district.
5. high voltage bearing technotron according to claim 1, it is characterised in that：The polysilicon layer is also formed in
On p-type doped region between first dielectric isolation layer and p-type heavily doped region.
6. high voltage bearing technotron according to claim 5, it is characterised in that：The polysilicon layer and p-type weight
Doped region is contacted.
7. high voltage bearing technotron according to claim 1, it is characterised in that：The corresponding N in the drain region side
Type lightly doped district forms low-doped resistance to compression layer with P type substrate intersection.
8. high voltage bearing technotron according to claim 7, it is characterised in that：The low-doped resistance to compression layer is to mix
N-type doping of the miscellaneous concentration less than N-type lightly doped district.
9. high voltage bearing technotron according to claim 7, it is characterised in that：The low-doped resistance to compression layer is to mix
Miscellaneous concentration is adulterated less than the p-type of P type substrate.
10. high voltage bearing technotron according to claim 1, it is characterised in that：First dielectric isolation layer
And second be dielectrically separated from layer material for silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611051954.0A CN106549037A (en) | 2016-11-25 | 2016-11-25 | A kind of high voltage bearing technotron |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611051954.0A CN106549037A (en) | 2016-11-25 | 2016-11-25 | A kind of high voltage bearing technotron |
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| CN106549037A true CN106549037A (en) | 2017-03-29 |
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| CN201611051954.0A Pending CN106549037A (en) | 2016-11-25 | 2016-11-25 | A kind of high voltage bearing technotron |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103700711A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Junction type field effect tube structure |
| US20140264564A1 (en) * | 2013-03-13 | 2014-09-18 | Cree, Inc. | Field Effect Transistor Devices with Buried Well Protection Regions |
| CN104518034A (en) * | 2014-06-17 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | JFET (junction field-effect transistor) device and manufacturing method thereof |
| CN104518008A (en) * | 2013-09-29 | 2015-04-15 | 北大方正集团有限公司 | Junction field effect transistor |
| CN104716179A (en) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | LDMOS device with deep hole and manufacturing method thereof |
-
2016
- 2016-11-25 CN CN201611051954.0A patent/CN106549037A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140264564A1 (en) * | 2013-03-13 | 2014-09-18 | Cree, Inc. | Field Effect Transistor Devices with Buried Well Protection Regions |
| CN104518008A (en) * | 2013-09-29 | 2015-04-15 | 北大方正集团有限公司 | Junction field effect transistor |
| CN104716179A (en) * | 2013-12-11 | 2015-06-17 | 上海华虹宏力半导体制造有限公司 | LDMOS device with deep hole and manufacturing method thereof |
| CN103700711A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Junction type field effect tube structure |
| CN104518034A (en) * | 2014-06-17 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | JFET (junction field-effect transistor) device and manufacturing method thereof |
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Application publication date: 20170329 |