CN106549016A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device, comprising: a first epitaxial layer on the substrate; a second epitaxial layer on the first epitaxial layer; first and second source/drain regions in the first and second epitaxial layers; a first channel formed by the second epitaxial layer between the first source/drain regions; a first gate stack on the first channel, the first source/drain region, the first channel and the first gate stack forming a first device; the second channel is formed by the first epitaxial layer between the second source drain regions; and a second gate stack on the second channel, the second source/drain region, the second channel and the second gate stack forming a second device. According to the semiconductor and the manufacturing method thereof, one of two epitaxial layers superposed on the substrate is removed through selective etching, channels of different materials are formed aiming at the NMOS and the PMOS, and the carrier mobility and the CMOS driving capability are simply and effectively improved.
Description
Technical field
The present invention relates to a kind of semiconductor device and its manufacture method, more particularly to a kind of
Cmos device and its manufacture method.
Background technology
Improve device performance and be always CMOS technology focus, existing ripe scheme includes should
Become engineering, height -- k metal gate techniques and nonplanar multi-gate device structure etc..
Traditional strain gauge technique is mainly by being epitaxially formed source and drain and then introducing desired stress in raceway groove
(nMOSFET introduces tensile stress, and pMOSFET introduces compressive stress).Because N-shaped and p-type
MOSFET element needs to introduce different stress, therefore extension can only be carried out step by step, be brought in technique
Complexity.By simple process needed for the raceway groove of two kinds of devices is synchronously introduced or further increased
The strain of type will be very valuable.
On the other hand, in existing planar CMOS device electron mobility apparently higher than hole migration
Rate, realizes pMOSFET and nMOSFET generally by the size of adjustment pMOSFET
The matching of energy, and then the comprehensive performance for improving circuit, but can so increase the area of pMOSFET,
Improve cost.Germanium silicon (SixGe1--x) alloy material hole mobility apparently higher than silicon materials, because
This is by SixGe1--xIntroduce pMOSFET very meaningful.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose a kind of energy letter
The semiconductor device and its manufacture method of CMOS driving forces are effectively improved singly.
For this purpose, the invention provides a kind of semiconductor device, including：First epitaxial layer, in lining
On bottom；Second epitaxial layer, on the first epitaxial layer；First source/drain region and the second source/drain region,
In the first epitaxial layer and the second epitaxial layer；First raceway groove, by second between the first source/drain region
Epitaxial layer is constituted；First grid is stacked, on the first raceway groove, the first source/drain region, the first raceway groove
The first device is constituted with first grid stacking；Second raceway groove, by first between the second source-drain area
Epitaxial layer is constituted；Second grid is stacked, on the second raceway groove, the second source/drain region, the second raceway groove
The second device is constituted with second grid stacking.
Wherein, the first epitaxial layer and/or the second epitaxial layer are height of the carrier mobility more than substrate
Mobility material；Optionally, high transport materials include selected from SiGe, SiC, SiGeC, Ge,
The high mobility material of GeSn, GaN, GaP, GaAs, InN, InP, InAs, InSb
Or their component proportion material, such as SiGeSn, InGaAs.
Wherein, the thickness of the first raceway groove is more than or equal to 5nm.
Wherein, the first source/drain region and/or the second source/drain region include that source drain extension area, source and drain are heavily doped
Miscellaneous area and optionally swoon shape source-drain area, optionally lifting source-drain area.
Wherein, there is isolation area between the first device and the second device；Optionally, first and/
Or second have stressor layers and/or metal silicide on source/drain region.
Wherein, first and/or second grid stacking include the gate dielectric layer and metal of high-g value
The grid conductive layer of material；Optionally, included between gate dielectric layer and the first and/or second raceway groove
Cross layer.
Present invention also offers a kind of method, semi-conductor device manufacturing method, including：On substrate successively
Form the first epitaxial layer and the second epitaxial layer；On the second epitaxial layer, formed in the first region
The first dummy grid stacking and in the second area the second dummy grid stacking；In the second epitaxial layer
In the first epitaxial layer, the first source/drain region in the first region and in the second area is formed
Second source/drain region；Interlayer dielectric layer is formed on substrate；The first and second dummy grids stacking is removed,
First grid opening and second grid opening are left in interlayer dielectric layer；Selective removal second
At least a portion of the second epitaxial layer in gate openings；Respectively in the first and second gate openings
The first and second gate stacks of middle formation, second grid stacking the first epitaxial layer of directly contact, the
The first epitaxial layer under two gate stacks is used as the second raceway groove, first grid stacking directly contact the
Two epitaxial layers, the second epitaxial layer under first grid stacking are used as the first raceway groove.
Wherein, adjust unstripped gas proportioning carrier mobility is formed in identical chamber higher than lining
First epitaxial layer and the second epitaxial layer at bottom.
Wherein, after at least a portion of the second epitaxial layer of selective removal, the second epitaxial layer is residual
The thickness for staying is 1～2nm.
Wherein, further include after forming the first source/drain region and the second source/drain region, extension life
Long lifting source-drain area, is optionally formed stressor layers.
According to the CMOS channel material process integration schemes of the application, wherein nMOSFET is still
Raceway groove is made using silicon, pMOSFET does raceway groove using SiGe.Under nMOSFET silicon raceway grooves
Side, so can be in Si raceway grooves due to there is SiGe (Ge atomic radiuses are more than Si atomic radiuses)
Twin shaft tensile strain is introduced, increases the mobility of electronics.In pMOSFET device channel regions, lead to
The Si layers (doing sacrifice layer) crossed above thinning SiGe, can finally obtain the P with SiGe as raceway groove
Type device, so as to improve the performance of pMOSFET.Wherein on the one hand Si sacrifice layers can reduce
Damage of the integrated technique to SiGe raceway grooves, on the other hand oxidation form SiOx and are used as height -- k media with
Transition zone between SiGe.Due to SixGe1--xLayer is to grow on a si substrate, therefore can be
SixGe1--xMiddle increase compressive strain, so also can further improve hole mobility.The CMOS
Raceway groove Integrated Solution is completely compatible with existing CMOS technology, and is easier to realize.
Quasiconductor according to the present invention and preparation method thereof, is removed on substrate by selective etch
One of two stacked epitaxial layers, form the raceway groove of different materials for NMOS and PMOS,
Carrier mobility and CMOS driving forces are improve simply and effectively.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 to Fig. 5 is the generalized section of each step of CMOS manufacture methods according to the present invention.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment
The feature and its technique effect of case, discloses the device and its system for effectively improving CMOS driving forces
Make method.It is pointed out that similar reference represents similar structure, in the application
Term " first " used, " second ", " on ", that D score etc. can be used for modification is each
Plant device architecture or manufacturing process.These modifications do not imply that modified device unless stated otherwise
The space of structure or manufacturing process, order or hierarchical relationship.
With reference to Fig. 1, at least two epitaxial layer 1E and 1C of stacking are formed on substrate 1S.
Substrate 1S is provided, is needed and reasonable selection according to device application, it may include monocrystalline silicon (Si),
Monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon (SiGe), or change
Compound semi-conducting material, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP),
Indium antimonide (InSb), and carbon-based semiconductors such as Graphene, SiC etc..For with CMOS
The consideration of process compatible, substrate 1S are preferably body Si.By MOCVD, PECVD,
The depositing operations such as UHVCVD, HDPCVD, MBE, ALD, successively in substrate 1S shapes
Into the first epitaxial layer 1E and the second epitaxial layer 1C.Preferably, the material of epitaxial layer 1E and 1C
Matter at least includes high mobility material, such as the Si materials of substrate 1S, two
At least one (also can both of which) of epitaxial layer include selected from SiGe, SiC, SiGeC, Ge,
The high mobility material of GeSn, GaN, GaP, GaAs, InN, InP, InAs, InSb
Material or combinations thereof material such as component proportion material, such as SiGeSn, InGaAs.
In a preferred embodiment of the invention, epitaxial layer 1E materials are SixGe1--x, epitaxial layer
1C materials are Si, such as by controlling unstripped gas (Si in MOCVD techniques2H2Cl2With
GeH4) component proportion and adjust the change of Ge contents in SiGe (epitaxial layer 1C be visual
Make the SiGe that Ge contents are 0), so as to continuous two epitaxial layers are realized in a process cavity
Deposition.Wherein, the thickness of epitaxial layer 1E is 10～100nm preferably 30～70nm,
Ge contents determine that according to the film quality of epitaxial layer 1E for example, 20～50% simultaneously preferably
30%.Preferably, the thickness of epitaxial layer 1C is more than or equal to 10nm, such as 10～50nm,
To ensure to also have certain thickness Si residuals after a series of oxidations, etching technics.
In other preferred embodiments of the present invention, when substrate 1S is Si, epitaxial layer 1E
Material for SiC epitaxial layer 1C materials be Si, or layer 1E materials for SiGe layer 1C
Material is Ge, or layer 1E for SiGe, layer 1C is SiGeC, or layer 1E is SiC
And layer 1C is SiGeC, the purpose or standard that material is selected is caused to adjust each component proportion
Between each layer of 1S, 1E, 1C, lattice paprmeter is close to reduce boundary defect and ensure as far as possible
Boost device characteristic as far as possible.When substrate 1S is the other materials such as Ge, GaN, GaAs,
The standard of selection is also identical.In the same manner, the thickness relationship of the layer of these different materials similar to
The above-mentioned situation of Si+SiGe+Si.
With reference to Fig. 2, pseudo- grid stacking is formed on epitaxial layer 1C.
First, the formation isolation area 2 in substrate 1S.For example pass through anisotropic dry etching
Technique is sequentially etched epitaxial layer 1C, epitaxial layer 1E, until formed and exposing and going deep in substrate 1S
Opening (not shown), then in the opening deposit or aoxidize filling form sealing coat 2, material
Matter such as silicon oxide or silicon oxynitride, the isolation area as device, or referred to as shallow trench isolation
(STI).The region that STI 2 is surrounded constitutes active area, and in Fig. 2, left side corresponds to such as NMOS
Multiple first areas, right side corresponding to such as PMOS multiple second areas, but two
Not only isolate by STI 2 between region but there may be multiple insertion elements.It is further excellent
Selection of land, is mask using photoetching offset plate figure (not shown), to first area and second area point
Do not carry out being lightly doped ion implanting, formed different well region (it is not separately shown, such as in NMOS
First area in formed p traps, and in the second area of PMOS formed n traps), so as to increase
The effect being dielectrically separated between strong device.It is further preferred that the isolation oxide of STI 2 is
Negative expansion dielectric material or positive thermal expansion dielectric material, enter one with the stress provided by STI
Step improves the carrier mobility in future channel area.Wherein, negative expansion dielectric material is calcium titanium
Ore deposit type oxide, including Bi0..95La0..05NiO3、BiNiO3、ZrW2O8；Positive thermal expansion medium
Material includes Ag3[Co(CN)6].Preferably, temperature of the isolation oxide of STI 2 using 100K
The absolute value of the degree lower linear coefficient of cubical expansion is more than 10-4/K。
Secondly, by LPCVD, PECVD, thermal oxide, thermal decomposition etc. on whole chip
Technique forms bed course 3A, then forms dummy gate layer 3B by techniques such as CVD, PVD,
Etch layer 3B and 3A form dummy grid stacking.Bed course 3A material such as silicon oxides.Dummy grid
3B the materials such as silicon substrate such as polysilicon, non-crystalline silicon, microcrystal silicon material, or amorphous carbon,
Diamond like carbon amorphous carbon (DLC), amorphous carbon nitrogen, polycrystalline boron nitrogen, amorphous fluorination hydrogenation
The non-silicon-based materials such as carbon, noncrystal carbon fluoride, fluorination tetrahedral carbon.In bed course 3A forming processes
In, if adopting thermal oxidation technology, the thickness of epitaxial layer 1C is needed more than or equal to 5nm,
To guarantee still to have enough epitaxial layer 1C to retain for subsequent treatment after forming oxide.
Then, form source-drain area.Photoresist is formed on second area (such as right side in figure)
(not shown), then 3B/3A and photoetching offset plate figure are stacked as mask with dummy grid, to epitaxial layer
1C and 1E carries out the first ion implanting, in the first region (at least in the second epitaxial layer 1C
In, it is also possible to continue deeper into the first epitaxial layer 1E) form lightly doped drain (LDD) structure
Source drain extension area.Optionally, angle-tilt ion injection is carried out, in source drain extension area and follow-up raceway groove
Area interface forms lightly doped bag-shaped or halo-like zone (halo areas) 1HN for precise controlling
Channel conduction.Subsequently deposit and etch to form isolation side walls in dummy grid stacking 3B/3A sides
3S, its material such as silicon nitride or silicon oxynitride.With isolation side walls as mask, carry out second from
Son injection, in the first region the formation source and drain heavy doping (mainly in the first epitaxial layer 1E)
Area.Source and drain heavily doped region and source drain extension area collectively form source region 1SN and leakage shown in Fig. 2
Area 1DN, epitaxial layer 1CN between source-drain area (and the top section of epitaxial layer 1E, take
Certainly in the control of source-drain area junction depth) will later serve as the conducting channel of nmos device.Then,
The techniques such as photoresist, deposition, injection are deposited with the process selectivity being similar to, in second area
Source region 1SP, drain region 1NP, Halo area 1HP are formed, epitaxial layer 1CP between source-drain area, is left
And 1EP.Optionally, formed source-drain area after, source-drain area surface formed metal silicide with
Reduce source-drain contact resistance.
In addition, although shown in Fig. 2, source-drain area is obtained for ion implanting, but one can also be entered
Step forms homogeneity or the 3rd heterogeneous epitaxial layer (not shown) on the second epitaxial layer 1C simultaneously
Doping in situ increases the stress in raceway groove so as to constitute lifting source-drain area (not shown), further
With reduction source and drain dead resistance.
Optionally, after forming source-drain area and optional silicide contacts, sink on whole chip
Product silicon nitride or DLC materials contact etching stop layer (CESL, not shown) for use as should
Power layer, to further enhance channel region stress.
Then, form interlayer dielectric layer (ILD) 4.For example by silk screen printing, spraying, rotation
The techniques such as painting, CVD deposition form the ILD of low-K material, and wherein low-k materials include but do not limit
In organic low-k materials (such as the organic polymer containing aryl or many yuan of rings), inorganic low k
Material (for example amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG,
BPSG), porous low k material (three oxygen alkane (SSQ) Quito hole low-k materials of such as two silicon,
Porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon,
Porous diamond, porous organic polymer).Cmp planarization chemical industry skill is carried out subsequently, until
Exposure dummy grid 3B.
With reference to Fig. 3, the dummy grid stacking of dummy grid 3B and bed course 3A is removed, in ILD layer 4
In leave first grid opening 4GN and second grid opening 4GP, exposure epitaxial layer 1CN and
1CP.For the different anisotropic etching technics of dummy grid material selection, such as TMAH
Dummy grid 3B of the wet etching for Si materials, HF wet etchings are for silicon oxide material
Bed course 3A, the fluorine-based (C of carbonxHyFz, xyz numerical value is selected so that composition saturation or undersaturated fluorine
For hydrocarbon) one step etch layer 3B of plasma etching and 3A, oxygen plasma dry etching is directed to C
Dummy grid 3B of material etc..
Reference Fig. 4, at least one of the second epitaxial layer 1CP in selective removal second area
Point.Photoresist exposure imaging are coated for example on whole chip, light is left in the first region
Photoresist figure 5, covers ILD 4 and completely fills first grid opening 4GN.Through
Second grid opening 4GP, anisotropically removes for example, by the fluorine-based dry plasma etch of carbon
Second epitaxial layer 1CP ground at least a portion.In an embodiment of the invention, the second extension
Layer 1CP is completely removed, and exposes the first epitaxial layer 1E of lower section.The present invention another
In embodiment, the thickness (such as from 10～50nm) of the second epitaxial layer 1CP is thinned to 1～
On the one hand 2nm, the second epitaxial layer of residual can protect the first epitaxial layer 1EP in second area
Raceway groove is not destroyed by subsequent technique, on the other hand can be used as channel region 1EP with partial oxidation
With follow-up height -- the transition zone between k gate mediums, interfacial state and interface scattering are reduced to device performance
Degeneration.
With reference to Fig. 5, the is formed in first grid opening 4GN and second grid opening 4GP
One gate stack 6AN/6BN and second grid stacking 6AP/6BP.By PECVD,
The techniques such as UHVCVD, HDPCVD, MOCVD, MBE, ALD, in first area
With second area (PMOS area) in the first grid opening 4GN of (NMOS area)
Second grid opening 4GP in formed high-g value the first gate dielectric layer 6AN and second gate
Dielectric layer 6AP.High-g value is included selected from HfO2、HfSiOx、
HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnio material
(wherein, each material is different according to multi-element metal component proportion and chemical valence, and oxygen atom contains for material
Amount x can Reasonable adjustment, can for example be 1～6 and be not limited to integer), or including selected from ZrO2、
La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or including Al2O3,
With the composite bed of its above-mentioned material.Subsequently adopt in first grid opening and second grid opening
The techniques such as MOCVD, MBE, ALD, magnetron sputtering deposit first grid conductive layer 6BN simultaneously,
First grid opening 4GN is filled preferably completely.Grid conductive layer 6BN can then be polysilicon, many
Brilliant germanium silicon or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru,
The metal simple-substances such as Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La,
Or the nitride of the alloy and these metals of these metals, can also mix in grid conductive layer 6BN
It is miscellaneous to have the elements such as C, F, N, O, B, P, As to adjust work function.Grid conductive layer 6BN
Further preferably formed by conventional methods such as PVD, CVD, ALD between gate dielectric layer 6AN
The barrier layer (not shown) of nitride, barrier layer material are MxNy、MxSiyNz、MxAlyNz、
MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.It is more excellent
Selection of land, grid conductive layer 6BN, are gone back not only with lamination layer structure stacked up and down with barrier layer
The injection doping Rotating fields for mixing can be adopted, namely constitutes grid conductive layer 6BN and barrier layer
Material be simultaneously deposited on gate dielectric layer 6AN, therefore grid conducting layer includes above-mentioned stop
The material of layer.After deposited the first grid conductive layer 6BN, photoresist is covered in first area
Or hard mask, perform selective etch technique and remove in the second grid opening of second area the
One grid conducting layer 6BN, subsequently using similar technique in first area and second grid opening
In simultaneously deposit second grid conductive layer 6BP (due to first grid conductive layer 6BN before
Jing completely fills first grid opening, therefore layer 6BP will not enter grid on the first region
Pole opening and be placed only on ILD), afterwards perform cmp planarizationization until exposure ILD.
As shown in figure 5, wherein the first epitaxial layer of second grid dielectric layer 6AP directly contacts 1EP,
Therefore the top of epitaxial layer 1EP is used as the raceway groove of the PMOS of second area.
Finally, the contact hole that ILD 4 forms exposure source-drain area is etched, gold is deposited in the contact hole
The barrier layer of category nitride and the packed layer of metal or alloy complete device to form contact plunger
Interconnection.
The cmos device that obtains is manufactured finally as shown in figure 5, including substrate 1S, in substrate
The first epitaxial layer 1E on 1S, the second epitaxial layer 1C on the first epitaxial layer 1E,
The first source/drain region 1SN/1DN and the second source in one epitaxial layer 1E and the second epitaxial layer 1C
Drain region 1SP/1DP, the second epitaxial layer 1C between the first source/drain region constitute the first raceway groove,
The first epitaxial layer 1E between second source-drain area constitutes the second raceway groove, first grid stacking
6AN/6BN is located on the first raceway groove, and second grid stacking 6AP/6BP is located on the second raceway groove,
First source-drain area, the first raceway groove, first grid stacking constitute the first device (such as NMOS),
Second source-drain area, the second raceway groove and second grid stacking constitutes the second device (such as PMOS).
Although Fig. 1～Fig. 5 shows the NMOS in the left side and PMOS on right side, actual
On can also according to epitaxial layer 1E, 1C material it is different and select the first device of left side be PMOS,
The second device of right side is NMOS, and correspondingly adjusts doping type and work function.
Quasiconductor according to the present invention and preparation method thereof, is removed on substrate by selective etch
One of two stacked epitaxial layers, form the raceway groove of different materials for NMOS and PMOS,
Carrier mobility and CMOS driving forces are improve simply and effectively.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture
And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or
The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to
It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (10)
1. a kind of semiconductor device, including：
First epitaxial layer, on substrate；
Second epitaxial layer, on the first epitaxial layer；
First source/drain region and the second source/drain region, in the first epitaxial layer and the second epitaxial layer；
First raceway groove, is made up of the second epitaxial layer between the first source/drain region；
First grid is stacked, on the first raceway groove, the first source/drain region, the first raceway groove and first
Gate stack constitutes the first device；
Second raceway groove, is made up of the first epitaxial layer between the second source-drain area；
Second grid is stacked, on the second raceway groove, the second source/drain region, the second raceway groove and second gate
Pole stacking constitutes the second device.
2. semiconductor device as claimed in claim 1, wherein, the first epitaxial layer and/or the second epitaxial layer
It is more than the high mobility material of substrate for carrier mobility；Optionally, high transport materials
Including selected from SiGe, SiC, SiGeC, Ge, GeSn, GaN, GaP, GaAs,
The high mobility material or combinations thereof material of InN, InP, InAs, InSb.
3. semiconductor device as claimed in claim 1, wherein, the thickness of the first raceway groove is more than or equal to
5nm。
4. semiconductor device as claimed in claim 1, wherein, the first source/drain region and/or the second source/drain
Area includes source drain extension area, source and drain heavily doped region and the shape source-drain area of optionally swooning, optionally
Ground lifting source-drain area.
5. semiconductor device as claimed in claim 1, wherein, have between the first device and the second device
There is isolation area；Optionally, there is stressor layers and/or gold on the first and/or second source/drain region
Category silicide.
6. semiconductor device as claimed in claim 1, wherein, first and/or second grid stacking include
The grid conductive layer of the gate dielectric layer and metal material of high-g value；Optionally, gate medium
Include transition zone between layer and the first and/or second raceway groove.
7. a kind of method, semi-conductor device manufacturing method, including：
The first epitaxial layer and the second epitaxial layer are sequentially formed on substrate；
On the second epitaxial layer, the first dummy grid stacking in the first region is formed and the
The second dummy grid stacking in two regions；
In the second epitaxial layer and the first epitaxial layer, the first source/drain in the first region is formed
Area and the second source/drain region in the second area；
Interlayer dielectric layer is formed on substrate；
The first and second dummy grids stacking is removed, and first grid is left in interlayer dielectric layer and is opened
Mouth and second grid opening；
At least a portion of the second epitaxial layer in selective removal second grid opening；
Form the first and second gate stacks respectively in the first and second gate openings, second
The first epitaxial layer of gate stack directly contact, the first lower epitaxial layer of second grid stacking is as the
Two raceway grooves, first grid stacking the second epitaxial layer of directly contact, second under first grid stacking
Epitaxial layer is used as the first raceway groove.
8. method, semi-conductor device manufacturing method as claimed in claim 7, wherein, adjust unstripped gas proportioning with
First epitaxial layer and second of the carrier mobility higher than substrate is formed in identical chamber
Epitaxial layer.
9. method, semi-conductor device manufacturing method as claimed in claim 7, wherein, outside selective removal second
After prolonging at least a portion of layer, the thickness of the second epitaxial layer residual is 1～2nm.
10. method, semi-conductor device manufacturing method as claimed in claim 7, wherein, formed the first source/drain region and
Further include after second source/drain region that epitaxial growth lifting source-drain area is optionally formed stress
Layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108584984A (en) * | 2018-04-17 | 2018-09-28 | 南昌航空大学 | A kind of metal organic framework powder and preparation method thereof with big negative expansion coefficient |
| CN113809008A (en) * | 2020-06-12 | 2021-12-17 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN118366929A (en) * | 2024-06-18 | 2024-07-19 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079086A1 (en) * | 2006-08-10 | 2008-04-03 | Hyung-Suk Jung | Semiconductor device and method of manufacturing the same |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
| CN102203924A (en) * | 2008-10-30 | 2011-09-28 | 飞思卡尔半导体公司 | Optimized compressive sige channel pmos transistor with engineered ge profile and optimized silicon cap layer |
| US20120267685A1 (en) * | 2009-09-18 | 2012-10-25 | International Business Machines Corporation | METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe |
-
2015
- 2015-09-21 CN CN201510605350.5A patent/CN106549016B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080079086A1 (en) * | 2006-08-10 | 2008-04-03 | Hyung-Suk Jung | Semiconductor device and method of manufacturing the same |
| CN102203924A (en) * | 2008-10-30 | 2011-09-28 | 飞思卡尔半导体公司 | Optimized compressive sige channel pmos transistor with engineered ge profile and optimized silicon cap layer |
| US20120267685A1 (en) * | 2009-09-18 | 2012-10-25 | International Business Machines Corporation | METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108584984A (en) * | 2018-04-17 | 2018-09-28 | 南昌航空大学 | A kind of metal organic framework powder and preparation method thereof with big negative expansion coefficient |
| CN113809008A (en) * | 2020-06-12 | 2021-12-17 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN118366929A (en) * | 2024-06-18 | 2024-07-19 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor device |
| CN118366929B (en) * | 2024-06-18 | 2024-09-03 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor device |
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