CN106558554A - CMOS manufacture methods - Google Patents
CMOS manufacture methods Download PDFInfo
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- CN106558554A CN106558554A CN201510629279.4A CN201510629279A CN106558554A CN 106558554 A CN106558554 A CN 106558554A CN 201510629279 A CN201510629279 A CN 201510629279A CN 106558554 A CN106558554 A CN 106558554A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of CMOS manufacture methods, including step：Etched substrate forms multiple first fins and multiple second fins for extending in a first direction；Shallow trench isolation is formed between multiple first fins and multiple second fins；Multiple first fins are removed at least in part, leave multiple first openings；The first channel layer of epitaxial growth in the multiple first openings；Multiple second fins are removed at least in part, leave multiple second openings；The second channel layer of epitaxial growth in the multiple second openings；The gate stack for extending in a second direction is formed on the first channel layer and the second channel layer；In the first channel layer and the second channel layer, both sides form source-drain area to gate stack in the first direction.According to the CMOS manufacture methods of the present invention, selectivity returns the mobility channel fin for carving substrate fin and epitaxial growth different materials, improves CMOS carrier mobilities and driving force low-cost high-efficiency.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of to have Gao Qian
The FinFET type CMOS manufacture methods of shifting rate raceway groove.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is
Main device architecture, this structure enhance grid control ability, inhibit electric leakage and short ditch
Channel effect.
For example, the MOSFET of double gate SOI structure and traditional single grid body Si or SOI
MOSFET is compared, and short-channel effect (SCE) and leakage can be suppressed to cause induced barrier to reduce
(DIBL) effect, with lower junction capacity, can realize that raceway groove is lightly doped, can be by setting
The work function for putting metal gates carrys out adjusting threshold voltage, can obtain about 2 times of driving current, reduces
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid
Pole encloses channel region top surface and two sides, and grid control ability is higher.Further, entirely
It is more advantageous around nano wire multi-gate device.
Single gate device is compared, double-gated devices are advantageous；Double grid is compared, tri-gate devices are advantageous；Phase
Than three grid, loopful is advantageous around nano wire multi-gate device；But the manufacture work of nano wire multi-gate device
Skill is typically complex, incompatible with main flow FinFETal technique.
On the other hand, although ring gate device has more preferable grid control function, can more effectively control short ditch
Channel effect, has more advantage during the reduction of sub- 14 nanotechnology, but a key issue is
Due to small conducting channel, more driving currents can not be provided in the equivalent silicon area of plane.
For this purpose, prior art generally in three-dimensional FinFET integrated heterogeneous mobility channel being conducive to more
Device and circuit performance are improved under small size.Conventional method is extension or selective epitaxy on substrate
The high mobility materials such as Ge, SiGe, iii-v, II-VI group compound.A kind of common technique is
After substrate Epitaxial growth high mobility material, etching forms fin structure, then ties in fin
Source-drain area is formed during grid, fin structure are formed on structure and completes device manufacture, this technique is often only
Disposably can deposit on the wafer substrates identical high mobility material namely be grown to it is of overall importance,
It is unfavorable for local device with CMOS hybrid integrateds in circuit.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose a kind of Gao Qian
Shifting rate FET-type CMOS manufacture methods, low-cost high-efficiency are formed selectively different raceway groove materials
The CMOS of material.
For this purpose, the invention provides a kind of CMOS manufacture methods, including step：Etched substrate
Multiple first fins and multiple second fins that formation is extended in a first direction；In multiple first fins
Shallow trench isolation is formed between piece and multiple second fins；Multiple first fins are removed at least in part
Piece, leaves multiple first openings；The first channel layer of epitaxial growth in the multiple first openings；Extremely
Multiple second fins are partially removed, multiple second openings are left；In the multiple second openings
The second channel layer of epitaxial growth；Formed in a second direction on the first channel layer and the second channel layer
The gate stack of extension；In the first channel layer and the second channel layer, gate stack is in the first direction
Both sides form source-drain area.
Wherein, the carrier mobility of the first channel layer and/or the second channel layer is higher than substrate；Appoint
Selection of land, the first channel layer are different from the second channel layer material；Preferably, the first channel layer and/
Or second the material of channel layer be that Ge, SiGe, SiC, SiGeC, III-V are partly led
Any one of body, II-VII compound semiconductors and combinations thereof.
Wherein, further include before epitaxial growth first and/or the second channel layer, multiple
One and/or second opening in epitaxial growth first and/or second buffer layer；Preferably, first and/
Or the lattice paprmeter of second buffer layer is between substrate and the first and/or second channel layer；It is preferred that
Ground, the conduction type of first, second cushion are contrary with source-drain area.
Wherein, the step of removing multiple second fins at least in part further includes that formation is covered
Mould figure covers the first channel layer on multiple first fins, with mask graph as mask selective
Etching removes multiple second fins.
Wherein, further include before forming the gate stack for extending in a second direction, return and carve shallow
Trench isolations, expose the first channel layer and the second channel layer at least in part.
Wherein, the top of shallow trench isolation is equal to or less than the first channel layer and/or the second raceway groove
The bottom of layer.
Wherein, dielectric layer is formed in the first and/or second channel layer bottom part down.
Wherein, source-drain area includes source drain extension area, source and drain heavily doped region, lifting source-drain area extremely
It is few one.
Wherein, gate stack is stacked for dummy grid.Wherein, further wrap after forming source-drain area
Include, form interlayer dielectric layer and cover whole substrate, etching removes dummy grid stacking to be situated between in interlayer
Gate openings are left in matter layer, the gate dielectric layer and gold of hafnium are formed in gate openings
The grid conducting layer of category material.
According to the CMOS manufacture methods of the present invention, selectivity is returned carves substrate fin and epitaxial growth
The mobility channel fin of different materials, improves CMOS carriers low-cost high-efficiency
Mobility and driving force.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 (Figure 1A and Figure 1B) to Figure 11 (Figure 11 A and Figure 11 B) is according to this
The generalized section of the bright each step of stacking nanowire MOS transistor manufacture method,
Wherein certain figure A is that, along the sectional view perpendicular to channel direction, certain figure B is along parallel to raceway groove
The sectional view in direction.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment
The feature and its technique effect of case, improves device drive ability with disclosing low-cost high-efficiency
And the high mobility FET-type CMOS manufacture methods of reliability.It is pointed out that similar
Reference represent similar structure, term " first " use herein, " second ",
" on ", D score etc. can be used to modify various device architectures or manufacturing process.These modifications
Space, order or the layer of modified device architecture or manufacturing process are not implied that unless stated otherwise
Level relation.
Especially, certain figure A is along the section view perpendicular to channel direction (in a second direction) below
Figure, certain figure B are along the sectional view parallel to channel direction (in the first direction).
With reference to Figure 1A and Figure 1B, etched substrate 1 forms multiple fins for extending in a first direction
Piece 1F, wherein first direction are future device channel region bearing of trend.Substrate 1, substrate are provided
1 needs and reasonable selection according to device application, it may include monocrystalline silicon (Si), monocrystal germanium
(Ge), strained silicon (Strained Si), germanium silicon (SiGe), or compound partly leads
Body material, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), antimony
Change indium (InSb), and carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc..Go out
In the consideration compatible with CMOS technology, substrate 1 is preferably body Si.For example in substrate 1
It is upper to form the photoetching offset plate figure (not shown) for extending in a first direction, serve as a contrast for mask etching accordingly
Bottom, formed in substrate 1 multiple distributions parallel in the first direction groove (not shown) and
Between the groove fin bottom 1F constituted by 1 material of remaining substrate, the depth-to-width ratio of groove are excellent
Selection of land is more than 5:1.Wherein in figure ia, left side be shown as the first device (such as PMOS,
Can also be NMOS) therefore including multiple first fin 1FP, right side is shown as forming region
Therefore second device (such as NMOS, it is also possible to corresponding for PMOS) forming region includes
Multiple second fin 1FN, two regions be although shown as it is adjacent, but actually according to
CMOS arrangements need and with physics and can electrically insulate.
Subsequently, PECVD, HDPCVD, RTO are passed through in the groove between fin structure
The filling material such as (rapid thermal oxidation) process deposits is, for example, silicon oxide, silicon oxynitride, carbon oxygen
SiClx, low k's (low-k) etc. is dielectrically separated from dielectric layer, so as to constitute shallow trench isolation (STI)
2.Low-k materials include but is not limited to organic low-k materials (such as containing aryl or many yuan of rings
Organic polymer), inorganic low-k material (for example amorphous carbon nitrogen film, polycrystalline boron nitrogen film,
Fluorine silica glass, BSG, PSG, BPSG), porous low k material (three oxygen alkane of such as two silicon
(SSQ) Quito hole low-k materials, porous silica, porous SiOCH, mix C dioxies
SiClx, mix F porous amorphous carbon, porous diamond, porous organic polymer).Optional,
STI isolation oxides are negative expansion dielectric material, and such as perofskite type oxide such as wraps
Include Bi0.95La0.05NiO3、BiNiO3、ZrW2O8；Or STI isolation oxides are positive heat
Inflating medium material, for example, frame material, such as including Ag3[Co(CN)6], thus STI
Isolation oxide is expanded by the positivity during following process or negativity and is further increased
Channel region stress, further increases carrier mobility.Preferably, cmp planarizationization is straight
To exposing multiple fin 1FP/1FN.
With reference to Fig. 2A and Fig. 2 B, by selective etch, first area is removed at least in part
In the first fin 1FP.For example mask is formed (for example on second area (such as NMOS)
The soft mask of coating photoresist, or the hard mask of deposition of insulative material are not shown) covering
Second fin 1FN of lid protection second area, exposes the first fin 1FP of first area.It is excellent
Choosing adopts anisotropic etch process, to the fin being made up of 1 material of substrate (such as Si)
1FP selective etch, at least eliminates a part of the first fin 1FP, between STI 2
Leave the first opening 2TP.The wet etching for example with KOH, TMAH is etched, or
Using carbon fluorine-based etching gas (fluorohydrocarbon CxHyFz) plasma dry etch or react from
Son etching.As shown in Figure 2 A, etching technics preferably leaves the first fin of part on substrate 1
Piece 1FP is strengthening the mechanical support intensity between subsequent epitaxial fin and substrate, such as the first fin
Piece 1FP residual altitudes are the 1/5～1/10 of original height, for example, leave 5～10nm.Now,
Second fin 1FN is not etched.Fig. 2 B are extended in a first direction for Fig. 2A first areas
Sectional view.
Reference picture 3A and Fig. 3 B, the epitaxial growth first in the first opening 2TP of first area
Channel layer 1CP, and optionally or preferably further included before extension 1CP that extension is given birth to
Long first buffer layer 1BP (namely cushion 1BP can not also be present).For example pass through
The techniques such as PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD,
Epitaxial growth buffer 1BP and channel layer 1CP, wherein channel layer 1CP successively on substrate 1
The fin 1FP that stays more than substrate 1/ of carrier mobility, and the lattice of cushion 1BP
Constant is between channel layer 1CP and substrate 1.In a preferred embodiment of the invention, ditch
Channel layer 1CP material be Ge, SiGe, SiC, SiGeC, Group III-V compound semiconductor,
Any one of II-VII compound semiconductors and combinations thereof, be selected from Ge, SiGe, SiC,
SiGeC、SiGeSn、SiGaN、SiGaP、SiGaAs、InSiN、InSiP、InSiAs、
InSiSb, GaN, InSb, InP, InAs, GaAs, SiInGaAs any one and its
Combination.In an embodiment of the invention, channel layer 1CP is used for PMOS, and its material is
Ge；In another embodiment, channel layer 1CP is used for NMOS, and its material is
Above-mentioned Group III-V compound semiconductor, II-VII compound semiconductors.Cushion 1BP materials
Ge, SiGe, SiC, SiGeC, iii-v can also be also selected from above-mentioned material scope
Any one of compound semiconductor, II-VII compound semiconductors and combinations thereof, and lattice
Constant is between channel layer 1CP and substrate 1.In a preferred embodiment of the invention,
Substrate 1 is Si, and cushion is Si1-xGexOr Si1-yCy, channel layer 1CP be Ge,
Si1-zGez、Si1-m-nGemCn, wherein x, y, z, m, n be all higher than equal to 0 less than etc.
X and/or y is preferably more than less than 1, z more than 0 in 1, m and n sums.Due to selecting
Appropriate lattice paprmeter, cushion 1BP will reduce high mobility material channel layer 1CP with
Lattice mismatch between substrate 1, so as to reduce dislocation, interface defect density, improves ditch
Road layer film growth quality, is beneficial to improve the reliability of device.As shown in Figure 3A, buffer
The thickness of layer 1BP is preferably at least the 1/4～1/2 of channel layer 1CP, more preferably
Thickness is equal, so most preferably improves the thin film growth quality of epi channels layer 1CP, reduces
Channel surface defect.Preferably, after epitaxial growth, each epitaxial layer of cmp planarizationization is straight
To exposure STI 2 and the second fin 1FN again.Now, the first channel layer 1CP, first are delayed
The first fin 1FN that layer 1BP is rushed with residual constitutes first area fin stacking.Fig. 3 B
For the sectional view that Fig. 3 A first areas extend in a first direction.
As shown in Figure 4 A and 4 B shown in FIG., at first area (such as PMOS, or NMOS)
Hard mask figure 3 is formed, is completely covered and is protected first area fin stacking, and expose the
Two fin 1FN.For example by works such as PECVD, LPCVD, HDPCVD, magnetron sputterings
Skill forms silicon oxide, silicon nitride, silicon oxynitride, the hard mask of DLC, ta-C material, and light
Carve/etch and form mask graph 3.Fig. 4 B are what Fig. 4 A first areas extended in a first direction
Sectional view.
As fig. 5 a and fig. 5b, with technique shown in Fig. 2A and Fig. 2 B and it is equivalently-sized or
It is similar, with mask graph 3 as mask, the exposed second fin 1FN of selective etch,
Multiple second opening 2TN are left in STI 2.Fig. 5 B be Fig. 5 A second areas in along first party
To the sectional view for extending.
As shown in Figure 6 A and 6 B, Fig. 6 B be Fig. 6 A second areas in prolong in the first direction
The sectional view stretched, the second channel layer of epitaxial growth in the second opening 2TN of second area
1CN, and epitaxial growth second optionally or was preferably further included before extension 1CN
Cushion 1BN (namely cushion 1BN can not also be present).Second channel layer 1CN materials
Matter is different from the first channel layer 1CP, but similarly can selected from Ge, SiGe, SiC,
SiGeC, Group III-V compound semiconductor, II-VII compound semiconductors any one and its
Combination, be selected from Ge, SiGe, SiC, SiGeC, SiGeSn, SiGaN, SiGaP,
SiGaAs、InSiN、InSiP、InSiAs、InSiSb、GaN、InSb、InP、InAs、
Any one of GaAs, SiInGaAs and combinations thereof.For example, in an embodiment of the invention,
Channel layer 1CN is used for NMOS, and its material is above-mentioned Group III-V compound semiconductor, II-VII
Compound semiconductor；In another embodiment, channel layer 1CN is used for PMOS,
Its material is Ge.Equally, each epitaxial layer of cmp planarizationization is until exposure STI2.
As shown in figures 7 a and 7b, Fig. 7 B are along first in Fig. 7 A first or second area
The sectional view that direction extends, returns and carves STI 2, exposes (being preferably completely exposed) at least in part
First channel layer 1CP and the second channel layer 1CN.For example with dHF, (HF is sour for dilution
Aqueous solution), dBOE (dilution NH4F and HF mixed aqueous solutions) etching oxidation silicon STI2,
Or select carbon fluorine base gas anisotropic dry etch STI 2.As shown in Figure 7 A, STI 2
Etch-stop stop in the interface of channel layer and cushion, but in other embodiments, can be with
Further increase STI 2 times carve depth with expose at least in part cushion 1BP/1BN (and
Optionally further sideetching forms depression), subsequently will be slow by oxidation and/or nitriding process
Rush layer segment or be completely transformed into dielectric material, so as to reduce or eliminate substrate leakage currents, carry
The reliability of high device.
As shown in Figure 8 A and 8 B, Fig. 8 B be in Fig. 8 A first or second area in the first direction
The sectional view of extension, forms dummy grid stacking.For example by LPCVD, PECVD, evaporation,
The techniques such as sputtering (magnetron sputtering), form bed course 4A and dummy gate layer 4B, and photoetching/etching
The dummy grid stacking lines that formation extends in a second direction.Bed course 4A is used to protect channel layer
1CP/1CN surfaces, avoid in subsequent etching oxidizing process surface defect density increase, material
For example, silicon oxide, silicon nitride, non-crystalline silicon, amorphous germanium, amorphous carbon, SiOC, low-k materials
Deng and combinations thereof, it is therefore preferable to distinguish with 2 materials of STI, so as to avoid subsequent etching mistake
Unexpectedly removed in journey.Dummy gate layer 4B material be, for example, polysilicon, non-crystalline silicon, microcrystal silicon,
Amorphous carbon, polycrystalline germanium, amorphous germanium etc. and combinations thereof.Optionally, it is stacked as covering with dummy grid
Mould, execution are lightly doped the source and drain that ion implanting forms low concentration shallow junction deep (namely LDD structures)
Extension area 1LS and 1LD.Subsequently both sides (in the first direction) are stacked in dummy grid form nitrogen
The grid curb wall 4C of the materials such as SiClx, diamond like carbon amorphous carbon (DLC).
As shown in fig. 9 a and fig. 9b, Fig. 9 B be in Fig. 9 A first or second area in the first direction
The sectional view of extension, forms heavy-doped source drain region.Heavy doping is performed by mask of grid curb wall 4C
Ion implanting forms source and drain the heavily doped region 1HS and 1HD of the big junction depth of high concentration, optionally in weight
Lifting source-drain area 1ES and 1ED is epitaxially formed on doped source drain region to reduce source-drain series resistance.
In another preferred embodiment of the invention, before injection doping forms source-drain area, first with dummy grid
Mask selective etching channel layer 1CP/1CN is stacked as, dummy grid is removed and is stacked in the first direction
The channel layer 1CP/1CN of both sides forms the source and drain groove of exposure cushion 1BP/1BN and (does not show
Go out), and the channel layer 1CP/1CN for only retaining dummy grid stacking lower section is used as the final ditch of device
Road area, subsequently in source and drain groove, other high mobility materials of epitaxial growth are (preferably synchronous to mix
It is miscellaneous) source-drain area is formed, subsequently re-form other source-drain area parts.The ionic type of injection doping
Choose according to MOSFET types, such as it is for PMOS is As, P, Sb, Sn etc., right
In NMOS be B, BF2, Be, In, Ga etc..Preferably, after forming source-drain area,
Metal silicide (not shown) is formed on source-drain area and is connect with reducing interface potential barrier, reducing source and drain
Get an electric shock and hinder.Optionally, before forming heavy-doped source drain region and source and drain extension, or even form ditch
Before channel layer, to undoped buffer layer (doping in situ when injection doping or epitaxial growth) with tool
There is the doping type contrary with source-drain area so that substrate break-through is prevented using PN junction.Or optionally
Ground, after above-mentioned source and drain etching groove exposure cushion, performs ion implanting (note to cushion
Enter O and/or N) and to anneal so that buffer layer part is completely transformed into the dielectric layer of insulation,
The anti-break-through performance of substrate is improved further.
As shown in figs. 10 a and 10b, Figure 10 B are along first in Figure 10 A first or second area
The sectional view that direction extends, selective etch remove dummy grid stacking.Pass through on whole device
The techniques such as spin coating, spraying, silk screen printing, CVD form the interlayer dielectric layer (ILD) of low-k materials
5.Cmp planarization ILD 5 is until exposure dummy gate layer 4B.Selective etch removes dummy gate layer
4B and bed course 4A, until forming gate openings 5G of exposure channel layer 1CP/1CN.Dummy grid
When layer 4B is Si (amorphous, crystallite, polycrystalline), from KOH, TMAH wet etching, layer
When 4B is amorphous carbon, from oxygen plasma dry etching.HF is selected when bed course 4A is silicon oxide
Base etching agent wet etching, selects hot phosphoric acid when layer 4A is silicon nitride.
As seen in figs. 11a and 11b, Figure 11 B are along first in Figure 11 A first or second area
The sectional view that direction extends, forms gate stack in gate openings 5G.By PECVD,
The techniques such as MOCVD, MBE, ALD, evaporation, sputtering, sink in gate openings 5G successively
The grid conducting layer 6BP/6BN of the gate insulator 6A and metal material of product high-g value, structure
Into gate stack structure.High-g value is included selected from HfO2、HfSiOx、
HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnio material
(wherein, each material is different according to multi-element metal component proportion and chemical valence, and oxygen atom contains for material
Amount x can Reasonable adjustment, can for example be 1～6 and be not limited to integer), or including selected from ZrO2、
La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or including Al2O3,
With the composite bed of its above-mentioned material.Grid conducting layer can be then polysilicon, poly-SiGe or gold
Category, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta,
The conjunction of the metal simple-substances such as Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals
Gold and these metals nitride, in grid conducting layer can also doped with C, F, N, O,
The elements such as B, P, As are adjusting work function.It is also excellent between grid conducting layer and gate insulator
The barrier layer (not shown) that the conventional methods such as PVD, CVD, ALD form nitride was gated,
Barrier layer material is MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M be Ta,
Ti, Hf, Zr, Mo, W or other elements.It is highly preferred that grid grid conducting layer and stop
Layer only with lamination layer structure stacked up and down, can also not adopt the injection doped layer knot for mixing
Structure, namely the material of grid conducting layer and barrier layer is constituted while being deposited on gate insulator,
Therefore grid conducting layer includes the material on above-mentioned barrier layer.Preferably, the metal gate of first area
Pole conductive layer 6BP is different with different from the metal gates conductive layer 6BN materials of second area
Work function, such as first the first metal conducting layer of sedimentary facies same material equal in gate openings 5G
6BP, then forms mask graph and covers first area exposure second area, and etching removes second
6BP in region is until exposed surface 6A, then deposits the second metal conducting layer 6BN.CMP puts down
Smoothization gate stack structure is until exposure ILD 5.Hereafter, according to standard technology, in ILD 5
The through source-drain area 1S/D of etching source and drain contact hole (not shown), deposits gold in source and drain contact hole
The barrier layer of category nitride and the conductive layer of metal material, form source and drain contact plug and (do not show
Go out).
According to the CMOS manufacture methods of the present invention, selectivity is returned carves substrate fin and epitaxial growth
The mobility channel fin of different materials, improves CMOS carriers low-cost high-efficiency
Mobility and driving force.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture
And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or
The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to
It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (10)
1. a kind of CMOS manufacture methods, including step：
Etched substrate forms multiple first fins and multiple second fins for extending in a first direction；
Shallow trench isolation is formed between multiple first fins and multiple second fins；
Multiple first fins are removed at least in part, leave multiple first openings；
The first channel layer of epitaxial growth in the multiple first openings；
Multiple second fins are removed at least in part, leave multiple second openings；
The second channel layer of epitaxial growth in the multiple second openings；
The gate stack for extending in a second direction is formed on the first channel layer and the second channel layer；
In the first channel layer and the second channel layer, both sides form source-drain area to gate stack in the first direction.
2. method as claimed in claim 1, wherein, the carrier mobility of the first channel layer and/or the second channel layer is higher than substrate；Optionally, the first channel layer is different from the second channel layer material；Preferably, the material of the first channel layer and/or the second channel layer is any one of Ge, SiGe, SiC, SiGeC, Group III-V compound semiconductor, II-VII compound semiconductors and combinations thereof.
3. method as claimed in claim 1, wherein, further include before epitaxial growth first and/or the second channel layer, epitaxial growth first and/or second buffer layer in the multiple first and/or second opening；Preferably, first and/or second buffer layer lattice paprmeter between substrate and the first and/or second channel layer；Preferably, the conduction type of first, second cushion is contrary with source-drain area.
4. method as claimed in claim 1, wherein, further include the step of remove multiple second fins at least in part, form the first channel layer that mask graph is covered on multiple first fins, multiple second fins are removed by mask selective etching of mask graph.
5. method as claimed in claim 1, wherein, further include before forming the gate stack for extending in a second direction, return and carve shallow trench isolation, expose the first channel layer and the second channel layer at least in part.
6. method as claimed in claim 5, wherein, the top of shallow trench isolation is equal to or less than the bottom of the first channel layer and/or the second channel layer.
7. method as claimed in claim 6, wherein, dielectric layer is formed in the first and/or second channel layer bottom part down.
8. method as claimed in claim 1, wherein, source-drain area include source drain extension area, source and drain heavily doped region, at least one of lifting source-drain area.
9. method as claimed in claim 1, wherein, gate stack is dummy grid stacking.
10. method as claimed in claim 1, wherein, further include after forming source-drain area, form interlayer dielectric layer and cover whole substrate, etching removes dummy grid and stacks so that gate openings are left in interlayer dielectric layer, and the grid conducting layer of the gate dielectric layer and metal material of hafnium is formed in gate openings.
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