CN106549016B - Semiconductor devices and preparation method thereof - Google Patents
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Abstract
A kind of semiconductor devices, comprising: the first epitaxial layer, on substrate；Second epitaxial layer, on the first epitaxial layer；First source/drain region and the second source/drain region, in the first epitaxial layer and the second epitaxial layer；First channel is made of the second epitaxial layer between the first source/drain region；First grid stacks, and on the first channel, the first source/drain region, the first channel and first grid, which stack, constitutes the first device；Second channel is made of the first epitaxial layer between the second source-drain area；Second grid stacks, and on the second channel, the second source/drain region, the second channel and second grid, which stack, constitutes the second device.According to semiconductor and preparation method thereof of the invention, one of two epitaxial layers being stacked on substrate are removed by selective etch, the channel of different materials is formed for NMOS and PMOS, simply and effectively improves carrier mobility and CMOS driving capability.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its manufacturing methods, more particularly to a kind of cmos device and its manufacturer
Method.
Background technique
Improving device performance is always CMOS technology focus, and existing maturation scheme includes strain engineering, height -- k gold
Belong to gate technique and nonplanar multi-gate device structure etc..
Traditional strain gauge technique mainly introduces desired stress in channel and then being epitaxially formed source and drain, and (nMOSFET is introduced
Tensile stress, pMOSFET introduce compression).Because N-shaped and p-type MOSFET element need to introduce different stress, extension can only
Substep carries out, and brings technologic complexity.It in the synchronous introducing of channel of two kinds of devices or is further increased by simple process
The strain of required type will be very valuable.
On the other hand, electron mobility is apparently higher than hole mobility in existing planar CMOS device, generally by
The size of pMOSFET is adjusted to realize the matching of pMOSFET and nMOSFET performance, and then the comprehensive performance for improving circuit, but this
Sample will increase the area of pMOSFET, improve cost.Germanium silicon (SixGe1--x) hole mobility of alloy material is apparently higher than silicon material
Material, therefore by SixGe1--xIt is very significant to introduce pMOSFET.
Summary of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, a kind of simple and effective raising CMOS of energy is proposed
The semiconductor devices and its manufacturing method of driving capability.
For this purpose, the present invention provides a kind of semiconductor devices, comprising: the first epitaxial layer, on substrate；Second epitaxial layer,
On the first epitaxial layer；First source/drain region and the second source/drain region, in the first epitaxial layer and the second epitaxial layer；First channel,
It is made of the second epitaxial layer between the first source/drain region；First grid stacks, on the first channel, the first source/drain region, first
Channel and first grid, which stack, constitutes the first device；Second channel is made of the first epitaxial layer between the second source-drain area；Second
Gate stack, on the second channel, the second source/drain region, the second channel and second grid, which stack, constitutes the second device.
Wherein, the first epitaxial layer and/or the second epitaxial layer are the high mobility material that carrier mobility is greater than substrate；Appoint
Selection of land, high transport materials include being selected from SiGe, SiC, SiGeC, Ge, GeSn, GaN, GaP, GaAs, InN, InP, InAs, InSb
High mobility material or their component proportion material, such as SiGeSn, InGaAs.
Wherein, the thickness of the first channel is more than or equal to 5nm.
Wherein, the first source/drain region and/or the second source/drain region include source drain extension area, source and drain heavily doped region and optionally
Dizzy shape source-drain area is optionally lifted source-drain area.
Wherein, there is isolated area between the first device and the second device；Optionally, have on the first and/or second source/drain region
There are stressor layers and/or metal silicide.
Wherein, first and/or second grid stack include high-g value gate dielectric layer and metal material grid it is conductive
Layer；It optionally, include transition zone between gate dielectric layer and the first and/or second channel.
The present invention also provides a kind of method, semi-conductor device manufacturing methods, comprising: sequentially forms the first epitaxial layer on substrate
With the second epitaxial layer；On the second epitaxial layer, forms the first dummy grid in the first region and stack and in the second area
Second dummy grid stacks；In the second epitaxial layer and the first epitaxial layer, the first source/drain region in the first region is formed and
The second source/drain region in two regions；Interlayer dielectric layer is formed on the substrate；The first and second dummy grids stacking is removed, in interlayer
First grid opening and second grid opening are left in dielectric layer；Second epitaxial layer in selective removal second grid opening
At least partially；The first and second gate stacks are formed in the first and second gate openings respectively, second grid stacks direct
Contact the first epitaxial layer, second grid stacks the first lower epitaxial layer and is used as the second channel, and first grid, which stacks, directly contacts the
Two epitaxial layers, the second epitaxial layer under first grid stacks are used as the first channel.
Wherein, unstripped gas proportion is adjusted to form the first epitaxial layer that carrier mobility is higher than substrate in identical chamber
With the second epitaxial layer.
Wherein, after at least part of the second epitaxial layer of selective removal, the second epitaxial layer it is remaining with a thickness of 1~
2nm。
Wherein, form the first source/drain region and the second source/drain region further comprises that epitaxial growth is lifted source-drain area later, is appointed
Selection of land forms stressor layers.
According to the CMOS channel material process integration scheme of the application, wherein nMOSFET still uses silicon to make channel,
PMOSFET does channel using SiGe.Since there are SiGe, (Ge atomic radius is greater than Si atom half below nMOSFET silicon channel
Diameter), twin shaft tensile strain can be introduced in Si channel in this way, increases the mobility of electronics.In the device channel region pMOSFET, pass through
The Si layer (doing sacrificial layer) above SiGe is thinned, the P-type device using SiGe as channel can be finally obtained, to improve pMOSFET
Performance.Wherein on the one hand Si sacrificial layer can reduce damage of the integrated technique to SiGe channel, and on the other hand oxidation is formed
SiOx is used as height -- the transition zone between k medium and SiGe.Due to SixGe1--xLayer is to grow on a si substrate, therefore can be
SixGe1--xMiddle increase compressive strain, can also further increase hole mobility in this way.The CMOS channel Integrated Solution and existing CMOS
Technique is completely compatible, and is easier to realize.
According to semiconductor and preparation method thereof of the invention, two extensions being stacked on substrate are removed by selective etch
One of layer forms the channel of different materials for NMOS and PMOS, simply and effectively improves carrier mobility and CMOS drives
Kinetic force.
Detailed description of the invention
Carry out the technical solution that the present invention will be described in detail referring to the drawings, in which:
Fig. 1 to Fig. 5 is the diagrammatic cross-section according to each step of CMOS manufacturing method of the invention.
Specific embodiment
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the device and its manufacturing method for effectively improving CMOS driving capability.It should be pointed out that similar attached drawing mark
Note indicates similar structure, and term " first " use herein, " second ", "upper", "lower" etc. can be used for modifying various
Device architecture or manufacturing process.These modifications do not imply that the sky of modified device architecture or manufacturing process unless stated otherwise
Between, order or hierarchical relationship.
Referring to Fig.1, at least two epitaxial layer 1E and 1C of stacking are formed on substrate 1S.Substrate 1S is provided, according to device
Purposes is needed and is reasonably selected, it may include monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained Si), germanium silicon
, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (SiGe) or compound semiconductor materials
(InSb) and carbon-based semiconductors such as graphene, SiC etc..For the consideration compatible with CMOS technology, substrate 1S is preferably
For body Si.By depositing operations such as MOCVD, PECVD, UHVCVD, HDPCVD, MBE, ALD, successively formed outside first in substrate 1S
Prolong layer 1E and the second epitaxial layer 1C.Preferably, the material of epitaxial layer 1E and 1C include at least high mobility material, such as relative to
For the Si material of substrate 1S, at least one (can also be both) of two epitaxial layers include selected from SiGe, SiC, SiGeC, Ge,
The high mobility material or their combination material such as component proportion of GeSn, GaN, GaP, GaAs, InN, InP, InAs, InSb
Material, such as SiGeSn, InGaAs.
In a preferred embodiment of the invention, epitaxial layer 1E material is SixGe1--x, epitaxial layer 1C material is Si, such as
Pass through unstripped gas (Si in control MOCVD technique2H2Cl2With GeH4) component proportion and the variation that adjusts Ge content in SiGe is (outer
Prolonging layer 1C may be regarded as the SiGe that Ge content is 0), to realize the deposition of continuous two epitaxial layers in a process cavity.Wherein,
Epitaxial layer 1E with a thickness of 10~100nm and preferably 30~70nm, Ge content determine, example according to the film quality of epitaxial layer 1E
For example 20~50% and preferably 30%.Preferably, the thickness of epitaxial layer 1C is more than or equal to 10nm, such as 10~50nm, to guarantee
There are also certain thickness Si to remain after a series of oxidations, etching technics.
In other preferred embodiments of the invention, when substrate 1S is Si, epitaxial layer 1E material is SiC and epitaxial layer 1C
Material be Si perhaps layer 1E material be SiGe and layer 1C material be Ge perhaps layer 1E is SiGe and layer 1C is SiGeC or layer
1E is SiC and layer 1C is SiGeC, and the purpose or standard that material selects make each layer of 1S, 1E, 1C to adjust each component proportion
Between as far as possible lattice constant close to reduce boundary defect and guarantee as far as possible promoted device property.When substrate 1S be Ge,
When the other materials such as GaN, GaAs, the standard selected is also identical.Similarly, the thickness relationship of the layer of these different materials is similar to
The above situation of Si+SiGe+Si.
Referring to Fig. 2, pseudo- grid are formed on epitaxial layer 1C and are stacked.
Firstly, forming isolated area 2 in substrate 1S.Such as extension is sequentially etched by anisotropic dry etch process
Then layer 1C, epitaxial layer 1E are deposited or are aoxidized in the opening until forming exposure and going deep into the opening (not shown) in substrate 1S
Filling forms separation layer 2, material such as silica or silicon oxynitride, the isolated area as device, or makees shallow trench isolation
(STI).The region that STI 2 is surrounded constitutes active area, and left side corresponds to multiple first areas of such as NMOS in Fig. 2, and right side is right
Multiple second areas of Ying Yu such as PMOS, but be not only isolated by STI 2 between two regions but may exist multiple
Insertion element.It is further preferred that be mask using photoetching offset plate figure (not shown), to first area and second area respectively into
Row ion implanting is lightly doped, formed different well regions (it is not separately shown, for example, in the first area of NMOS formed p trap, and
N trap is formed in the second area of PMOS), to enhance the effect being dielectrically separated between device.It is further preferred that STI 2
Isolation oxide is negative expansion dielectric material or just thermally expands dielectric material, is further increased with the stress provided by STI
The carrier mobility in future channel area.Wherein, negative expansion dielectric material is perofskite type oxide, including
Bi0..95La0..05NiO3、BiNiO3、ZrW2O8；Positive thermal expansion dielectric material includes Ag3[Co(CN)6].Preferably, STI 2 every
It is greater than 10 using the absolute value of the coefficient of cubical expansion linear at a temperature of 100K from oxide-4/K。
Secondly, forming bed course 3A by techniques such as LPCVD, PECVD, thermal oxide, thermal decompositions on entire chip, then lead to
It crosses the techniques such as CVD, PVD and forms dummy gate layer 3B, etch layer 3B and 3A form dummy grid and stack.Bed course 3A material for example aoxidizes
Silicon.The silicon substrates materials such as dummy grid 3B material such as polysilicon, amorphous silicon, microcrystal silicon are also possible to amorphous carbon, diamond-like without fixed
The non-silicon-based such as shape carbon (DLC), amorphous carbon nitrogen, polycrystalline boron nitrogen, amorphous fluorination hydrogenated carbon, noncrystal carbon fluoride, fluorination tetrahedral carbon
Material.In bed course 3A forming process, if needing the thickness of epitaxial layer 1C to be more than or equal to 5nm using thermal oxidation technology, with
Ensure to be formed oxide still has enough epitaxial layer 1C to retain for subsequent processing later.
Then, source-drain area is formed.Photoresist (not shown) is formed on second area (such as right side in figure), then with pseudo- grid
Pole stacks 3B/3A and photoetching offset plate figure is mask, carries out the first ion implanting to epitaxial layer 1C and 1E, in the first region (extremely
It is few in the second epitaxial layer 1C, can continue to go deep into the first epitaxial layer 1E) form the source drain extension of lightly doped drain (LDD) structure
Area.Optionally, carry out angle-tilt ion injection, source drain extension area and subsequent channel region interface formation be lightly doped it is bag-shaped or dizzy
Shape area (area halo) 1HN is for finely controlling channel conduction.Then deposit and etch in the dummy grid stacking side 3B/3A to be formed
Isolation side walls 3S, material such as silicon nitride or silicon oxynitride.Using isolation side walls as mask, the second ion implanting is carried out, the
Source and drain heavily doped region is formed in one region (mainly in the first epitaxial layer 1E).The common structure of source and drain heavily doped region and source drain extension area
At source region 1SN shown in Fig. 2 and drain region 1DN, epitaxial layer 1CN between source-drain area (and the top section of epitaxial layer 1E, depend on
In the control of source-drain area junction depth) it will later serve as the conducting channel of NMOS device.Then, light is deposited with similar process selectivity
The techniques such as photoresist, deposition, injection also form source region 1SP, the drain region area 1NP, Halo 1HP in second area, between source-drain area there are
Epitaxial layer 1CP and 1EP.Optionally, it is formed after source-drain area, forms metal silicide on source-drain area surface to reduce source and drain contact
Resistance.
, can also be further in the second epitaxial layer 1C in addition, although source-drain area shown in Fig. 2 obtains for ion implanting
On formed homogeneity or heterogeneous third epitaxial layer (not shown) and in situ doping to constitute be lifted source-drain area (not shown), into
One step increases the stress in channel and reduces source and drain dead resistance.
Optionally, it is formed after source-drain area and optional silicide contacts, deposited silicon nitride or DLC material on entire chip
The contact etching stop layer (CESL is not shown) of material is for use as stressor layers, to further enhance channel region stress.
Then, interlayer dielectric layer (ILD) 4 is formed.Such as pass through the techniques shape such as silk-screen printing, spraying, spin coating, CVD deposition
At the ILD of low-K material, wherein low-k materials include but is not limited to that organic low-k materials are (such as organic containing aryl or polynary ring
Polymer), it is inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), more
Hole low-k materials (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous silica, porous SiOCH, mix C titanium dioxide
Silicon mixes the porous amorphous carbon of F, porous diamond, porous organic polymer).Cmp planarization chemical industry skill is then carried out, until exposure
Dummy grid 3B.
Referring to Fig. 3, the dummy grid of removal dummy grid 3B and bed course 3A is stacked, and first grid opening is left in ILD layer 4
4GN and second grid opening 4GP, exposure epitaxial layer 1CN and 1CP.For different dummy grid material selection anisotropic quarters
Etching technique, such as TMAH wet etching are directed to the bed course 3A of oxidation silicon material for dummy grid 3B, the HF wet etching of Si material,
Fluorine-based (the C of carbonxHyFz, xyz numerical value select so that constituting saturated or unsaturated fluorohydrocarbon) plasma etching one step etch layer 3B and
3A, oxygen plasma dry etching are directed to the dummy grid 3B etc. of C material.
Referring to Fig. 4, at least part of the second epitaxial layer 1CP in selective removal second area.Such as entire brilliant
On piece coats photoresist and exposure development, leaves photoetching offset plate figure 5 in the first region, covers ILD 4 and be filled up completely
First grid is open 4GN.Through second grid opening 4GP, anisotropically for example, by the fluorine-based dry plasma etch of carbon
With removing the second epitaxial layer 1CP at least part.In an embodiment of the invention, the second epitaxial layer 1CP is completely removed, cruelly
The first epitaxial layer 1E of lower section is revealed.In another embodiment, the second epitaxial layer 1CP thickness (such as from 10~
50nm) it is thinned to 1~2nm, on the one hand remaining second epitaxial layer can protect in second area the first epitaxial layer 1EP channel not
It is destroyed by subsequent technique, on the other hand can be used as channel region 1EP and subsequent height -- the transition between k gate medium with partial oxidation
Layer reduces the degeneration of interfacial state and interface scattering to device performance.
Referring to Fig. 5, first grid be open in 4GN and second grid opening 4GP formed first grid stack 6AN/6BN and
Second grid stacks 6AP/6BP.By techniques such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, in first area
High k material is formed in the first grid opening 4GN of (NMOS area) and in the second grid opening 4GP of second area (PMOS area)
The the first gate dielectric layer 6AN and the second gate dielectric layer 6AP of material.High-g value includes but is not limited to include selected from HfO2、HfSiOx、
HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnium sill (wherein, each material is according to multi-element metal
Component proportion and chemical valence are different, and oxygen atom content x can be reasonably adjusted, be may be, for example, 1~6 and be not limited to integer), or packet
It includes selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare-earth base high K dielectric material, or including Al2O3, with its above-mentioned material
Composite layer.It is then same using techniques such as MOCVD, MBE, ALD, magnetron sputterings in first grid opening and second grid opening
When deposit first grid conductive layer 6BN, preferably completely filling first grid be open 4GN.Grid conductive layer 6BN then can for polysilicon,
Poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu,
The nitride of the alloy and these metals of the metal simple-substances such as Nd, Er, La or these metals can also adulterate in grid conductive layer 6BN
There are the elements such as C, F, N, O, B, P, As to adjust work function.Between grid conductive layer 6BN and gate dielectric layer 6AN further preferably by PVD,
The conventional methods such as CVD, ALD form the barrier layer (not shown) of nitride, and barrier layer material is MxNy、MxSiyNz、MxAlyNz、
MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.It is highly preferred that grid conductive layer 6BN and barrier layer are not only
Using lamination layer structure stacked up and down, can also using the injection doped layer structure mixed, namely constitute grid conductive layer 6BN with
The material on barrier layer is deposited on gate dielectric layer 6AN simultaneously, therefore grid conducting layer includes the material on above-mentioned barrier layer.It deposited
After first grid conductive layer 6BN, photoresist or hard mask are covered in first area, selective etch technique is executed and removes the secondth area
First grid conductive layer 6BN in the second grid opening in domain, then using similar technique in first area and second grid
Second grid conductive layer 6BP is deposited (since first grid conductive layer 6BN has completely filled the first grid before simultaneously in opening
Pole opening, therefore layer 6BP will not enter gate openings on the first region and be placed only on ILD), it is flat that CMP is executed later
Smoothization is until exposure ILD.As shown in figure 5, wherein second grid dielectric layer 6AP directly contacts the first epitaxial layer 1EP, therefore extension
The top of layer 1EP is used as the channel of the PMOS of second area.
Finally, etching ILD 4 forms the contact hole of exposure source-drain area, the in the contact hole barrier layer of deposited metal nitride
Filled layer with metal or alloy completes the interconnection of device to form contact plunger.
Finally manufacture obtained cmos device as shown in figure 5, include substrate 1S, the first epitaxial layer 1E on substrate 1S,
The second epitaxial layer 1C on the first epitaxial layer 1E, the first source/drain region in the first epitaxial layer 1E and the second epitaxial layer 1C
1SN/1DN and the second source-drain area 1SP/1DP, the second epitaxial layer 1C between the first source/drain region constitute the first channel, the second source
The first epitaxial layer 1E between drain region constitutes the second channel, and first grid stacks 6AN/6BN and is located on the first channel, second grid
Stack 6AP/6BP be located on the second channel, the first source-drain area, the first channel, first grid stack composition the first device (such as
NMOS), the second source-drain area, the second channel and second grid, which stack, constitutes the second device (such as PMOS).
Although FIG. 1 to FIG. 5 shows the NMOS in left side and the PMOS on right side, actually can also be according to epitaxial layer
1E, 1C material is different and select that the first device of left side is PMOS, the second device of right side is NMOS, and correspondingly class is adulterated in adjustment
Type and work function.
According to semiconductor and preparation method thereof of the invention, two extensions being stacked on substrate are removed by selective etch
One of layer forms the channel of different materials for NMOS and PMOS, simply and effectively improves carrier mobility and CMOS drives
Kinetic force.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the disclosed specific embodiment for realizing preferred forms of the invention, and disclosed device architecture
And its manufacturing method will include all embodiments fallen within the scope of the present invention.
Claims (13)
1. a kind of semiconductor devices, comprising:
First epitaxial layer, on substrate；
Second epitaxial layer, on the first epitaxial layer；
First source/drain region and the second source/drain region, in the first epitaxial layer and the second epitaxial layer；
First channel is made of the second epitaxial layer between the first source/drain region；
First grid stacks, and on the first channel, the first source/drain region, the first channel and first grid, which stack, constitutes the first device；
Second channel is made of the first epitaxial layer between the second source/drain region, also has remaining second extension on the second channel
Layer；
Second grid stacks, and on the second channel, the second source/drain region, the second channel and second grid, which stack, constitutes the second device.
2. semiconductor devices as claimed in claim 1, wherein the first epitaxial layer and/or the second epitaxial layer are big for carrier mobility
In the high mobility material of substrate.
3. semiconductor devices as claimed in claim 2, wherein the high mobility material include selected from SiGe, SiC, SiGeC, Ge,
The high mobility material or their combination material of GeSn, GaN, GaP, GaAs, InN, InP, InAs, InSb.
4. semiconductor devices as claimed in claim 1, wherein the thickness of the first channel is more than or equal to 5nm.
5. semiconductor devices as claimed in claim 1, wherein the first source/drain region and/or the second source/drain region include source drain extension area,
Source and drain heavily doped region, dizzy shape source-drain area or lifting source-drain area.
6. semiconductor devices as claimed in claim 1, wherein have isolated area between the first device and the second device.
7. semiconductor devices as claimed in claim 1, wherein have stressor layers and/or metal on the first and/or second source/drain region
Silicide.
8. semiconductor devices as claimed in claim 1, wherein first and/or gate dielectric layer of the second grid stacking including high-g value
And the grid conductive layer of metal material.
9. semiconductor devices as claimed in claim 1, wherein include transition zone between gate dielectric layer and first and/or the second channel.
10. a kind of method, semi-conductor device manufacturing method, comprising:
The first epitaxial layer and the second epitaxial layer are sequentially formed on substrate；
On the second epitaxial layer, the first dummy grid formed in the first region is stacked and the second dummy grid in the second area
It stacks；
In the second epitaxial layer and the first epitaxial layer, the first source/drain region in the first region and in the second area is formed
Second source/drain region；
Interlayer dielectric layer is formed on the substrate；
The first and second dummy grids stacking is removed, first grid opening and second grid opening are left in interlayer dielectric layer；
At least part of the second epitaxial layer in selective removal second grid opening；
The first and second gate stacks are formed in the first and second gate openings respectively, second grid stacks directly contact first
Epitaxial layer, the first epitaxial layer under second grid stacks are used as the second channel, and first grid, which stacks, directly contacts the second epitaxial layer,
The second epitaxial layer under first grid stacks is used as the first channel.
11. such as the method, semi-conductor device manufacturing method of claim 10, wherein adjust unstripped gas proportion to be formed in identical chamber
Carrier mobility is higher than the first epitaxial layer and the second epitaxial layer of substrate.
12. such as the method, semi-conductor device manufacturing method of claim 10, wherein at least part of the second epitaxial layer of selective removal
Later, the second epitaxial layer is remaining with a thickness of 1~2nm.
13. such as the method, semi-conductor device manufacturing method of claim 10, wherein formed after the first source/drain region and the second source/drain region
It further comprise that epitaxial growth is lifted source-drain area and/or forms stressor layers.
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| CN102203924A (en) * | 2008-10-30 | 2011-09-28 | 飞思卡尔半导体公司 | Optimized compressive sige channel pmos transistor with engineered ge profile and optimized silicon cap layer |
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| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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