CN118366929A

CN118366929A - Manufacturing method of semiconductor device

Info

Publication number: CN118366929A
Application number: CN202410781132.6A
Authority: CN
Inventors: 薛翔; 郭廷晃; 林智伟
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2024-06-18
Filing date: 2024-06-18
Publication date: 2024-07-19
Anticipated expiration: 2044-06-18
Also published as: CN118366929B

Abstract

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a pseudo gate on the substrate, wherein a gate material layer of the pseudo gate comprises an amorphous carbon nitrogen layer; forming side wall structures on two sides of the pseudo grid electrode; forming a heavily doped region in the substrate at one side of the side wall structure far away from the pseudo grid electrode; forming a metal silicide layer on the heavily doped region; forming a dielectric layer on the substrate, wherein the surface of the dielectric layer is flush with the surface of the dummy gate; removing the pseudo grid electrode by dry etching to form a concave part; a metal gate is formed within the recess. The manufacturing method of the semiconductor device provided by the invention can control the height of the metal grid and improve the electrical property of the semiconductor device.

Description

Manufacturing method of semiconductor device

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a semiconductor device.

Background

With the continuous development of integrated circuit manufacturing technology, in order to achieve faster operation speed, larger data storage amount and more functions, integrated circuit chips are developing toward higher semiconductor device density and higher integration level. With the continuous shrinking of the feature size of semiconductor devices, the polysilicon gate process cannot meet the requirements of the semiconductor devices, and the problems of threshold voltage drift, polysilicon gate depletion effect, excessively high gate resistance, pinning of fermi level and the like can be solved by adopting a metal gate to replace the polysilicon gate. However, in the process of manufacturing the metal gate, the polysilicon dummy gate is easy to have problems of metallization or ionization, so that the polysilicon dummy gate is remained or the gate height is difficult to control, and the performance of the metal gate is limited.

Disclosure of Invention

The invention aims to provide a manufacturing method of a semiconductor device, which can completely remove a gate material layer in a pseudo gate when forming the metal gate, control the height of the metal gate, improve the height consistency of the metal gate and improve the electrical property of the semiconductor device.

In order to solve the technical problems, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:

Providing a substrate, and forming a pseudo gate on the substrate, wherein a gate material layer of the pseudo gate comprises an amorphous carbon nitrogen layer;

Forming side wall structures on two sides of the pseudo grid electrode;

forming a heavily doped region in the substrate at one side of the side wall structure far away from the pseudo grid electrode;

Forming a metal silicide layer on the heavily doped region;

forming a dielectric layer on the substrate, wherein the surface of the dielectric layer is flush with the surface of the dummy gate;

removing the pseudo grid electrode by dry etching to form a concave part; and

A metal gate is formed within the recess.

In an embodiment of the present invention, an atomic ratio of nitrogen atoms to carbon atoms in the gate material layer is 15:85 to 20:80.

In an embodiment of the present invention, a smooth roughness of a surface of the gate material layer is less than 1nm.

In an embodiment of the present invention, the dry etching gas includes an etching gas and a carrier gas, the etching gas includes hydrogen and nitrogen, and the carrier gas includes argon.

In an embodiment of the present invention, the total flow rate of the etching gas and the carrier gas is 60 sccm-80 sccm, the flow rate of the carrier gas is 40 sccm-60 sccm, and the ratio of nitrogen in the etching gas is 0.2-0.3.

In an embodiment of the present invention, the dc bias voltage of the dry etching is 40v to 60v.

In an embodiment of the present invention, in the dry etching, an etching selection ratio of the gate material layer, the silicon oxide and the silicon nitride is 10:1:1 to 8:1:1.

In an embodiment of the present invention, the manufacturing method further includes: and forming a hard mask layer on the pseudo gate, wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially arranged on the pseudo gate.

In an embodiment of the present invention, the first hard mask layer is a silicon nitride layer, and the second hard mask layer is a silicon oxide layer.

In one embodiment of the invention, the gate material layer is prepared by porous hollow cathode plasma enhanced chemical vapor deposition,

In summary, the present application provides a method for manufacturing a semiconductor device, which has the unexpected technical effects of improving the thermal stability and adhesion of the gate material layer and ensuring the accuracy of the subsequently formed dummy gate. The defect generation in the manufacturing process can be reduced, and the manufacturing yield is improved. The metallization or ionization of the dummy gate can be avoided, so that in the subsequent process, high selectivity and complete removal can be realized when the dummy gate is removed, and the height of the metal gate is stabilized. The method can reduce the situation that the side wall structure is broken, improve the etching selection ratio of the pseudo grid electrode and the side wall structure, shorten the removal time, and further reduce the etching amount of the side wall structure, thereby being easy to control the height of the metal grid electrode, improving the height consistency of the metal grid electrode and improving the electrical property of the semiconductor device.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the invention.

FIG. 2 is a schematic diagram illustrating formation of a first photoresist layer according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a shallow trench isolation structure formed according to an embodiment of the invention.

FIG. 4 is a schematic diagram illustrating formation of a well region according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating formation of a gate material layer and a hard mask layer according to an embodiment of the invention.

FIG. 6 is a schematic diagram illustrating formation of a dummy gate according to an embodiment of the invention.

FIG. 7 is a schematic diagram illustrating formation of lightly doped regions according to an embodiment of the present invention.

Fig. 8 is a schematic diagram illustrating formation of a sidewall structure and a heavily doped region according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of forming a contact etch stop layer and a dielectric layer in accordance with an embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating a planarization of a dielectric layer to a first hard mask layer according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of the first hard mask layer removed according to an embodiment of the invention.

Fig. 12 is a schematic diagram illustrating removal of dummy gates according to an embodiment of the invention.

Fig. 13 is a schematic view of a semiconductor device according to an embodiment of the invention.

Description of the reference numerals:

10. A substrate; 101. a well region; 11. a pad oxide layer; 12. pad nitriding layer; 13. a first photoresist layer; 131. an opening; 14. shallow trench isolation structures; 15. a gate oxide layer; 16. a first gate dielectric layer; 17. a second gate dielectric layer; 18. a gate material layer; 181. a dummy gate; 19. a first hard mask layer; 20. a second hard mask layer; 21. a second photoresist layer; 22. a lightly doped region; 23. a side wall structure; 231. a first sub-layer; 232. a second sub-layer; 233. a third sub-layer; 234. a fourth sub-layer; 24. a heavily doped region; 25. a metal silicide layer; 26. a contact hole etching stop layer; 27. a dielectric layer; 28. a metal gate; 201. a recess.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

In the description of the present specification, it should be understood that the directions or positional relationships indicated in terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or component referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

According to the manufacturing method of the semiconductor device, when the metal grid is formed, the grid material layer in the pseudo grid can be completely removed, meanwhile, the etching of the side wall structure is reduced, the height of the metal grid is controlled, the height consistency of the metal grid is improved, and the electrical performance of the semiconductor device is improved. The semiconductor device prepared by the method can be widely applied to various fields such as optical communication, digital display, image receiving, optical integration, traffic, energy, medicine, household appliances, aerospace and the like.

Referring to fig. 1 and 2, in an embodiment of the present invention, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compound, and the like, and further includes a stacked structure formed of these semiconductor materials, or a silicon-on-insulator, a stacked silicon-on-insulator, a silicon-germanium-on-insulator, and a germanium-on-insulator. In the present embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate. In other embodiments, the type of substrate 10 is selected depending on the semiconductor device being fabricated. The invention is not limited to the kind of semiconductor device, and the semiconductor device is one or more of a field effect Transistor (FIELD EFFECT Transistor, FET), a Metal-Oxide-semiconductor field effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a complementary Metal Oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT), a gate turn-off Thyristor (Gate Turn off Thyristor, GTO), a Thyristor (Thyristor), and the like. In this embodiment, a method for manufacturing a semiconductor device will be described, for example, using a MOS transistor.

Referring to fig. 1, in an embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, the pad oxide layer 11 is used as a buffer layer to improve stress between the substrate 10 and a pad nitride layer 12 formed later, the pad oxide layer 11 is made of a material such as dense silicon oxide, and the pad oxide layer 11 can be formed by any one of a dry oxygen oxidation method, a wet oxygen oxidation method, or an In situ vapor growth method (In-Situ Steam Generation, ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by a dry oxidation method, specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen is introduced, the surface of the substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is better. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 20nm, 30nm, 40nm, or the like.

Referring to fig. 1 to 3, in an embodiment of the present invention, a pad nitride layer 12 is formed on a pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In the present embodiment, the pad nitride layer 12 is, for example, silicon nitride, and may be formed by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and the pad nitride layer 12 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 900 ℃, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50nm to 80nm, specifically, for example, 50nm, 60nm or 70nm, and by providing the pad nitride layer 12, the substrate 10 can be protected from planarization processes such as Chemical Mechanical Polishing (CMP) involved in the process of manufacturing the shallow trench isolation structure 14. And the pad nitride layer 12 can be used as a mask in the subsequent shallow trench isolation structure formation process to protect the substrate 10 from damage during etching of the substrate 10.

Referring to fig. 1 to 3, in an embodiment of the invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are formed on the first photoresist layer 13 through an exposure and development process, wherein the openings 131 are used to define the positions of the shallow trench isolation structures 14. Etching is performed by using the first photoresist layer 13 as a mask, and the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131 are removed, so as to form a shallow trench. In this embodiment, for example, a shallow trench (not shown) is formed by dry etching, and after the etching is completed, the first photoresist layer 13 is removed. After the shallow trenches are formed, an insulating medium is deposited in the shallow trenches until the insulating medium covers the surface of the pad nitride layer 12. In this embodiment, the insulating medium is, for example, silicon oxide. The present invention is not limited to the deposition method of the insulating medium, and for example, high-quality insulating medium can be formed by high-density plasma chemical vapor deposition (HIGH DENSITY PLASMA CVD, HDP-CVD) or high-aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD) or the like. In other embodiments, the insulating medium may be other insulating materials and methods of formation suitable for isolation.

Referring to fig. 1 to 3, in an embodiment of the invention, after the insulating medium is prepared, the insulating medium is planarized, for example, by chemical mechanical polishing (CHEMICAL MECHANICAL Polish, CMP). For example, polishing to remove part of the insulating medium and part of the pad nitride layer 12, and then removing the pad nitride layer 12 to obtain the shallow trench isolation structure 14, wherein the shallow trench isolation structure 14 is higher than the pad oxide layer 11 on two sides, for example. The present invention is not limited to the method of removing the pad nitride layer 12, and for example, dry etching, wet etching, or a combination of dry etching and wet etching is used. In this embodiment, the pad nitride layer 12 is removed, for example, with hot phosphoric acid, to form shallow trench isolation structures 14 to isolate adjacent semiconductor devices.

Referring to fig. 3 to 4, in an embodiment of the present invention, after the preparation of the shallow trench isolation structure 14 is completed, the pad oxide layer 11 is used as an ion implantation buffer layer, and the ion implantation is performed on the substrate 10 to form the well region 101. In one embodiment of the present invention, the semiconductor device is, for example, a PMOS transistor, and the dopant ions in the well 101 are, for example, N-type dopant ions, and are, for example, phosphorus (P) or arsenic (As). In another embodiment of the present invention, the semiconductor device is, for example, an NMOS transistor, and the dopant ions in the well region 101 are, for example, P-type dopant ions, and are, for example, boron (B) or gallium (Ga) or the like. After the ion implantation, a rapid thermal annealing process (RAPID THERMAL ANNEAL, RTA) is performed on the well region 101, so that the ion implantation is diffused to a proper depth, and the avalanche breakdown resistance of the semiconductor device is improved. The pad oxide layer 11 is etched by wet etching, for example, and the etching liquid of the wet etching is hydrofluoric acid or buffered oxide etching liquid (Buffered Oxide Etch, BOE) or the like.

Referring to fig. 4 to 5, in an embodiment of the invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10, wherein the gate oxide layer 15 is, for example, a silicon oxide layer, and the gate oxide layer 15 is, for example, formed by an in-situ vapor growth method, and the thickness of the gate oxide layer 15 is, for example, 8a to 15 a. After forming the gate oxide layer 15, a first gate dielectric layer 16 is deposited on the gate oxide layer 15 and the shallow trench isolation structure 14, where the first gate dielectric layer 16 is, for example, one or more of hafnium oxide (HfO ₂), hafnium oxynitride (HfON), zirconium oxide (ZrO ₂), zirconium oxynitride (ZrON), zirconium oxynitride silicate (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitride silicate (HfSiON), hafnium lanthanum oxynitride (HfLaON) or hafnium aluminum oxide (HfAlO), and the first gate dielectric layer 16 has a thickness of, for example, 12a to 20 a. The first gate dielectric layer 16 may be formed by using, for example, an atomic layer deposition method (Atomic Layer Deposition, ALD), a Metal organic vapor deposition method (Metal-Organic Chemical Vapor Deposition, MOCVD), a Molecular beam epitaxy method (Molecular BeamEpitaxy, MBE), a chemical vapor deposition method, or a physical vapor deposition method (Physical Vapor Deposition, PVD), etc. By forming the gate oxide layer 15, the problem of poor interface quality between the first gate dielectric layer 16 and the substrate 10 can be improved, and the performance of the semiconductor device can be improved.

Referring to fig. 5, in an embodiment of the present invention, after forming the first gate dielectric layer 16, a second gate dielectric layer 17 is formed on the first gate dielectric layer 16, the second gate dielectric layer 17 is, for example, titanium nitride or titanium, and the second gate dielectric layer 17 is, for example, prepared by a method such as direct current magnetron sputtering or atomic layer deposition, and the thickness of the second gate dielectric layer 17 is, for example, 15 a to 25 a. By providing the second gate dielectric layer 17, the first gate dielectric layer 16 can be prevented from being polluted or damaged in the subsequent manufacturing process, and the performance of the subsequently manufactured metal gate can be improved. A gate material layer 18 is then formed on the second gate dielectric layer 17, the gate material layer 18 including, for example, an amorphous carbon nitrogen layer (α -CN) or the like. In this embodiment, the gate material layer 18 is prepared by a porous hollow cathode plasma enhanced chemical vapor deposition (HC-PECVD) technique, and the thickness of the gate material layer 18 is 50 nm-150 nm, and is selected according to the thickness of the final metal gate. Specifically, in the deposition chamber, the working pressure is 50 Pa-80 Pa, the working temperature is 500 ℃ to 700 ℃, the direct-current working voltage is 200V-800V, for example, nitrogen-containing gas, carbon-containing gas and carrier gas are introduced under the condition, wherein the nitrogen-containing gas comprises ammonia (NH ₃) or nitrogen (N ₂) and the like, The carbon-containing gas includes, for example, methane (CH ₄) or acetylene (C ₂H₂) or the like, and the carrier gas includes, for example, hydrogen (H ₂) for promoting the gas phase reaction, cleaning and purging the deposition chamber, ensuring deposition quality, and the like. In this embodiment, the total flow rate of the nitrogen-containing gas and the carrier gas is, for example, 1mL/min to 3mL/min, the volume ratio of the nitrogen-containing gas and the carrier gas is, for example, 1:7 to 1:9, and the flow rate of the carbon-containing gas is, for example, 1mL/min to 10mL/min. By controlling the deposition time, the thickness of the gate material layer 18 is controlled. In the embodiment, in the amorphous carbon-nitrogen layer, the atomic ratio of nitrogen atoms to carbon atoms is, for example, 15:85-20:80, so as to improve the thermal stability of the gate material layer 18, and meanwhile, the amorphous carbon-nitrogen layer has high hardness and good adhesion with the second gate dielectric layer 17, and is not easy to peel off in the manufacturing process, thereby ensuring the accuracy of the subsequently formed dummy gate. The smooth roughness of the surface of the gate material layer 18 is less than 1nm, so that the interface contact performance of the gate material layer 18 and other layers can be improved, the generation of defects is reduced in the manufacturing process, and the manufacturing yield is improved. By forming the amorphous carbon-nitrogen layer, the dense layer is high relative to the carbon layer, and the metallization or ionization of the dummy gate can be avoided in the subsequent manufacturing process, so that the high selection ratio and complete removal can be realized when the dummy gate is removed in the subsequent process, and the height of the metal gate is stabilized.

Referring to fig. 5, in an embodiment of the present invention, after forming the gate material layer 18, a hard mask layer is formed on the gate material layer 18, wherein the hard mask layer includes, for example, a first hard mask layer 19 and a second hard mask layer 20, the first hard mask layer 19 is disposed on the gate material layer 18, and the second hard mask layer 20 is disposed on the first hard mask layer 19. In this embodiment, the first hard mask layer 19 is, for example, a silicon nitride layer, and the thickness thereof is, for example, 15nm to 25nm, and the second hard mask layer 20 is, for example, a silicon oxide layer, and the thickness thereof is, for example, 25nm to 35nm. By providing two hard mask layers, the second hard mask layer 20 protects the first hard mask layer 19, so as to prevent the first hard mask layer 19 from being completely etched to cause the dummy gate to be etched when the sidewall structure, the heavily doped region or the contact hole etching stop layer and other structures are formed subsequently, and the second hard mask layer 20 can ensure the height of the dummy gate in the process before the dummy gate is removed, thereby ensuring the height of the metal gate and improving the height consistency of the subsequent metal gate.

Referring to fig. 5 to 6, in an embodiment of the invention, after the gate material layer 18 is formed, a second photoresist layer 21 is formed on the gate material layer 18, and then the second photoresist layer 21 is exposed and developed to remove the second photoresist layer 21 that needs to form the area except the dummy gate. The second hard mask layer 20, the first hard mask layer 19, the first gate dielectric layer 16 and the second gate dielectric layer 17 are then etched using the second photoresist layer 21 as a mask and the gate oxide layer 15 as an etch stop, for example by a dry etching process, a wet etching process or a combination of a dry etching process and a wet etching process, defining the remaining gate material layer 18 as a dummy gate 181.

Referring to fig. 6 to 7, in an embodiment of the present invention, after forming the dummy gate 181, lightly doped regions 22 are formed in the substrate 10 at both sides of the dummy gate 181. Wherein the doping ions of lightly doped region 22 are formed, for example, by ion implantation, and the implanted ion type is opposite to the ion type in well region 101. In the present embodiment, when the semiconductor device is a PMOS transistor, the doped ions in the lightly doped region 22 are P-type impurities such as boron or gallium, and when the semiconductor device is an NMOS transistor, the doped ions in the lightly doped region 22 are N-type impurities such as phosphorus or arsenic, and the lightly doped region 22 is formed to partially overlap the dummy gate during the process of implanting the doped ions.

Referring to fig. 7 to 8, in an embodiment of the invention, after forming the lightly doped region 22, sidewall structures 23 are formed on two sides of the dummy gate, wherein the sidewall structures 23 are, for example, stacked structures. In this embodiment, the sidewall structure 23 includes, for example, a first sub-layer 231, a second sub-layer 232, a third sub-layer 233 and a fourth sub-layer 234 stacked from a side near the dummy gate 181, where the first sub-layer 231 and the third sub-layer 233 are, for example, silicon nitride layers, and the second sub-layer 232 and the fourth sub-layer 234 are, for example, silicon oxide layers. By setting the first sub-layer 231 as a silicon nitride layer, in the process of forming the heavily doped region later, the situation that the side wall structure is broken in the patterning process can be reduced, and meanwhile, the stability of the side wall structure 23 after the dummy gate is removed can be improved. In other embodiments, the sidewall structures 23 are, for example, other stacked structures. By setting the sidewall structure 23 to a stacked structure, uniformity of the dummy gate is improved, thereby improving stability of the threshold voltage of the semiconductor device.

Referring to fig. 8 to 9, in an embodiment of the invention, after forming the sidewall structure 23, a heavily doped region 24 is formed in the substrate 10 on the side of the sidewall structure 23 away from the dummy gate 181, and an edge of the heavily doped region 24 is aligned with the side of the sidewall structure 23 away from the dummy gate 181. In which a region where the heavily doped region 24 is to be formed is exposed by a photoresist process, for example, the heavily doped region 24 is formed by ion implantation of doped ions, and the implanted ions are of the opposite type to the ions in the well region, i.e., the same type as the ions in the lightly doped region 22, and the doping concentration of the heavily doped region 24 is greater than the doping concentration of the lightly doped region 22. After formation of heavily doped region 24, heavily doped region 24 and lightly doped region 22 are activated, such as by rapid thermal annealing of substrate 10. By rapid thermal annealing, lattice defects generated during the fabrication process can be repaired and dopant ions activated, thereby activating heavily doped region 24 and lightly doped region 22. When the heavily doped region is formed, part of doped ions can enter the pseudo grid electrode, but amorphous carbon nitrogen cannot be ionized reversely, so that the etching rate is reduced in the removing process, the removing speed of the subsequent pseudo grid electrode is increased, the removing time is shortened, the etching amount of the side wall structure is further reduced, and the height of the metal grid electrode is easy to control.

Referring to fig. 8 to 9, in an embodiment of the present invention, after forming the heavily doped region 24, the gate oxide layer 15 is removed, for example, by etching, from the region except the sidewall structure 23 and the dummy gate 181, a metal layer (not shown) is formed on the entire structure on the substrate 10, the metal reacts with the exposed substrate 10 by heat treatment, a metal silicide layer 25 is formed on the heavily doped region 24, and the unreacted metal layer is removed, so that the contact resistance of the conductive plugs formed on the source and the drain is improved by the metal silicide layer 25. In the process of forming the heavily doped region, although the problem of cracking of the sidewall structure 23 is reduced, part of metal still enters the dummy gate 182 through the sidewall structure, and during heat treatment, the metal does not react with the gate material layer in the dummy gate 181 to cause metallization of the gate material layer, so that the gate material layer of the dummy gate can be ensured to be easily removed, and no residue exists. After the metal silicide layer 25 is formed, a contact hole etch stop layer 26 is formed on the substrate 10, the contact hole etch stop layer 26 being, for example, silicon nitride or the like. The contact hole etching stop layer 26 covers the side wall structure 23, the dummy gate 181, the metal silicide layer 25 and the shallow trench isolation structure 14, for example, so as to avoid affecting the stability of the side wall structure 23 or damaging the substrate 10 in the subsequent manufacturing process, thereby improving the performance of the semiconductor device.

Referring to fig. 9 to 10, in an embodiment of the present invention, after forming the contact hole etching stop layer 26, a dielectric layer 27 is formed on the substrate 10, where the dielectric layer 27 covers, for example, the dummy gate 181, the sidewall structure 23, the shallow trench isolation structure 14, the substrate 10, and the like. The dielectric layer 27 is, for example, silicon oxide, and is obtained by, for example, a chemical vapor deposition method or the like. In other embodiments, the dielectric layer 27 is made of silicon fluoride (SiF), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF), which is not limited in the present invention. After forming the dielectric layer 27, the dielectric layer 27 is planarized, for example, by chemical mechanical polishing to planarize the dielectric layer 27. In the polishing process, the first hard mask layer 19 is used as a polishing stop layer, non-selective polishing is adopted, polishing time is controlled, the dielectric layer 27, the contact hole etching stop layer 26 and the second hard mask layer 20 on the dummy gate 181 are removed, and after planarization treatment, the surface of the dielectric layer 27, the surface of the first hard mask layer 19 and the surface of the contact hole etching stop layer 26 are flush.

Referring to fig. 10 to 11, in an embodiment of the application, after the dielectric layer 27 is planarized, the first hard mask layer 19 is removed to expose the surface of the dummy gate 181, and at the same time, part of the dielectric layer 27, the contact hole etching stop layer 26 and the sidewall structure 23 are removed to make the dummy gate 181 flush with the structures on both sides. The first hard mask layer 19 is removed by etching or planarization, for example, and the present application is not limited thereto.

Referring to fig. 11 to 12, in an embodiment of the present invention, after removing the first hard mask layer 19, the dummy gate 181 is removed to form a recess 201 at the position of the dummy gate 181, and dry etching, wet etching or a combination of dry etching and wet etching may be used when removing the gate material layer. In this embodiment, the dummy gate 181 is removed by dry etching, for example, and the second gate dielectric layer 17 is used as an etching stop layer, and the etching gas includes, for example, an etching gas, a carrier gas, and the like. The etching gas includes, for example, a gas containing no oxygen atom such as hydrogen and nitrogen, the carrier gas is, for example, an inert gas such as argon, the total flow rate of the etching gas and the carrier gas is, for example, 60sccm to 80sccm, the flow rate of the carrier gas is, for example, 40sccm to 60sccm, the flow rate ratio of the nitrogen to the total flow rate of the nitrogen and the hydrogen is, for example, 0.2 to 0.3, and the ratio of the nitrogen in the immediate etching gas is, for example, 0.2 to 0.3. During etching, the pressure of the etching chamber is, for example, 12 mTorr-18 mTorr, the power of the top electrode is, for example, 150W-250W, and the DC bias voltage is, for example, 40V-60V. In the etching process, the etching gas does not contain oxygen atoms, so that the etching selection ratio of the gate material layer in the dummy gate 181 to the silicon-based material can be improved, in this embodiment, the etching selection ratio of the gate material layer, the silicon oxide and the silicon nitride is, for example, 10:1:1-8:1:1, and the etching selection ratio of the gate material layer to the silicon nitride and the silicon nitride is relatively large, thereby improving the etching selection ratio of the dummy gate 181 to the side wall structure 23 and the dummy gate 181 to the contact hole etching stop layer 26, reducing the loss of the side wall structure 23 to the contact hole etching stop layer 26, and effectively controlling the height of the subsequent metal gate. By controlling the DC bias voltage, the collimation of the plasma can be controlled, the removal of the grid electrode material layer in the pseudo grid electrode 181 can be effectively controlled, and meanwhile, the side wall structure 23 is not damaged in the removal process, so that the side wall structure is used as a side wall structure of a metal grid electrode prepared later, and the electrical property of a semiconductor device is improved.

Referring to fig. 12 and 13, in one embodiment of the present invention, after removing dummy gate 181, a plurality of metal work function layers and metal conductive layers (not shown) are deposited on dielectric layer 27 and on the bottom and sidewalls of recess 201, and the metal conductive layers are disposed on the plurality of metal work function layers until recess 201 is completely filled. The metal conductive layer and the metal work function layer are then planarized until they are flush with the surface of dielectric layer 27 to form metal gate 28. The material of the metal work function layer is one or a stack of tantalum nitride (TaN), titanium nitride (tin), titanium aluminide (TiAl), titanium aluminum nitride (TiAIN), tungsten nitride (WN), etc., and the metal work function layer is formed by a method such as a Plasma Enhanced Chemical Vapor Deposition (PECVD), atomic layer Deposition, or physical Vapor Deposition (pvd), etc. The number of layers and materials of the metal work function layer are selected according to the types of semiconductor devices so as to meet the threshold voltage requirements of different semiconductor devices. The metal conductive layer is made of metal materials with better conductivity, such as metal aluminum, tungsten, copper or silver, and the metal conductive layer is in a structure of single-layer metal, multi-layer metal or metal compound stack. After the metal gate 28 is formed, for example, conductive plugs, metal wiring layers, and the like are formed, which will not be described herein.

In summary, the present application provides a method for manufacturing a semiconductor device, which improves the method for manufacturing a semiconductor device, and the unexpected technical effect of the present application is to improve the thermal stability and adhesion of the gate material layer, so as to ensure the accuracy of the subsequently formed dummy gate. The defect generation in the manufacturing process can be reduced, and the manufacturing yield is improved. The metallization or ionization of the dummy gate can be avoided, so that in the subsequent process, high selectivity and complete removal can be realized when the dummy gate is removed, and the height of the metal gate is stabilized. The method can reduce the situation that the side wall structure is broken, improve the etching selection ratio of the pseudo grid electrode and the side wall structure, shorten the removal time, and further reduce the etching amount of the side wall structure, thereby being easy to control the height of the metal grid electrode, improving the height consistency of the metal grid electrode and improving the electrical property of the semiconductor device.

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.

The above description is only a preferred embodiment of the present application and the description of the technical principle applied, and it should be understood by those skilled in the art that the scope of the present application is not limited to the specific combination of the above technical features, but also covers other technical features formed by any combination of the above technical features or the equivalent features thereof without departing from the inventive concept, for example, the technical features disclosed in the present application (but not limited to) are replaced with technical features having similar functions. Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present application.

Claims

1. A method of fabricating a semiconductor device, comprising the steps of:

Forming side wall structures on two sides of the pseudo grid electrode;

Forming a metal silicide layer on the heavily doped region;

removing the pseudo grid electrode by dry etching to form a concave part; and

A metal gate is formed within the recess.

2. The method of manufacturing a semiconductor device according to claim 1, wherein an atomic ratio of nitrogen atoms to carbon atoms in the gate material layer is 15:85 to 20:80.

3. The method of manufacturing a semiconductor device according to claim 1, wherein a smooth roughness of a surface of the gate material layer is less than 1nm.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the dry etching gas includes an etching gas including hydrogen and nitrogen and a carrier gas including argon.

5. The method according to claim 4, wherein a total flow rate of the etching gas and the carrier gas is 60sccm to 80sccm, a flow rate of the carrier gas is 40sccm to 60sccm, and a ratio of nitrogen in the etching gas is 0.2 to 0.3.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the dc bias voltage of the dry etching is 40v to 60v.

7. The method of manufacturing a semiconductor device according to claim 1, wherein in the dry etching, an etching selection ratio of the gate material layer, the silicon oxide and the silicon nitride is 10:1:1 to 8:1:1.

8. The method of manufacturing a semiconductor device according to claim 1, further comprising: and forming a hard mask layer on the pseudo gate, wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer which are sequentially arranged on the pseudo gate.

9. The method of claim 8, wherein the first hard mask layer is a silicon nitride layer and the second hard mask layer is a silicon oxide layer.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the gate material layer is prepared by porous hollow cathode plasma enhanced chemical vapor deposition.