CN106527997A - NAND flash bad block reutilization method and device based on sequence expansion - Google Patents
NAND flash bad block reutilization method and device based on sequence expansion Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0617—Improving the reliability of storage systems in relation to availability
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention provides an NAND flash bad block reutilization method and device based on sequence expansion. The NAND flash bad block recycling method and device are used for solving the technical problems that through an existing bad block processing method, the utilization rate of a bad block is low, and adaptability is poor. The processing method comprises the steps that original test data is acquired; an initial sequence expansion code length L and a judgment threshold P are set; the original test data is subjected to sequence expansion; the data obtained after sequence expansion is written into a bad block; the data is read out of the bad block; the data read out of the bad block is subjected to de-expansion; the data obtained after de-expansion is recovered; whether the recovered data is consistent with the original test data or not is detected; if yes, reutilization of the bad block is realized; if not, n corresponding to L and P is changed into n+1, and the steps are repeated. The processing device comprises a data acquisition module, a sequence expansion module, a data writing-in module, a data reading-out module, a de-expansion module, a data recovery module and a data detection module. Through the NAND flash bad block reutilization method and device, the utilization rate of the bad block is high, the writing-in data volume of a flash memory is large, and the service life is long.
Description
Technical field
The invention belongs to communication technique field, is related to a kind of bad block recycling method of nand flash memory and device, especially relates to
And it is a kind of based on the bad block recycling method of nand flash memory and device that expand sequence, can be used for the storage such as USB flash disk and solid state hard disc and set
It is standby.
Background technology
Flash memory (Flash) is a kind of nonvolatile semiconductor memory chip, with small volume, it is low in energy consumption, be difficult by thing
The advantage of reason destruction, is the preferable storage medium of mobile digital product.
It is several that flash storage can be divided into AND, NAND, NOR and DiNOR etc. according to inside structure and the technology that implements
Kind, at present with nand flash memory as main flow memorizer.Nand flash memory has that capacity is big, small volume, low in energy consumption, random read-write performance
Well, the advantages of cost performance is high, so as to be widely applied.Nand flash memory from framework for be again divided into three kinds：SLC
(Single Level Cell), MLC (Multi Level Cell) and TLC (Triple Level Cell), due to MLC framves
Comprehensive advantage of the nand flash memory of structure at aspects such as speed, life-span and prices, has obtained generally adopting for industry.Nand flash memory
Basic unit of storage in technology is " page ", and some pages constitute a block, and block capacity is equal to the product of page capacity and number of pages in block,
In the block of different flash memories, number of pages is not quite similar, usually page 16～page 512.The programming of flash memory before writing must in units of page
First must wipe；Then in units of block, nand flash memory is made up of multiple pieces of serial arrangements for the erasing of flash memory.Nand flash memory is a kind of
Order read equipment, it only can just be accessed by page with the I/O ports of 8 or 16 bits in units of data.Nand flash memory exists
When reading with erasable continuous Large Copacity file, speed advantage is obvious, but speed is slow during random access memory, because it can not be by byte
Write.Nand flash memory easily produces bad block, and in the physical mechanism that bad block is damaged usually page, some bits can not be programmed, generally
It is 1 can not to be programmed to 0, it is discrete independent that it occurs bit-errors.If the bit number that can not be programmed in one page exceedes
During the ECC maximum checking features of chip setting, " bad block " will be referred to as and be abandoned.Such as magnesium light company
MT29F512G08 chips, its ECC check ability are 1100 byte error correction, 40 bit, i.e., when the mistake ratio in every 1100 byte
When special number is more than 40, this block will be identified as bad block and be not used, and cause substantial amounts of waste.
Two kinds are broadly divided into the processing method of bad block at present, are Shift Method and recycling method respectively.
Shift Method refers to that with a controller management bad block, when to bad block access data, controller will in design
Data are transferred to predetermined standby replacement region, complete to guarantee data security.Such as Chinese patent application, Authorization Notice No. is
CN103593301B, discloses a kind of bad block management method and system, including operating system performs the receive data from destination address
According to monitoring from the destination address data that read and inconsistent after comparing with the data of original write；By the destination address
The memory area of sensing is set to bad block region, and sets up replacement region corresponding with the bad block region；The data that will be stored
It is written in the replacement region.Although the method can ensure that the correct storage of data, but be thrown during realization completely
The bad block for still possessing most of normal memory cells has been abandoned, the waste of memory space has been caused.
Recycling method is referred to and bad block is utilized by related algorithm or instrument.Such as Chinese patent application, authorizes
Notification number is CN101859604B, discloses a kind of Application way of flash memory bad block, and the method is first by production tool software
Scanning flash memory, finds bad block therein and records in flash controller；The flash memory for finding to production tool software scans again is bad
Tuber is scanned again according to the screening conditions of " being available for utilizing " for being previously set, and the bad block for meeting screening conditions is labeled and remembers
Record waits to be used in flash controller；The bad block for not meeting screening conditions is then labeled as real bad block and is recorded in flash memory
In controller, do not use；The repetition scanning and labeling process are until all flash memory bad blocks are all labeled and record；Finally will
Meeting the bad block of the screening conditions of " be available for utilize " in flash memory, to be placed on replacement area etc. to be used.The invention using those can be
Special very small part in bad block to some data sensitives, that is, bad block, and the common bad block to being left to be in the great majority
Can only give it up., in the case where flash capacity is continuously increased, the flash memory space of waste will be increasing for this.Can
See, prior art is very poor using the adaptability of flash memory bad block, can not be adapted to all bad blocks, and finding one kind can be with unconfined
The method utilized to flash memory bad block is particularly important.
The content of the invention
It is an object of the invention to overcome the defect that above-mentioned prior art is present, it is proposed that a kind of based on the NAND for expanding sequence
Flash memory bad block recycling method and device, it is intended to improve the utilization rate of bad block, improve the bad adaptability of bad block recycling
Problem, extends the service life of nand flash memory.
To achieve these goals, the technical scheme taken of the present invention is：
Based on the bad block recycling method of nand flash memory for expanding sequence, comprise the following steps：
(1) data acquisition module will write the data of bad block in obtaining External memory equipment, obtain original test data；
(2) the initial length L for arranging despreading code sequence is 3, and decision threshold P is 2, and wherein L=2n-1, P=L-n+1, n are expansion
The exponent number of sequence code, and n >=2；
(3) expand block and utilize despreading code sequence, expansion sequence is carried out to original test data, obtain expanding data after sequence；
(4) after Data write. module will expand sequence, data are write in the bad block of nand flash memory；
(5) data read-out module reads the data in nand flash memory bad block, obtains treating despread data；
(6) despreading module treats despread data using despreading code sequence carries out despreading process, data after being de-spread；
(7) data recovery module is made decisions to every L bit datas successively according to decision threshold P, and be restored data；
(8) data detection module will recover data and original test data is compared, and whether judge two kinds of data
Unanimously, the recycling of bad block is if so, then realized, is terminated；If it is not, n is changed to n+1, execution step 3 then.
The above-mentioned bad block recycling method of nand flash memory based on expansion sequence, the acquisition external storage described in step 1 set
The data of bad block will be write in standby, will be obtained by direct memory access mode.
It is above-mentioned based on the bad block recycling method of nand flash memory for expanding sequence, data after the expansion sequence described in step 3 are
Step-by-step XOR is carried out by original test data and despreading code sequence and processes what is obtained, data after the despreading described in step 6 are logical
Cross and treat that despread data carries out step-by-step XOR with despreading code sequence and processes what is obtained.
The above-mentioned bad block recycling method of nand flash memory based on expansion sequence, the bad block are referred to beyond flash controller
The flash block of ECC error correction scope.
The above-mentioned bad block recycling method of nand flash memory based on expansion sequence, step 1～step 8 are all based on FPGA realities
Existing.
It is above-mentioned based on expand sequence the bad block recycling method of nand flash memory, described in step 7 to every L bit datas according to
Secondary to make decisions, its decision method is that, if having P or more than P 1 in per L bit datas, it is 1 to recover data, if there is P
Individual or individual more than P 0, then it is 0 to recover data.
It is above-mentioned based on the bad block recycling method of nand flash memory for expanding sequence, data and original will be recovered described in step 8
Beginning test data is compared, and refers to that will recover data and original test data carries out step-by-step XOR process, and to result
It is analyzed realization.
It is a kind of based on expand sequence the bad block reusing device of nand flash memory, it is characterised in that including data acquisition module,
Expand block, Data write. module, data read-out module, despreading module, data recovery module and detection module, wherein,
Data acquisition module, for obtaining the original test data in External memory equipment；
Expand block, expansion sequence is carried out to the data that will write bad block for the despreading code sequence by length for L；
Data write. module, is written in corresponding nand flash memory bad block for will expand data after sequence；
Data read-out module, for reading data after the expansion sequence in bad block；
Despreading module, the despreading code sequence for the data to reading from bad block by same length for L are carried out at despreading
Reason；
Data recovery module, for the data after despreading are carried out data recovery；
Whether data detection module is consistent with original test data for detecting recovery data.
The present invention compared with prior art, has the advantage that.
The present invention is due to existing in nand flash memory in the case that bad block can not be utilized, bad by writing nand flash memory
The data of block are write after carrying out expansion sequence again, through follow-up despreading process and data recovery, can be realized to all in theory
Reuse more than the nand flash memory bad block of flash controller ECC check ability, extend the available storage of nand flash memory,
The write data volume of nand flash memory is increased, the utilization rate of flash memory bad block compared with prior art, is improve, bad block weight is improved
The problem of the bad adaptability for utilizing again, so as to reduce the number of times of nand flash memory erasing, and then extends the use of nand flash memory
Life-span.
Description of the drawings
Fig. 1 is that the present invention realizes FB(flow block) based on the nand flash memory bad block recycling method for expanding sequence；
Fig. 2 is structural representation of the present invention based on the bad block reusing device of nand flash memory for expanding sequence；
Fig. 3 is the operating diagram for expanding block and Data write. module in Fig. 2 embodiments during n=2；
Fig. 4 is the despreading module and data recovery module operating diagram in Fig. 2 embodiments during n=2；
Fig. 5 is data detection module operation principle schematic diagram in Fig. 2 embodiments.
Specific embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail；
It is with reference to Fig. 1, a kind of based on the bad block recycling method of nand flash memory for expanding sequence, comprise the following steps：
Step S10, obtains original test data；
MT29F512G08 of the nand flash memory chip using magnesium light company in the present embodiment, per page of the chip are 16K+1216
Byte, each block are constituted by page 512, and size is 8192K+608K bytes, and chip total capacity is 512Gb.
In the present embodiment, obtain original test data and refer to, the data of bad block in obtaining External memory equipment, will be write,
One section is intercepted, as original test data；As the every page of size of flash memory in the present embodiment is 16K, so selecting to intercept
(16/L) data of K bytes, as original test data so when despreading code sequence length is L, after expanding series processing
Write data become 16K, and just one page, facilitates data to write.
In the present embodiment, External memory equipment is the such as desktop computer of the electronic equipment with memory space.Specifically, can pass through
PCI-e interfaces are by way of direct memory access by the caching of the data transfer stored in desktop computer to FPGA；In directly
Deposit access refer to external equipment not by CPU directly with Installed System Memory exchange data, data reading speed is fast, efficiency high；
Step S11, arranges initial despreading code sequence length L and decision threshold P；
In the present embodiment, initial despreading code sequence length L is set to into 3, decision threshold P is set to 2, and wherein despreading code sequence is long
Degree L=2n-1, decision threshold P=L-n+1, n >=2；Length is that 3 despreading code sequence adopts 110 sequences, and this despreading code sequence is 2 ranks
Pseudo noise code, length are that 5 despreading code sequence adopts 10011 sequences, shortened code of this yard for 3 rank pseudo noise codes；Sequence will initially be expanded
Row code length L is set to 3 decision threshold P and is set to 2, is because so can both having solved in bad block discrete single-bit error and can
With the increase write data volume of maximal efficiency；When despreading code sequence length is 3, the data volume that is written efficiently into of bad block is changed into original bad
/ 3rd of block size, with should despreading code sequence length be L when, the data volume that is written efficiently into of bad block is changed into original bad block size
L/mono-；Using pseudo-random sequence, despreading code sequence is because that pseudo-random sequence has good randomness and balance；
Step S12, carries out expansion series processing with the despreading code sequence that length is L to original test data；
In the present embodiment, it is that original test data carries out step-by-step XOR with despreading code sequence to expand series processing；
In the present embodiment, expand the specific works schema reference Fig. 3 top half of series processing；
Step S13, by the bad block of the data write nand flash memory expanded after sequence；
Bad block described in the present embodiment refers to the nand flash memory bad block beyond ECC check ability, whether right as bad block
Which data sensitive present invention is without restriction；ECC (Error Correcting Code) is a kind of data error detection error correction algorithm,
Code is compiled to data storage by way of increasing redundant data, for solving to there is a small amount of bit reversal in nand flash memory
Problem；Refer to more than ECC check ability, the ECC check of each flash controller has maximum error correcting capability, such as the present embodiment
In ECC error correction ability be exactly 40 bit of every 1100 byte error correction, i.e., when the error bit number in 1100 bytes is more than 40, this
Individual block is just identified as bad block；
In the present embodiment, data write is to realize nand flash memory interface write timing by FPGA, will expand the data after sequence
In the bad block of write nand flash memory.It should be noted that should wipe to the bad block before data write, bad block is kept
In normal bit be all one state, as shown in Fig. 3 fourth lines；In the present embodiment, block erasing operation needs 3 address cycles, first
First command word 60H is wiped by FPGA transmission blocks first, the block address of the needs erasing in 3 cycles is then sent, is finally sent
Second command word D0H of block erasing；Data write operation needs 5 address cycles, sends data write the by FPGA first
One command word 80H, then sends address in the block in 5 cycles, then sends 16K data to be written, finally sends data and writes
Second command word 10H for entering；
In the present embodiment, the specific works schema reference Fig. 3 the latter half of data write；
Step S14, data is read from the bad block, obtains treating despread data；
In the present embodiment, data read-out is to realize nand flash memory interface readout sequence by FPGA, by data from nand flash memory
Bad block in read；Data read-out operation in the present embodiment needs 5 address cycles, is sent the of data read-out first by FPGA
One command word 00H, then sends address in the block of 5 address cycles, finally sends second command word of data read-out
30H；
Step S15, will treat that despread data despreading code sequence carries out despreading process；
In the present embodiment, it is that data to be de-spread are carried out step-by-step XOR process with former despreading code sequence that despreading is processed；
In the present embodiment, the specific works schema reference Fig. 4 top half for processing is de-spread；
Data after despreading are carried out data recovery by step S16；
In the present embodiment, despreading code sequence length L is 3, and decision threshold P is 2, the specific works schema reference figure of data recovery
4 the latter half；
Step S17, whether detection recovers data consistent with original test data；
In the present embodiment, Data Detection is by former data and recovery data are carried out step-by-step XOR, if in as a result
There is 1 appearance then to illustrate that recovery data and original test data are incomplete same, illustrate that this expands the fault-tolerant ability of sequence method also not
Can need to change a bigger expansion sequence method of fault-tolerant ability for reusing bad block；If there is no 1 appearance, number is illustrated
Correct according to read-write, this fault-tolerant ability for expanding sequence solution can be reused to bad block；
In the present embodiment, specific works schema reference Fig. 5 of Data Detection；
In the present embodiment, Data Detection is used carries out step-by-step XOR process with data are recovered by original test data,
Testing result is obtained by analysis processing result；Should appreciate that and subtract each other and can also reach with data are recovered by original test data
Said function, it is also within the scope of the present invention using other similar operations in order to reach Data Detection；
N corresponding with despreading code sequence length L and decision threshold P is changed to n+1 by step S18；
In the present embodiment, when step S17 has problems, there are continuous 2 bit-errors in illustrating nand flash memory bad block, initially
In the case of expansion sequence method can not evade continuous 2 bit-errors, sequence length increase should be expanded, and corresponding decision gate is changed
Limit value so as to which fault-tolerant ability is higher.When n is 2, the fault-tolerant ability of the bad block recycling method of this nand flash memory is 1 bit, is held
Wrong ability is embodied in L-P, and with the increase of n, fault-tolerant ability is also increasing；
With reference to Fig. 2, a kind of bad block reusing device of nand flash memory based on expansion sequence, including data acquisition module
B100, expansion block B101, Data write. module B102, data read-out module B103, despreading module B104, data recovery mould
Block B105 and data detection module B106；Wherein modules are ordered into linking together, be connected with each other order can not overturn and
Replace；
Data acquisition module B100, for obtaining the data that bad block will be write in External memory equipment；
In the present embodiment, FPGA is by way of PCI-e interface direct memory access by the data stored in desktop computer
Transmit into the data register of FPGA；
Expand block B101, the data to obtaining from External memory equipment are expanded with the despreading code sequence that length is L
Series processing；
Expand sequence and refer to the operation that initial data is expanded by corresponding computing by using sequence length, in the present embodiment, expand
Series processing is that source data carries out step-by-step XOR with despreading code sequence；
Data write. module B102, in the bad block for the data write nand flash memory that will expand after sequence；
Data write. module is referred to and is required according to the corresponding time sequence of chip by certain instrument, write data into and store single
In unit；In the present embodiment, data write is to realize nand flash memory interface write timing by FPGA, and the data expanded after sequence are write
Enter in the bad block of nand flash memory.It should be noted that the bad block should be wiped before data write, in keeping bad block
Normal memory cell be all one state；
Data read-out module B103, data to be written are read from the bad block；
Data read-out module is referred to and is required according to the corresponding time sequence of chip by certain instrument, by data from memory element
Read；In the present embodiment, data read-out is to realize nand flash memory interface readout sequence by FPGA, by data from nand flash memory
Read in bad block.
Despreading module B104, for will treat that despread data carries out despreading process with the despreading code sequence that same length is L；
The algorithm that data de-spreading operation expands series of operations with data is identical, and expansion sequence is also identical；In the present embodiment,
It is that data to be de-spread are carried out step-by-step XOR process with former despreading code sequence that despreading is processed；
Data recovery module B105, for the data after despreading are carried out data recovery；
Data recovery refers to and former data is made decisions by certain recovery standard that be restored data；In the present embodiment,
When despreading code sequence length L is 3, and decision threshold P is 2, data recovery is made decisions to every 3 bit data successively, if there is 2
Or more than 21 appearance, then it is 1 to recover initial data；If there is 2 or more than 20 appearance, it is 0 to recover initial data；
Data detection module B106, whether detection recovers data consistent with original test data；
Data Detection refers to that by related operation analytic operation result draws judged result；In the present embodiment, comparing
Be by former data and the data that recover are carried out step-by-step XOR process, as a result in illustrate to recover data if having 1 appearance
It is incomplete same with initial data, illustrate that this fault-tolerant ability for expanding sequence solution can't need to change for processing this bad block
The bigger expansion sequence solution of one fault-tolerant ability；If there is no 1 appearance, illustrate that reading and writing data is correct；
In the present embodiment, when B106 detections are gone wrong, in illustrating nand flash memory, there are continuous 2 bit-errors, initial situation
Under expansion sequence pattern can not evade continuous 2 bit-errors, despreading code sequence length should be increased, and change corresponding decision threshold
Value so as to which fault-tolerant ability strengthens；
With reference to Fig. 3, the operating diagram for expanding block and Data write. module when being n=2 in Fig. 2 embodiments, its
In；
The first row represents original test data, in the present embodiment, by the data cutout 16/3K obtained in External memory equipment
One section of size is used as original test data；
Second row represents the despreading code sequence that despreading code sequence length L is as 3, from 110 sequences as initial expansion in the present embodiment
Sequence code；
The third line is the data after the expansion sequence obtained after original test data carries out step-by-step XOR process with despreading code sequence,
Wherein original test data is 16/3K sizes, and despreading code sequence length L is 3, so size of data is 16K after the expansion sequence for obtaining,
The size of flash memory one page exactly in the present embodiment；
Fourth line simulates the memory element in nand flash memory, and wherein each square frame represents a memory element, runic side
Frame is represented and can not be programmed that error bit；
Fifth line be expand sequence after data write bad block in state, it is seen that except other normal memory cells of error bit
Data because data write and change；
With reference to Fig. 4, the despreading module and data recovery module operating diagram when being n=2 in Fig. 2 embodiments, wherein；
The first row represents that what is read from bad block treats despread data；
Second row represents initial despreading code sequence during data expansion series of operations；
The third line represents data after the despreading obtained after despread data carries out step-by-step xor operation with despreading code sequence；
Fourth line represents the recovery data after data recovery, and to data after the despreading in the third line, every 3 bit data is carried out
Judgement, if 2 or more than 2 is 1, then it is 1 to recover data.If 2 or 2 data above are 0, then recover data
For 0, the size of the recovery data for obtaining is 1/3rd of data after despreading；
With reference to Fig. 5, it is data detection module operation principle schematic diagram in Fig. 2 embodiments, wherein；
The first row represents original test data；
Second row represents the recovery data obtained through data recovery；
The third line represents the testing result that original test data and recovery data are obtained after carrying out step-by-step XOR, shows full 0
Then represent that original test data is identical with data are recovered, it was demonstrated that the read-write to bad block is completely correct, if having 1 in testing result
Occur, then it represents that reading and writing data goes wrong；
The preferred embodiments of the present invention are these are only, is not thereby limited the scope of the invention, it is every using this
Equivalent structure and equivalent flow conversion that bright description and accompanying drawing content are done, or directly or indirectly it is used in other related skills
Art field, includes within the scope of the present invention in the same manner.
Claims (8)
1. it is a kind of based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that to comprise the following steps：
(1) data acquisition module will write the data of bad block in obtaining External memory equipment, obtain original test data；
(2) the initial length L for arranging despreading code sequence is 3, and decision threshold P is 2, and wherein L=2n-1, P=L-n+1, n are expansion sequence
The exponent number of code, and n >=2；
(3) expand block and utilize despreading code sequence, expansion sequence is carried out to original test data, obtain expanding data after sequence；
(4) after Data write. module will expand sequence, data are write in the bad block of nand flash memory；
(5) data read-out module reads the data in nand flash memory bad block, obtains treating despread data；
(6) despreading module treats despread data using despreading code sequence carries out despreading process, data after being de-spread；
(7) data recovery module is made decisions to every L bit datas successively according to decision threshold P, and be restored data；
(8) data detection module will recover data and original test data is compared, and judge whether two kinds of data are consistent,
If so, the recycling of bad block is then realized, is terminated；If it is not, n is changed to n+1, execution step 3 then.
2. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that step
The data of bad block will be write in acquisition External memory equipment described in 1, will be obtained by direct memory access mode.
3. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that step
Data after expansion sequence described in 3, carry out the process of step-by-step XOR by original test data and despreading code sequence and obtain, step
Data after despreading described in 6, are obtained by treating that despread data and despreading code sequence carry out the process of step-by-step XOR.
4. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that described
Bad block, refers to the flash block beyond flash controller ECC error correction scope.
5. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that step
1～step 8, is all based on FPGA realizations.
6. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that step
Made decisions to every L bit datas successively described in 7, its decision method is, if having P in per L bit datas or more than P
1, then it is 1 to recover data, if there is P or more than P 0, it is 0 to recover data.
7. it is according to claim 1 based on the bad block recycling method of nand flash memory for expanding sequence, it is characterised in that step
To recover data and original test data described in 8 is compared, refer to will recover data and original test data carry out by
Position XOR is processed, and is analyzed realization to result.
8. it is a kind of based on the bad block reusing device of nand flash memory for expanding sequence, it is characterised in that including data acquisition module, to expand
Block, Data write. module, data read-out module, despreading module, data recovery module and detection module, wherein,
Data acquisition module, for obtaining the original test data in External memory equipment；
Expand block, expansion sequence is carried out to the data that will write bad block for the despreading code sequence by length for L；
Data write. module, is written in corresponding nand flash memory bad block for will expand data after sequence；
Data read-out module, for reading data after the expansion sequence in bad block；
Despreading module, the despreading code sequence for the data to reading from bad block by same length for L carry out despreading process；
Data recovery module, for the data after despreading are carried out data recovery；
Whether data detection module is consistent with original test data for detecting recovery data.
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