CN110570898A - Method and device for detecting data processing speed of memory - Google Patents
Method and device for detecting data processing speed of memory Download PDFInfo
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- CN110570898A CN110570898A CN201910745761.2A CN201910745761A CN110570898A CN 110570898 A CN110570898 A CN 110570898A CN 201910745761 A CN201910745761 A CN 201910745761A CN 110570898 A CN110570898 A CN 110570898A
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Abstract
the invention relates to a method and a device for detecting the data processing speed of a memory, wherein the method comprises the following steps: performing data processing operation on a target data block according to a first processing speed to obtain a first bad block area generated in the target data block; improving the data processing speed of the target data block, performing data processing operation on the target data block according to a second processing speed, and acquiring a second bad block area generated after the data processing operation is performed on the target data block; and judging whether the first bad block area and the second bad block area are different, and if so, taking the second processing speed as the highest data processing speed of the memory. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a method and an apparatus for detecting a data processing speed of a memory.
background
the application of the memory is more and more extensive, the memory with various read-write speeds is filled in the market, the corresponding memory is customized according to different products, the cost is higher, the read-write speed test of the manufactured memory cannot be carried out, and the corresponding product is matched according to the measured result, so that a device capable of detecting the read-write speed of the memory is needed, the speed of the manufactured memory is measured, the highest read-write speed of the memory is measured, the corresponding product is matched according to the measured result, and the manufacturing cost is saved.
disclosure of Invention
In order to solve the above technical problem, the present application provides a method and an apparatus for detecting a data processing speed of a memory.
in a first aspect, the present application provides a method for detecting a data processing speed of a memory, the method comprising:
Extracting a target data block from a memory;
performing data processing operation on the target data block according to a first processing speed in a fixed time period,
Acquiring a first bad block area generated in the fixed time period in the target data block;
increasing the data processing speed of the target data block to a second processing speed,
Performing data processing operation on the target data block for a fixed time period according to a second processing speed,
acquiring a second bad block area generated after the target data block is subjected to data processing operation according to a second processing speed in a fixed time period;
judging whether the first bad block area and the second bad block area are different,
when the first bad block area and the second bad block area have difference, the second processing speed is taken as the highest data processing speed of the memory;
wherein, the data processing operation sequence is data erasing, data writing and data reading.
Preferably, the method further comprises:
And when the first bad block area and the second bad block area have no difference, increasing the data processing speed of the target data block to a third processing speed.
preferably, the extracting the target data block from the memory includes:
extracting three data blocks with bits from a memory as target data blocks, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to a physical address, an end data block which is positioned in the memory and distributed according to the physical address, and a middle data block which is positioned between the first data block and the end data block.
preferably, the intermediate data block located between the first data block and the last data block includes:
And when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
Preferably, the intermediate data block located between the first data block and the last data block includes:
and when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
in a second aspect, the present application provides an apparatus for detecting a data processing speed of a memory, the apparatus comprising:
the data block acquisition module is used for extracting a target data block from the memory;
the data reading and writing module is used for carrying out data processing operation on the target data block according to a first processing speed in a fixed time period;
A first bad block area obtaining module, configured to obtain a first bad block area generated in the target data block within the fixed time period;
The speed-up module is used for increasing the data processing speed of the target data block to a second processing speed;
The processing module is used for carrying out data processing operation of a fixed time period on the target data block according to a second processing speed;
a second bad block area obtaining module, configured to obtain a second bad block area generated after the target data block performs data processing operation at a second processing speed within a fixed time period;
The judging module is used for judging whether the first bad block area and the second bad block area are different;
And the stopping module is used for taking the second processing speed as the highest data processing speed of the memory when the first bad block area and the second bad block area have difference.
preferably, the apparatus further comprises:
and the secondary speed-up module is used for increasing the data processing speed of the target data block to a third processing speed when the first bad block area and the second bad block area have no difference.
Preferably, the data block obtaining module includes:
The data block acquisition unit is used for extracting three data blocks as target data blocks from a memory, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to physical addresses, an end data block which is positioned in the memory and distributed according to physical addresses, and a middle data block which is positioned between the first data block and the end data block.
preferably, the intermediate data block includes:
and when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
preferably, the intermediate data block includes:
and when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
The invention has the beneficial effects that:
the invention discloses a method and a device for detecting the data processing speed of a memory, wherein the method comprises the following steps: extracting a target data block from a memory; in a fixed time period, performing data processing operation on the target data block according to a first processing speed, wherein the data processing operation sequence comprises data erasing, data writing and data reading, and acquiring a first bad block area generated in the target data block in the fixed time period; increasing the data processing speed of the target data block to a second processing speed, performing data processing operation on the target data block for a fixed time period according to the second processing speed, and acquiring a second bad block area generated after the data processing operation is performed on the target data block for the fixed time period according to the second processing speed; and judging whether the first bad block area is different from the second bad block area, and when the first bad block area is different from the second bad block area, taking the second processing speed as the highest data processing speed of the memory. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a flow diagram illustrating a method for detecting a processing speed of memory data according to one embodiment;
FIG. 2 is a flow diagram illustrating a method for detecting memory re-boosting data processing speed in one embodiment;
FIG. 3 is a flowchart illustrating a method for detecting processing speeds of three target blocks of data according to one embodiment;
FIG. 4 is a block diagram of an apparatus for detecting a processing speed of memory data according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic flowchart of a method for detecting a data processing speed of a memory according to an embodiment of the present invention, and in an embodiment of the present invention, referring to fig. 1, the present application provides a method for detecting a data processing speed of a memory, where the method includes:
S101, extracting a target data block from a memory;
S102, in a fixed time period, carrying out data processing operation on the target data block according to a first processing speed,
s103, acquiring a first bad block area generated in the target data block within the fixed time period;
s104, increasing the data processing speed of the target data block to a second processing speed,
S105, performing data processing operation on the target data block according to a second processing speed for a fixed time period,
s106, acquiring a second bad block area generated after the target data block is subjected to data processing operation according to a second processing speed in a fixed time period;
s107, judging whether the first bad block area and the second bad block area are different,
s108, when the difference exists between the first bad block area and the second bad block area, taking the second processing speed as the highest data processing speed of the memory;
wherein, the data processing operation sequence is data erasing, data writing and data reading.
The invention discloses a method for detecting the data processing speed of a memory, which comprises the following steps: extracting a target data block from a memory; in a fixed time period, performing data processing operation on the target data block according to a first processing speed, wherein the data processing operation sequence comprises data erasing, data writing and data reading, and acquiring a first bad block area generated in the target data block in the fixed time period; increasing the data processing speed of the target data block to a second processing speed, performing data processing operation on the target data block for a fixed time period according to the second processing speed, and acquiring a second bad block area generated after the data processing operation is performed on the target data block for the fixed time period according to the second processing speed; and judging whether the first bad block area is different from the second bad block area, and when the first bad block area is different from the second bad block area, taking the second processing speed as the highest data processing speed of the memory. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
fig. 2 is a schematic flowchart of a method for detecting that a memory increases a data processing speed again in an embodiment, and in an embodiment of the present invention, referring to fig. 2, after step S107, the method further includes:
and S109, when the first bad block area and the second bad block area have no difference, increasing the data processing speed of the target data block to a third processing speed.
Fig. 3 is a flowchart illustrating a method for detecting processing speeds of three target data blocks in an embodiment of the present invention, and in an embodiment of the present invention, referring to fig. 3, the method includes:
s201, extracting three data blocks of bits from a memory as target data blocks, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to a physical address, an end data block which is positioned in the memory and distributed according to the physical address, and a middle data block which is positioned between the first data block and the end data block;
s202, in a fixed time period, carrying out data processing operation on the target data block according to a first processing speed,
s203, acquiring a first bad block area generated in the target data block within the fixed time period;
s204, improving the data processing speed of the three target data blocks,
S205, carrying out data processing operation for the three target data blocks for a fixed time period according to the accelerated processing speed,
S206, obtaining a bad block area generated after the target data block is subjected to data processing operation according to the accelerated processing speed in a fixed time period;
s207, judging whether the bad block area generated before the speed is increased is different from the bad block area generated after the speed is increased,
s208, when the bad block area generated before the speed is increased is different from the bad block area generated after the speed is increased, taking the processing speed after the speed is increased as the highest data processing speed of the memory;
Wherein, the data processing operation sequence is data erasing, data writing and data reading.
in this embodiment of the present invention, the intermediate data block located between the first data block and the last data block includes:
and when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
In this embodiment of the present invention, the intermediate data block located between the first data block and the last data block includes:
and when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
fig. 4 is a schematic structural diagram of an apparatus for detecting a memory data processing speed according to an embodiment of the present invention, and referring to fig. 4, the present application provides an apparatus for detecting a memory data processing speed, where the apparatus includes:
A data block acquiring module 101, configured to extract a target data block from a memory;
A data reading and writing module 201, configured to perform data processing operation on the target data block at a first processing speed in a fixed time period;
A first bad block area obtaining module 301, configured to obtain a first bad block area generated in the target data block within the fixed time period;
A speed-up module 401, configured to increase a data processing speed of the target data block to a second processing speed;
a processing module 501, configured to perform a data processing operation on the target data block for a fixed time period according to a second processing speed
A second bad block area obtaining module 601, configured to obtain a second bad block area generated after the target data block performs data processing operation at a second processing speed in a fixed time period;
A determining module 701, configured to determine whether the first bad block area and the second bad block area are different;
a stopping module 801, configured to use the second processing speed as a highest data processing speed of the memory when there is a difference between the first bad block area and the second bad block area.
the invention discloses a device for detecting the data processing speed of a memory, which comprises: a data block acquiring module 101, configured to extract a target data block from a memory; a data reading and writing module 201, configured to perform data processing operation on the target data block at a first processing speed in a fixed time period; a first bad block area obtaining module 301, configured to obtain a first bad block area generated in the target data block within the fixed time period; a speed-up module 401, configured to increase a data processing speed of the target data block to a second processing speed; a processing module 501, configured to perform data processing operation on the target data block at a second processing speed for a fixed time period, and a second bad block region obtaining module 601, configured to obtain a second bad block region generated after the target data block performs data processing operation at the second processing speed within the fixed time period; a determining module 701, configured to determine whether the first bad block area and the second bad block area are different; a stopping module 801, configured to use the second processing speed as a highest data processing speed of the memory when there is a difference between the first bad block area and the second bad block area. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
in an embodiment of the present invention, the apparatus further includes:
And the secondary speed-up module is used for increasing the data processing speed of the target data block to a third processing speed when the first bad block area and the second bad block area have no difference.
in an embodiment of the present invention, the data block obtaining module includes:
The data block acquisition unit is used for extracting three data blocks as target data blocks from a memory, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to physical addresses, an end data block which is positioned in the memory and distributed according to physical addresses, and a middle data block which is positioned between the first data block and the end data block.
in an embodiment of the present invention, the intermediate data block includes:
and when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
in an embodiment of the present invention, the intermediate data block includes:
and when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
the invention discloses a method and a device for detecting the data processing speed of a memory, wherein the method comprises the following steps: extracting a target data block from a memory; in a fixed time period, performing data processing operation on the target data block according to a first processing speed, wherein the data processing operation sequence comprises data erasing, data writing and data reading, and acquiring a first bad block area generated in the target data block in the fixed time period; increasing the data processing speed of the target data block to a second processing speed, performing data processing operation on the target data block for a fixed time period according to the second processing speed, and acquiring a second bad block area generated after the data processing operation is performed on the target data block for the fixed time period according to the second processing speed; and judging whether the first bad block area is different from the second bad block area, and when the first bad block area is different from the second bad block area, taking the second processing speed as the highest data processing speed of the memory. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
the device comprises: a data block acquiring module 101, configured to extract a target data block from a memory; a data reading and writing module 201, configured to perform data processing operation on the target data block at a first processing speed in a fixed time period; a first bad block area obtaining module 301, configured to obtain a first bad block area generated in the target data block within the fixed time period; a speed-up module 401, configured to increase a data processing speed of the target data block to a second processing speed; a processing module 501, configured to perform data processing operation on the target data block at a second processing speed for a fixed time period, and a second bad block region obtaining module 601, configured to obtain a second bad block region generated after the target data block performs data processing operation at the second processing speed within the fixed time period; a determining module 701, configured to determine whether the first bad block area and the second bad block area are different; a stopping module 801, configured to use the second processing speed as a highest data processing speed of the memory when there is a difference between the first bad block area and the second bad block area. Whether the bad block area generated by the target data block at the slow speed is different from the bad block area generated by the target data block after the speed is increased or not is judged, whether the memory can bear the operation speed after the speed is increased or not can be known, the highest data processing speed of the memory is obtained, the memory is matched with a product corresponding to the data processing speed, and the formulation cost is saved.
The data blocks at three positions in the memory are acquired as target data blocks, whether the bad block area generated by the three target data blocks at a low speed is different from the bad block area generated after the speed is increased is judged, the test result of the data blocks at different physical positions is avoided being different, the highest data processing speed of the memory can be obtained through the test, the memory is matched with a product with the corresponding required data processing speed, the product is matched with the memory with the overhigh or overlow processing speed, the memory with the overhigh processing speed is matched with the product, the data processing capacity of the memory is wasted, the memory with the overlow processing speed cannot complete normal work operation, the memory consumes higher manufacturing cost when the product is made, and the problems can be solved through the method disclosed by the invention, the effect of saving the manufacturing cost is achieved.
Fig. 1 is a flowchart illustrating a method for detecting a data processing speed of a memory according to an embodiment, fig. 2 is a flowchart illustrating a method for detecting a data processing speed of a memory according to an embodiment, and fig. 3 is a flowchart illustrating a method for detecting a data processing speed of three target data blocks according to an embodiment. It should be understood that although the various steps in the flowcharts of fig. 1-3 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-3 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
it is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
the foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. a method of detecting a memory data processing speed, the method comprising:
extracting a target data block from a memory;
performing data processing operation on the target data block according to a first processing speed in a fixed time period,
acquiring a first bad block area generated in the fixed time period in the target data block;
increasing the data processing speed of the target data block to a second processing speed,
Performing data processing operation on the target data block for a fixed time period according to a second processing speed,
acquiring a second bad block area generated after the target data block is subjected to data processing operation according to a second processing speed in a fixed time period;
Judging whether the first bad block area and the second bad block area are different,
when the first bad block area and the second bad block area have difference, the second processing speed is taken as the highest data processing speed of the memory;
wherein, the data processing operation sequence is data erasing, data writing and data reading.
2. the method of claim 1, further comprising:
and when the first bad block area and the second bad block area have no difference, increasing the data processing speed of the target data block to a third processing speed.
3. the method of claim 2, wherein the extracting the target data block from the memory comprises:
extracting three data blocks with bits from a memory as target data blocks, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to a physical address, an end data block which is positioned in the memory and distributed according to the physical address, and a middle data block which is positioned between the first data block and the end data block.
4. the method of claim 3, wherein the intermediate data block located between the first data block and the last data block comprises:
And when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
5. The method of claim 3, wherein the intermediate data block located between the first data block and the last data block comprises:
And when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
6. an apparatus for detecting a data processing speed of a memory, the apparatus comprising:
The data block acquisition module is used for extracting a target data block from the memory;
the data reading and writing module is used for carrying out data processing operation on the target data block according to a first processing speed in a fixed time period;
A first bad block area obtaining module, configured to obtain a first bad block area generated in the target data block within the fixed time period;
the speed-up module is used for increasing the data processing speed of the target data block to a second processing speed;
the processing module is used for carrying out data processing operation of a fixed time period on the target data block according to a second processing speed;
A second bad block area obtaining module, configured to obtain a second bad block area generated after the target data block performs data processing operation at a second processing speed within a fixed time period;
the judging module is used for judging whether the first bad block area and the second bad block area are different;
and the stopping module is used for taking the second processing speed as the highest data processing speed of the memory when the first bad block area and the second bad block area have difference.
7. The apparatus of claim 6, further comprising:
and the secondary speed-up module is used for increasing the data processing speed of the target data block to a third processing speed when the first bad block area and the second bad block area have no difference.
8. The apparatus of claim 6, wherein the data block obtaining module comprises:
The data block acquisition unit is used for extracting three data blocks as target data blocks from a memory, wherein the three data blocks comprise a first data block which is positioned in the memory and distributed according to physical addresses, an end data block which is positioned in the memory and distributed according to physical addresses, and a middle data block which is positioned between the first data block and the end data block.
9. the apparatus of claim 8, wherein the intermediate data block comprises:
and when the number of the data blocks in the memory is odd, selecting the data block positioned in the middle in the memory according to the physical address distribution as a middle data block.
10. the apparatus of claim 8, wherein the intermediate data block comprises:
and when the number of the data blocks in the memory is an even number, selecting any one of two data blocks positioned in the middle of the memory according to physical address distribution as a middle data block.
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