CN106527100B - A kind of adjustable timing circuit of tracking-resistant interference - Google Patents
A kind of adjustable timing circuit of tracking-resistant interference Download PDFInfo
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- CN106527100B CN106527100B CN201610948469.7A CN201610948469A CN106527100B CN 106527100 B CN106527100 B CN 106527100B CN 201610948469 A CN201610948469 A CN 201610948469A CN 106527100 B CN106527100 B CN 106527100B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/02—Apparatus for measuring unknown time intervals by electric means using oscillators with passive electric resonator, e.g. lumped LC
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Abstract
The present invention provides a kind of adjustable timing circuits of tracking-resistant interference.The adjustable timing circuit of tracking-resistant interference includes: comparator, for being compared the voltage of external capacitor with a preset voltage threshold and exporting comparison result；Logic circuit, with the port for receiving clock signal, enable signal, the output signal and clock signal of the comparator can be received, and export control signal, wherein, logic circuit is since enable signal is effective and external capacitor starts to charge, until counting in this period that the voltage of external capacitor reaches preset voltage threshold to clock signal, and obtains the first count value；Logic circuit is adjusted the first count value, and exports control signal；Controlled counter is counted for receiving the input signal to be postponed and control signal, and according to control signal, when counting up to the second count value, controlled counter just exports input signal, wherein the control signal that the second count value is exported by logic circuit is determined.
Description
Technical field
The present invention relates to IC design fields, more particularly to need the IC circuit of clocking capability.
Background technique
Certain chips need the clocking capability of adjustable time for application demand.If will be after chip package to meter
When be adjusted, the connect external devices of PIN foot generally can be perhaps replaced using chip PIN foot and are selected or using chip
Communication is to be adjusted.It is more commonly used in the prior art for adjusting chip interior timing by replacement external devices
It is to be realized using to external capacitor charge and discharge (I*t=C*V).But this mode can exist on external capacitor when timing is longer
The small problem of pull-down current.Such as in lithium electric protection product, the realization of overcurrent protection function needs the timing up to 1s, if sharp
With realizing to external capacitor charge and discharge, in the case where it is 5V that pull-up, which overturns point voltage, the external capacitor of 0.1uF needs upper
Sourcing current is only 0.5uA (0.5uA=0.1uF*5V/1s).Such pull-up current very little, if at the port of external capacitor
There is electric leakage in the presence of electric leakage or external capacitor, then timing is just affected and is likely to not come into force.
Figure 1A is the port (COFF) of external capacitor in the prior art without the timing waveform diagram of electric leakage.
Figure 1B is that the port (COFF) of external capacitor in the prior art has the timing waveform diagram of electric leakage.
Wherein, VTR is the voltage of COFF when timing stops.When there is electric leakage at the port (COFF) of external capacitor, meter
When be likely to just come into force forever, as shown in Figure 1B.
Therefore, for by capacitor charging come realize adjust clocking capability in the way of, how to increase charging current to realize
The scheme of tracking-resistant interference is that current industry needs to seek.
Summary of the invention
In order to solve this problem, the invention discloses a kind of adjustable timing circuits of tracking-resistant interference.The circuit can be with
It is widely used in the various chips for needing internal clocking.
In one embodiment, the present invention provides a kind of adjustable timing circuits of tracking-resistant interference, which is characterized in that institute
Stating the adjustable timing circuit that tracking-resistant is interfered includes:
Comparator, compared with the voltage of external capacitor is compared and is exported with a preset voltage threshold (VTR)
As a result；
Logic circuit, port of the logic circuit with reception clock signal, the logic circuit reception enable signal,
The output signal of the comparator and the clock signal (CLK), and export control signal, wherein the logic circuit from
Enable signal is effectively and external capacitor starts to charge beginning, until the voltage of external capacitor reaches the preset voltage threshold
(VTR) clock signal (CLK) is counted in this period, and obtains the first count value；The logic circuit pair
First count value is adjusted, and exports the control signal；
Controlled counter, the controlled counter is for receiving the input signal to be postponed (IN) and the logic circuit
The control signal of output, and counted according to the control signal, when counting up to the second count value, controlled counter
Just export the input signal, wherein the control signal that second count value is exported by the logic circuit is determined.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference further include:
For connecting the port (COFF) of external capacitor.
In one embodiment, the voltage threshold (VTR) is determined by actual demand and circuit realization.
In one embodiment, the control signal is the function of first count value, for the controlled counting
Device is adjusted.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference further include:
Pull-up circuit includes at least current source or resistance, the port of the pull-up circuit and the connection external capacitor
(COFF) it is connected；
Pull-down circuit includes at least current source or resistance, the port of the pull-down circuit and the connection external capacitor
(COFF) it is connected.
In one embodiment, when the enable signal is effective, the pull-down circuit stops working, the pull-up circuit
It starts to work and the current potential of the external capacitor is pulled up.
Beneficial effects of the present invention are as follows:
For the circuit in the present invention, since the period that CLK may be implemented is sufficiently small, pull-up circuit can be with by force
Pull-up current realizes timing, needs to reduce external electrical when timing is longer to solve using to external capacitor charge and discharge
In appearance the problem of pull-down current.
Still by taking the overcurrent protection function of lithium electric protection product as an example, function realizes the timing needed up to 1s, using external
Portion capacitor charge and discharge realizes that, in the case where pull-up overturning point is 5V, the pull-up current that the external capacitive of 0.1uF needs is only
0.5uA.As shown in figure 4, traditional timing circuit pull-up current is 0.5uA, resistive when having under external capacitor 0.1uF, VTR=5V
When electric leakage, the VTR that linearly increases to when voltage on COFF is from without resistive electric leakage becomes certain that can only increase between 0V~VTR
A level, so as to cause loss of timing；And for the timing circuit in the present invention, timing includes pull-up external capacitor and controlled meter
Number this two parts of device timing, the time that distribution external capacitor is pulled to VTR is 5ms (=1s/200), when controlled counter counts
995ms (=1s*199/200) is adjusted to by logic circuit, such pull-up current can be increased to 100uA, even if there is resistance at this time
Property electric leakage, influence to timing also very little.If clk cycle is sufficiently small, external capacitor pulls up the time can be shorter, on
Sourcing current can be bigger, and the influence leaked electricity to timing is just smaller.When due to external capacitor pull-up time and controlled counter counts all
It is, the size of change external capacitor size i.e. changeable timing relevant to external capacitor size.
Detailed description of the invention
The above summary of the invention of the invention and following specific embodiment can obtain more preferably when reading in conjunction with the drawings
Understanding.It should be noted that attached drawing is only used as the example of claimed invention.In the accompanying drawings, identical appended drawing reference
Represent same or similar element.
Figure 1A is the port (COFF) of external capacitor without the timing waveform diagram of electric leakage；
Figure 1B is that the port (COFF) of external capacitor has the timing waveform diagram of electric leakage；
Fig. 2 is the adjustable timing circuit interfered according to a kind of tracking-resistant of one embodiment of the invention；
Fig. 3 is the circuit working timing figure according to one embodiment of the invention；
Fig. 4 is the port (COFF) according to the external capacitor of one embodiment of the invention in different pull-up currents, different electric leakages
Timing waveform diagram under state.
Description of symbols
201 pull-up circuits
202 pull-down circuits
203 comparators
204 logic circuits
205 counters
206 chips input PIN foot
EN enable signal
VTR voltage compares threshold value
The output of CMP_O comparator
CLK clock signal
The output of LOGIC_O logic circuit, control signal
IN needs the signal postponed
Signal after OUT delay
The port of COFF external capacitor
Specific embodiment
Describe detailed features and advantage of the invention in detail in a specific embodiment below, content is enough to make any
Skilled in the art realises that technology contents of the invention and implementing accordingly, and according to specification disclosed by this specification, power
Benefit requires and attached drawing, skilled person readily understands that the relevant purpose of the present invention and advantage.
Fig. 2 is the adjustable timing circuit interfered according to a kind of tracking-resistant of one embodiment of the invention.This is adjustable timing circuit
Include, but are not limited to pull-up circuit (PULL UP) 201, pull-down circuit (PULL DOWN) 202, comparator (CMP) 203, logic
Circuit (LOGIC) 204, controlled counter (COUNTER) 205, chip input PIN foot (COFF) 206.
Pull-up circuit 201 includes, but are not limited to current source, resistance etc..
Pull-down circuit 202 includes, but are not limited to current source, resistance etc..
Chip input PIN foot (COFF) 206 is for connecing off-chip capacitive appearance.
Comparator (CMP) 203 is used for the voltage and a preset electricity on PIN foot (COFF, for connecting external capacitor)
Pressure threshold value VTR is compared, and voltage threshold VTR can be determined by actual demand and circuit realization.
Logic circuit (LOGIC) 204 is used to become 1 (i.e., 1 indicates effective) from 0 to enable signal (EN) defeated to comparator
The clock signal clk that (CMP_O) becomes between 1 from 0 out is counted and is obtained the first count value n, and to the first count value n into
Row adjustment (i.e. to the first count value n carry out functional transformation), and export control signal LOGIC_O, the control signal for pair
Controlled counter (COUNTER) 205 is adjusted, wherein the function that control signal is the first count value n.
Controlled counter (COUNTER) 205 is used to receive the control letter of the signal IN to be postponed and logic circuit output
Number, and (count value of controlled counter is known as the second count value) is counted according to the control signal, second count value with
The control signal of logic circuit output is related, when counting up to second count value, controlled counter output input signal IN's
Rising edge, this, which is equivalent to, postpones input signal IN, and the delay time and the first count value n are at functional dependence.
It compares traditional utilization and timing is realized to external capacitor charge and discharge, present invention adds patrolling with the port clock CLK
Collect circuit (LOGIC) 204 and controlled counter (COUNTER) 205.
When enable signal EN becomes 1 from 0, pull-down circuit (PULL DOWN) 202 stops working, by pull-up circuit (PULL
UP) external capacitor of 201 pairs of chips pulls up, and when the voltage of external capacitor port COFF206 is greater than preset voltage threshold
When value VTR, the output CMP_O of comparator (CMP) 203, which is flipped from 0, becomes 1, and logic circuit (LOGIC) 204 is just to EN (0
→ 1) and in CMP_O (0 → 1) this period (namely the voltage of external capacitor is out of, 0 charging is raised to VTR period)
CLK rising edge (or failing edge) is counted, and count value n is obtained.Meanwhile logic circuit 204 converts count value n,
A control signal relevant to n is exported, for example, the control signal is the function of n.The control signal is to the controlled of chip interior
Counter (COUNTER) controlled to adjust, so that arbitrary input IN will be by prolonging with the functional dependence of count value n
Chi Caineng is output to OUT, so that it is adjustable to realize timing.Clock signal clk provided by the invention is in chip, and the period can
To be designed to very little, thus no matter the voltage at the end COFF by 0 to preset threshold V T R time, (i.e. external capacitor fills
The electric time) have it is how short, CLK always can to the period carry out sample count.And very short capacitor charging time, it is meant that on
Puller circuit (PULL UP) 201 can use strong pull-up electric current, count to solve tradition using to external capacitor charge and discharge to realize
When, the small problem of pull-down current on external capacitor when timing is longer.At this point, if there is leakage current, due to pull-up current
Very big, electric leakage is nearly free from interference to the pull-up current.
Circuit working timing figure is as shown in Figure 3.When enable signal EN becomes 1 by 0, chip external capacitor is by PULL UP
It draws, until the voltage on COFF is greater than VTR, the output CMP_O of comparator CMP also becomes 1 by 0,204 pairs of logic circuit (LOGIC)
Clock signal clk rising edge in EN (0 → 1) and CMP_O (0 → 1) this period is counted.In one embodiment, it patrols
The failing edge of clock signal clk can also be counted by collecting circuit.After the completion of counting will relevant to count value parameter (i.e. into
The second count value after row adjustment) COUNTER is sent to adjust timing；If the count value in Fig. 3 is n, logic circuit is adjusted
The timing of controlled counter circuit is n clk cycle (Fig. 3 is a special case, can be arbitrary function relevant to n), then
Input signal IN (can be any signal for needing delay output) is sent to output OUT by the delay of n clk cycle.
In one embodiment, the present invention provides a kind of adjustable timing circuit of tracking-resistant interference, the tracking-resistant is dry
The adjustable timing circuit disturbed includes:
Comparator, compared with the voltage of external capacitor is compared and is exported with a preset voltage threshold (VTR)
As a result；
Logic circuit, port of the logic circuit with reception clock signal, the logic circuit reception enable signal,
The output signal of the comparator and the clock signal (CLK), and export control signal, wherein the logic circuit from
Enable signal is effectively and external capacitor starts to charge beginning, until the voltage of external capacitor reaches the preset voltage threshold
(VTR) clock signal (CLK) is counted in this period, and obtains the first count value；The logic circuit pair
First count value is adjusted, and exports the control signal；
Controlled counter, the controlled counter is for receiving the input signal to be postponed (IN) and the logic circuit
The control signal of output, and counted according to the control signal, when counting up to the second count value, controlled counter
Just export the input signal, wherein the control signal that second count value is exported by the logic circuit is determined.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference further include:
For connecting the port (COFF) of external capacitor.
In one embodiment, the voltage threshold (VTR) is determined by actual demand and circuit realization.
In one embodiment, the control signal is the function of first count value, for the controlled counting
Device is adjusted.
In one embodiment, the adjustable timing circuit of the tracking-resistant interference further include:
Pull-up circuit includes at least current source or resistance, the port of the pull-up circuit and the connection external capacitor
(COFF) it is connected；
Pull-down circuit includes at least current source or resistance, the port of the pull-down circuit and the connection external capacitor
(COFF) it is connected.
In one embodiment, when the enable signal is effective, the pull-down circuit stops working, the pull-up circuit
It starts to work and the current potential of the external capacitor is pulled up.
In conjunction with foregoing description, for the circuit in the present invention, as long as the period of clock signal clk is small, so that it may allow pull-up
Circuit strong pull-up electric current subtracts to solve using to external capacitor charge and discharge to realize timing, need when timing is longer
On small external capacitor the problem of pull-down current.
It should be appreciated by those skilled in the art that technical solution of the present invention can be applied to need any of clocking capability
IC.In order to facilitate understanding, for this sentences the overcurrent protection function of lithium electric protection product, function realizes the meter needed up to 1s
When, using being realized to external capacitor charge and discharge, in the case where pull-up overturning point (i.e. VTR) is 5V, the external capacitor of 0.1uF
The pull-up current needed is only 0.5uA.As shown in Fig. 4, under external capacitor 0.1uF, VTR=5V, traditional timing circuit pull-up
Electric current is 0.5uA, when there is resistive electric leakage, linearly increasing to when voltage on COFF is from without resistive electric leakage VTR becomes can only
Some level between 0V~VTR is increased to, so as to cause loss of timing；And for the timing circuit in the present invention, timing packet
Pull-up external capacitor and controlled counter (COUNTER) timing this two parts are included, distribution external capacitor is pulled to the time of VTR
For 5ms (=1s/200), controlled counter (COUNTER) timing is adjusted to 995ms (=1s*199/ by logic circuit (LOGIC)
200), such pull-up current can be increased to 100uA, even if there is resistive electric leakage at this time, the also very little of the influence to timing.If
Clk cycle is sufficiently small, then the external capacitor pull-up time can be shorter, pull-up current can be bigger, the shadow to leak electricity to timing
Sound is just smaller.Since external capacitor pull-up time and controlled counter (COUNTER) timing are all related to external capacitor size
, change the size that external capacitor size is changeable timing.
Here the term and form of presentation used is only intended to describe, and the present invention should not be limited to these terms and table
It states.It is not meant to exclude the equivalent features of any signal and description (or in which part) using these terms and statement, should recognize
Knowing various modifications that may be present should also be included in scope of the claims.Other modifications, variations and alternatives are also likely to be present.
Correspondingly, claim should be regarded as covering all these equivalents.
Equally, it should be pointed out that although the present invention is described with reference to current specific embodiment, this technology neck
Those of ordinary skill in domain it should be appreciated that more than embodiment be intended merely to illustrate the present invention, in no disengaging present invention
Various equivalent change or replacement can be also made in the case where spirit, therefore, as long as right in spirit of the invention
The variation, modification of above-described embodiment will all be fallen in the range of following claims.
Claims (6)
1. a kind of adjustable timing circuit of tracking-resistant interference, which is characterized in that the adjustable timing circuit packet of the tracking-resistant interference
It includes:
Comparator, for being compared the voltage of external capacitor and a preset voltage threshold (VTR) and exporting comparison result；
Logic circuit, the logic circuit have a port for receiving clock signal, and the logic circuit receives enable signal, described
The output signal of comparator and the clock signal (CLK), and export control signal, wherein the logic circuit is from enabled
Signal is effectively and external capacitor starts to charge beginning, until the voltage of external capacitor reaches this section of the preset voltage threshold
The clock signal (CLK) is counted in time, and obtains the first count value；The logic circuit is counted to described first
Value is adjusted, and exports the control signal；
Controlled counter, the controlled counter is for receiving the input signal to be postponed (IN) and logic circuit output
The control signal, and counted according to the control signal, when counting up to the second count value, controlled counter is just defeated
The input signal out, wherein the control signal that second count value is exported by the logic circuit is determined.
2. adjustable timing circuit as described in claim 1, which is characterized in that the adjustable timing circuit of the tracking-resistant interference is also
Include:
For connecting the port (COFF) of external capacitor.
3. adjustable timing circuit as described in claim 1, which is characterized in that the voltage threshold is real by actual demand and circuit
Now determine.
4. adjustable timing circuit as described in claim 1, which is characterized in that the control signal is first count value
Function, for the controlled counter to be adjusted.
5. adjustable timing circuit as claimed in claim 2, which is characterized in that the adjustable timing circuit of the tracking-resistant interference is also
Include:
Pull-up circuit includes at least current source or resistance, the port of the pull-up circuit and the connection external capacitor
(COFF) it is connected；
Pull-down circuit includes at least current source or resistance, the port of the pull-down circuit and the connection external capacitor
(COFF) it is connected.
6. adjustable timing circuit as claimed in claim 5, which is characterized in that when the enable signal is effective, the drop-down
Circuit stops working, and the pull-up circuit is started to work and pulled up to the external capacitor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610948469.7A CN106527100B (en) | 2016-10-26 | 2016-10-26 | A kind of adjustable timing circuit of tracking-resistant interference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610948469.7A CN106527100B (en) | 2016-10-26 | 2016-10-26 | A kind of adjustable timing circuit of tracking-resistant interference |
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| CN106527100A CN106527100A (en) | 2017-03-22 |
| CN106527100B true CN106527100B (en) | 2019-01-15 |
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| CN110035581B (en) * | 2019-04-22 | 2023-10-13 | 上海芯荃微电子科技有限公司 | Slow timing module |
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| EP1041464A2 (en) * | 1999-03-03 | 2000-10-04 | Seiko Epson Corporation | Electronic device and method of controlling the same |
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| CN1298131A (en) * | 1999-11-24 | 2001-06-06 | 精工爱普生株式会社 | Electronic chronometer and its controlling method |
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| CN103684374A (en) * | 2012-09-14 | 2014-03-26 | Nxp股份有限公司 | Zero or ultra-low dc current consumption power-on and brown-out detector |
| CN104660022A (en) * | 2015-02-02 | 2015-05-27 | 昂宝电子（上海）有限公司 | System and method for providing overcurrent protection for power converter |
| CN104883159A (en) * | 2015-04-20 | 2015-09-02 | 成都岷创科技有限公司 | Clock phase control circuit |
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2016
- 2016-10-26 CN CN201610948469.7A patent/CN106527100B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87100999A (en) * | 1987-03-03 | 1988-02-10 | 周洪璋 | The long-time controller that pump formula staircase generator is arranged |
| EP1041464A2 (en) * | 1999-03-03 | 2000-10-04 | Seiko Epson Corporation | Electronic device and method of controlling the same |
| US6181649B1 (en) * | 1999-07-14 | 2001-01-30 | Guide Technology, Inc. | Time interval analyzer having current boost |
| CN1298131A (en) * | 1999-11-24 | 2001-06-06 | 精工爱普生株式会社 | Electronic chronometer and its controlling method |
| US8020138B2 (en) * | 2008-06-02 | 2011-09-13 | International Business Machines Corporation | Voltage island performance/leakage screen monitor for IP characterization |
| CN103684374A (en) * | 2012-09-14 | 2014-03-26 | Nxp股份有限公司 | Zero or ultra-low dc current consumption power-on and brown-out detector |
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| CN106527100A (en) | 2017-03-22 |
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