CN104883159A - Clock phase control circuit - Google Patents
Clock phase control circuit Download PDFInfo
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- CN104883159A CN104883159A CN201510183934.8A CN201510183934A CN104883159A CN 104883159 A CN104883159 A CN 104883159A CN 201510183934 A CN201510183934 A CN 201510183934A CN 104883159 A CN104883159 A CN 104883159A
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Abstract
A clock phase control circuit comprises a clock input stage, a capacitor, a level detection circuit, a pull-up circuit, a pull-down circuit, a clock output stage and a logic control circuit. The output end of the clock input stage and the input end of the level detection circuit are connected at an A point, and the A point is also connected with the output ends of the capacitor, the pull-up circuit and the pull-down circuit. The other end of the capacitor is connected with a fixed DC level, and the level detection circuit detects the voltage of the A point and outputs a detection signal to the clock output stage. The logic control circuit is connected with the clock input stage, the pull-up circuit and the pull-down circuit, and controls the pull-up circuit and the pull-down circuit to be turned on at the high level time and the low level time of a clock respectively. The clock phase control circuit of the present invention starts to charge and discharge the capacitor at the rising or falling edge of the clock, thereby causing the time delay of a signal output edge. The clock phase control circuit is simple in circuit principle, is convenient to integrate in an integrated circuit existing technology, does not need to the support of a peripheral separating electronic component, realizes a clock buffer function, and also enables the circuit cost to be reduced.
Description
Technical field
The invention belongs to electronic circuit field, relate to a kind of clock phase control circuit.
Background technology
Clock frequency, refers to the base frequency of clock in synchronous circuit, and it is measured with " the several times cycle is per second ", and unit adopts SI unit hertz (Hz).In digital circuit and analog circuit chip, numerous transistors is all operated on off state, and their turn-on and turn-off action is carry out according to the rhythm of clock signal invariably.If clock frequency is too high, just may occur that the state of transistor has little time situation, produce of deadlock or the randomness misoperation changed.Meanwhile, due to the needs of circuit working state, the phase place of clock needs to adjust, and existing clock phase adjustment usually relies on independent chip and realizes, and occupies the area of pcb board while raising the cost.
Summary of the invention
For overcoming the defect of prior art, the invention discloses a kind of clock phase control circuit.
Clock phase control circuit of the present invention, comprise clock input stage, electric capacity, level sensitive circuit, pull-up circuit, pull-down circuit, clock output stage and logic control circuit, the output of clock input stage and the input of level sensitive circuit are connected to A point, A point is also connected with the output of electric capacity and pull-up circuit and pull-down circuit, another termination of electric capacity fixes DC level, described level sensitive circuit detects A point voltage, and output detection signal is to clock output stage; Described logic control circuit is connected with clock input stage, pull-up circuit and pull-down circuit, and control pull-up circuit and pull-down circuit are opened at the high level time of clock and low level time respectively.
Concrete, described clock input stage and clock output stage are realized by a rest-set flip-flop, and clock signal is from the R end input of rest-set flip-flop, and Q holds output; QN end is connected with A point, and S end is connected with the output of level sensitive circuit.
Concrete, described pull-up circuit is PMOS, pull-down circuit is NMOS tube, and PMOS is connected with the equal andlogic control circuit of the grid of NMOS tube.
Concrete, described level sensitive circuit is inverter or comparator.
Concrete, described logic control circuit is that an inverter or the odd number inverter series that is greater than 1 realize.
Adopting clock phase control circuit of the present invention to adopt starts capacitor charge and discharge when the rising of clock or trailing edge, capacitor charging or energizing signal again when discharging into the detection level of level sensitive circuit, signal is caused to export the time delay on edge, circuit theory is simple, be convenient to realize in the existing technique of integrated circuit integrated, need not peripheral separating electronic components support, reduce circuit cost while realizing clock buffer function.
Accompanying drawing explanation
Fig. 1 illustrates a kind of embodiment structural representation of the present invention;
In figure, Reference numeral name is called: 1. logic control circuit 2. detection reference voltage 3. electric capacity 6. level sensitive circuit 7. input end of clock mouth 8. pull-up circuit 9. pull-down circuit 10. output terminal of clock.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
Clock phase control circuit of the present invention comprises clock input stage, electric capacity 3, level sensitive circuit 6, pull-up circuit 8, pull-down circuit 9, clock output stage and logic control circuit 1, the output of clock input stage and the input of level sensitive circuit 6 are connected to A point, A point is also connected with the output of electric capacity 3 and pull-up circuit 8 and pull-down circuit 9, another termination of electric capacity fixes DC level, preferably can ground connection; Described level sensitive circuit 6 pairs of A point voltages detect, and output detection signal is to clock output stage; Described logic control circuit 1 is connected with clock input stage, pull-up circuit 8 and pull-down circuit 9, and control pull-up circuit and pull-down circuit are opened at the high level time of clock and low level time respectively.
Clock signal inputs from input end of clock mouth 7, when rising edge clock signal is by after clock input stage, pull-up circuit 8 is started working, now pull-down circuit 9 is closed, pull-up circuit 8 pairs of electric capacity 3 charge, when charging to the detection level higher than level sensitive circuit, level sensitive circuit output signal uprises from low, and the charging interval is the time delay between rising edge clock signal and level sensitive circuit output signal rising edge.In the high level stage of clock signal, capacitance voltage is pulled up circuit and is pulled up to supply voltage.When clock signal trailing edge passes through clock input stage, pull-down circuit works, pull-up circuit is closed simultaneously, electric capacity is discharged, when being discharged to the detection level lower than level sensitive circuit, level sensitive circuit output signal, from high step-down, is the time delay between clock signal trailing edge and level sensitive circuit output signal trailing edge discharge time.Here suppose that the time delay of level sensitive circuit is negligible, in fact, the time delay of usual level sensitive circuit is quite little compared with capacitor charge and discharge time delay, and the time delay due to level sensitive circuit is difficult to accurate control, the design focal point of therefore time delay length is the accuracy of detection of capacitor charge and discharge time and level sensitive circuit.
Foregoing circuit structure adopts and starts capacitor charge and discharge when the rising of clock or trailing edge, and capacitor charging or energizing signal again when discharging into the detection level of level sensitive circuit, cause signal to export the time delay on edge.
Provide some can combination preferred embodiment, such as pull-up and pull-down circuit can adopt current source to realize, and current source easily realizes matching each other in design, makes pull-up current and pull-down current all equal under various conditions.And with prior art, constant temperature current source easily realizes, charging and discharging electric current is made not vary with temperature and change.Relative RC time delay, current source discharge and recharge time delay avoids the time delay drift that electrical resistance process deviation brings.
Level sensitive circuit is a comparator circuit preferably, and comparator anode connects a detection reference voltage 2, the DC level of such as about 1.2V.Detection reference voltage is selected usually near the half of supply voltage, and make on the one hand comparator at this reference voltage as better performances when comparing input voltage, voltage drop during electric capacity 3 discharge and recharge simultaneously on electric capacity is roughly the same, is convenient to charging and discharging currents and arranges.
Consider from design is succinct, level sensitive circuit also can adopt simple gate, such as an inverter, and using the reversion level of inverter as detection voltage, but the reversion level of inverter is larger with multiple factor bias such as technological temperatures.
Clock input stage and clock output stage can be realized by a rest-set flip-flop, and clock signal is from the R end input of rest-set flip-flop, and Q end goes clock signal output terminal 10 connection to export; QN end is connected with A point, and S end is connected with the output of level sensitive circuit.This implementation is simple and reliable, and only two can realize with door.
Adopting clock phase control circuit of the present invention to adopt starts capacitor charge and discharge when the rising of clock or trailing edge, capacitor charging or energizing signal again when discharging into the detection level of level sensitive circuit, signal is caused to export the time delay on edge, circuit theory is simple, be convenient to realize in the existing technique of integrated circuit integrated, need not peripheral separating electronic components support, reduce circuit cost while realizing clock buffer function.
Previously described is each preferred embodiment of the present invention, preferred implementation in each preferred embodiment is if not obviously contradictory or premised on a certain preferred implementation, each preferred implementation can stack combinations use arbitrarily, design parameter in described embodiment and embodiment is only the invention proof procedure in order to clear statement inventor, and be not used to limit scope of patent protection of the present invention, scope of patent protection of the present invention is still as the criterion with its claims, the equivalent structure change that every utilization specification of the present invention and accompanying drawing content are done, in like manner all should be included in protection scope of the present invention.
Claims (5)
1. clock phase control circuit, it is characterized in that, comprise clock input stage, electric capacity (3), level sensitive circuit (6), pull-up circuit (8), pull-down circuit (9), clock output stage and logic control circuit (1), the output of clock input stage and the input of level sensitive circuit are connected to A point, A point is also connected with electric capacity (3), and the output of pull-up circuit (8) and pull-down circuit (9), electric capacity (3) another termination fixes DC level, described level sensitive circuit (6) detects A point voltage, and output detection signal is to clock output stage, described logic control circuit (1) is connected with clock input stage, pull-up circuit and pull-down circuit, and control pull-up circuit and pull-down circuit are opened at the high level time of clock and low level time respectively.
2. clock phase control circuit as claimed in claim 1, is characterized in that: described clock input stage and clock output stage are realized by a rest-set flip-flop, and clock signal is from the R end input of rest-set flip-flop, and Q holds output; QN end is connected with A point, and S end is connected with the output of level sensitive circuit.
3. clock phase control circuit as claimed in claim 1, it is characterized in that, described pull-up circuit (8) is PMOS, pull-down circuit (9) is NMOS tube, PMOS is connected with the equal andlogic control circuit of the grid of NMOS tube.
4. clock phase control circuit as claimed in claim 1, it is characterized in that, described level sensitive circuit is inverter or comparator.
5. clock phase control circuit as claimed in claim 1, is characterized in that, described logic control circuit is that an inverter or the odd number inverter series that is greater than 1 realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510183934.8A CN104883159A (en) | 2015-04-20 | 2015-04-20 | Clock phase control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510183934.8A CN104883159A (en) | 2015-04-20 | 2015-04-20 | Clock phase control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104883159A true CN104883159A (en) | 2015-09-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510183934.8A Pending CN104883159A (en) | 2015-04-20 | 2015-04-20 | Clock phase control circuit |
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| CN (1) | CN104883159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527100A (en) * | 2016-10-26 | 2017-03-22 | 中颖电子股份有限公司 | Adjusting time-counting circuit resistant to electric leakage interference |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020021153A1 (en) * | 2000-07-21 | 2002-02-21 | Nec Corporation | Clock controlling method and circuit |
| CN102739209A (en) * | 2012-07-09 | 2012-10-17 | 成都启臣微电子有限公司 | Clock pulse width modulation circuit and clock pulse width modulation method |
| CN103000143A (en) * | 2012-12-24 | 2013-03-27 | 成都巨芯科技有限公司 | Full-color light-emitting diode (LED) array gray level adjustment method and circuit |
-
2015
- 2015-04-20 CN CN201510183934.8A patent/CN104883159A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020021153A1 (en) * | 2000-07-21 | 2002-02-21 | Nec Corporation | Clock controlling method and circuit |
| CN102739209A (en) * | 2012-07-09 | 2012-10-17 | 成都启臣微电子有限公司 | Clock pulse width modulation circuit and clock pulse width modulation method |
| CN103000143A (en) * | 2012-12-24 | 2013-03-27 | 成都巨芯科技有限公司 | Full-color light-emitting diode (LED) array gray level adjustment method and circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106527100A (en) * | 2016-10-26 | 2017-03-22 | 中颖电子股份有限公司 | Adjusting time-counting circuit resistant to electric leakage interference |
| CN106527100B (en) * | 2016-10-26 | 2019-01-15 | 中颖电子股份有限公司 | A kind of adjustable timing circuit of tracking-resistant interference |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20160419 Address after: 201204 Zhang Heng road Shanghai, Pudong New Area Zhangjiang hi tech Park Lane 666 No. 2 floor 504-511 room 5 Applicant after: Shanghai Bright Power Semiconductor Co.,Ltd. Address before: West high tech Zone Fucheng Road in Chengdu city of Sichuan province 610000 399 No. 6 Building 1 unit 10 floor No. 2 Applicant before: Chengdu Minchuang Science & Technology Co., Ltd. |
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Address after: 5 room 504-511, room 2, Lane 666, Zhang Heng Road, Pudong New Area, China (Shanghai) free trade zone, Shanghai, China () Applicant after: Shanghai semiconducto Limited by Share Ltd Address before: 201204 Zhang Heng road Shanghai, Pudong New Area Zhangjiang hi tech Park Lane 666 No. 2 floor 504-511 room 5 Applicant before: Shanghai Bright Power Semiconductor Co.,Ltd. |
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| WD01 | Invention patent application deemed withdrawn after publication | ||
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Application publication date: 20150902 |