CN106486168B - Intersection write method on nand flash memory based on index modulation - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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Abstract
The invention discloses the intersection write method on a kind of nand flash memory based on index modulation, it the steps include: that (1) carries out erasing operation to nand flash memory cell；(2) nand flash memory cell wiped is written by the intersection write method on nand flash memory based on index modulation in the data being written into；(3) data stored in nand flash memory cell are read.The present invention has many advantages, such as that interference performance is strong, average bit error performance is good, unequal error protection may be implemented between anti-unit, for solving the problems, such as that error performance is poor, can not achieve unequal error protection present in existing nand flash memory write method.
Description
Technical field
The invention belongs to technical field of electronic devices, further relate to one of technical field of semiconductor memory NAND
Intersection write method based on index modulation on (Not AND, NAND) flash memory.Present invention could apply to realize on nand flash memory
Data write, while the lower bit information of priority is write by odd character line, it is higher that even character line writes priority
Bit information realizes the unequal error protection of storing data in flash cell.
Background technique
In the modern semiconductors information processing technology, the nand flash memory nonvolatile storage technologies important as one kind are
It is paid close attention to more and more by people.Due to device integration is higher and higher and the use of multilevel-cell technology etc., by dodging
It is interfered between the unit that parasitic coupling capacitance effect generates between memory cell also further serious.Therefore NAND flash memory equipment reliability is improved
Data write method also become an important research contents.
The prior art provides some for improving the data write method of NAND flash memory equipment reliability.These methods are big
Mostly writing sequentially by adjusting nand flash memory cell, interferes the influence write to flash data between reduction unit, to improve
The reliability of NAND flash memory equipment.But compared to the demand of present people, these methods are existing there are clearly disadvantageous
Nand flash memory write method can not be realized under the premise of improving error performance and not wait error protections.
Ken Takeuchi et al. is in article " A 56-nm CMOS 99-mm2 8-Gb multi-level NAND
flash memory with 10-MB/s program throughput”(IEEE Solid-State Circuits
Society, 2007) a kind of even-odd bit line nand flash memory write method is disclosed in.This method passes through respectively for mutually friendship
Wrong odd bit line carries out compilation operation with the mode that even bit line replaces access.Each pair of even-odd bit line can share a set of outer
Circuit is enclosed, this feature to possess the lower advantage of manufacturing cost using parity bits line method.In addition, this method is due to surprise
The degree interfered between the unit that flash cell is subject on even bit line is different, therefore the mistakes such as not can also be realized to storing data
Protection.Shortcoming existing for this method is, since flash cell intersection is write on even-odd bit line, to go out
It is interfered between existing biggish unit, whole error performance is poor.
Paper " the A 34MB/s MLC write throughput that Raul-Adrian Cernea et al. is delivered at it
16Gb NAND with all bit line architecture on 56nm technology”(IEEE J.Solid-
State Circuits, Jan 2009) in disclose a kind of full bit line nand flash memory write method.In the method, own
Bit line accessed carry out compilation operation simultaneously.Such design method is compared to parity bits line method, while it is desirable to more
More peripheral circuits improves manufacturing cost, but has stronger immunocompetence to make whole error performance interference unit
Preferably.But the shortcoming that this method still has is, due to being interfered between flash cell is subject on even-odd bit line unit
Degree it is identical, therefore can not to storing data realize unequal error protection.
Patent " method and dress in flash memories be written end unit between interference mitigation of the Infineon Technologies Corp. in its application
Set " a kind of mitigation nand flash memory data are proposed in (number of patent application 200980132503.1, publication number 102132348B) compiles
The method interfered between the unit generated during writing.This method, which mainly passes through acquisition, will be written in the flash memories
The programming data of at least one object element obtains the volume of at least one interference unit for being later than the object element programming
One or more positions of number of passes evidence；And by generating the programming value through pre-compensating for, to pre-compensate for for the object element
Unit between interfere.The interference unit includes one or more units adjacent with the object element, such as with institute
State one or more adjacent units in object element same word line and/or in the adjacent word line of the unit up or down
One or more units.Deficiency existing for this method is, since this method is to subtract one in advance before introducing interference
Voltage value, therefore this method may not apply to the unit in erase status, the interference being subject to the unit in erase status
Helpless, the bit error rate is higher.
Summary of the invention
The advantages of it is an object of the invention to be directed to the above-mentioned prior art and deficiency propose on a kind of nand flash memory based on rope
The intersection write method for drawing modulation has while guaranteeing preferably whole error performance and carries out the mistakes such as not to storing data
The ability of protection.
To achieve the above object, specific steps of the present invention include the following:
(1) erasing operation is carried out to nand flash memory cell:
The charge on nand flash memory cell, the nand flash memory cell wiped are removed by nand flash memory controller.
(2) nand flash memory cell wiped is written in the data being written into:
(2a) by step pulse write method, carries out the nand flash memory cell on the odd character line wiped line by line
Compilation operation obtains storing the data in nand flash memory cell.
Specific step is as follows for step pulse write method:
Step 1, the reading data that the nand flash memory cell formulation on the odd character line wiped is entered to nand flash memory control
Device processed obtains the threshold voltage of the nand flash memory cell.
Step 2 adds a step voltage on odd character line, follows to the nand flash memory cell on the odd character line wiped
Ring carries out charge injection, and the voltage value of the nand flash memory cell is compared with threshold voltage, when the nand flash memory cell
Voltage value reach threshold voltage after, terminate compilation operation.
(2b) after the completion of being write to the nand flash memory cell on the odd character line wiped, to the even character line wiped
On nand flash memory cell compilation operation is carried out by index modulation write method line by line, obtain storage to nand flash memory cell
In data.
Specific step is as follows for index modulation write method:
Step 1, the bit sequence u that formulation is entered to the nand flash memory cell on the even character line wiped are divided into bit sequence
Arrange u1 and bit sequence u2.
Step 2 calculates the length of bit sequence u1 according to the following formula:
Wherein, K1Indicate the length of bit sequence u1, M indicates of the nand flash memory cell on the even character line wiped
Number, N indicate that formulation enters the number of the nand flash memory cell on the even character line of data wiped, and N=M/2, C (M, N) are indicated
The combined number of N number of flash cell is selected from M flash cell,Expression takes maximum integer to operate, log2It indicates with 2 to be bottom
Log operations.
Step 3 calculates the length of bit sequence u2 according to the following formula:
K2=Nlog2L
Wherein, K2Indicate the length of bit sequence u2, N indicates that formulation enters the NAND on the even character line of data wiped
The number of flash cell, L indicate that the voltage that uses writes the number of plies on the nand flash memory cell for the even character line of activation wiped,
log2Indicate the log operations with 2 bottom of for.
Step 4, nand flash memory controller read the data of bit sequence u1, obtain formulation on the even character line wiped and enter
The position of the nand flash memory cell of data.
Step 5, nand flash memory controller read the data of bit sequence u2, obtain the even word wiped that formulation enters data
The nand flash memory cell threshold voltage of line is accorded with, then compilation operation is completed by step pulse write method.
(3) data stored in nand flash memory cell are read:
(3a) reads the voltage value on the nand flash memory cell of storing data by nand flash memory controller.
(3b) by the nand flash memory cell of the storing data of reading voltage value and write-in data when threshold voltage
Be compared, obtain with read storing data nand flash memory cell on voltage value it is immediate write-in data when thresholding
Voltage value.
Threshold voltage when the write-in data that (3c) nand flash memory controller is read obtains in nand flash memory cell
The data of storage.
Compared with the prior art, the present invention has the following advantages:
First, since the present invention is after the completion of writing the nand flash memory cell on the odd character line wiped, to having wiped
The nand flash memory cell on even character line removed carries out compilation operation by index modulation write method line by line, at this point, even word
It is interfered between the unit that nand flash memory cell on symbol line is subject to negligible.Overcoming the prior art can not be to storing data reality
The deficiency of existing unequal error protection, so that the present invention has the function of the advantages of achievable unequal error protection.
Second, since the present invention is in the data of nand flash memory controller reading bit sequence u1, obtain the even word wiped
Formulation enters the position of the nand flash memory cell of data on symbol line.The nand flash memory list being actually written on even character line is allowed in this way
The data of member tail off, and interfere and reduce the unit between caused by the nand flash memory cell on odd character line.The prior art is overcome to exist
It will appear interference and the higher deficiency of the bit error rate between biggish unit in compiling procedure, so that the present invention interferes between having anti-unit
The advantage that ability is strong, average bit error performance is good.
Detailed description of the invention
Fig. 1 is flow chart of the invention；
Fig. 2 is flash cell on odd character line of the invention by the schematic diagram interfered between unit；
Fig. 3 is the bit error rate performance comparison diagram of the present invention with even-odd bit line nand flash memory write method；
Fig. 4 be the present invention with even-odd bit line nand flash memory write method, full bit line nand flash memory write method it is flat
Equal bit error rate performance comparison diagram.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.
Referring to Fig.1, to the specific steps of the present invention are as follows.
Step 1, erasing operation is carried out to nand flash memory cell.
The charge on nand flash memory cell, the nand flash memory cell wiped are removed by nand flash memory controller.
Each nand flash memory cell must first carry out erasing operation before being encoded, the meaning of erasing is exactly the floating from storage unit
All charges are removed inside grid, and the voltage of nand flash memory cell transistor is made to reach minimum.The erasing operation of nand flash memory
It is to be carried out with block (each piece includes many flash cells) for unit.The voltage value of nand flash memory cell becomes after the erase operation
It is greater than zero Gaussian Profile in mean value.
Step 2, the nand flash memory cell wiped is written in the data being written into.
Nand flash memory cell on the odd character line wiped is write line by line by step pulse write method
Operation, obtains storing the data in nand flash memory cell.
Specific step is as follows for step pulse write method:
Step 1, the reading data that the nand flash memory cell formulation on the odd character line wiped is entered to nand flash memory control
Device processed obtains the threshold voltage of the nand flash memory cell.
Step 2 adds a step voltage on odd character line, follows to the nand flash memory cell on the odd character line wiped
Ring carries out charge injection, and the voltage value of the nand flash memory cell is compared with threshold voltage, when the nand flash memory cell
Voltage value reach threshold voltage after, terminate compilation operation.
After the completion of being write to the nand flash memory cell on the odd character line wiped, on the even character line wiped
Nand flash memory cell carries out compilation operation by index modulation write method line by line, obtains storing in nand flash memory cell
Data.
Specific step is as follows for index modulation write method:
Step 1, the bit sequence u that formulation is entered to the nand flash memory cell on the even character line wiped are divided into bit sequence
Arrange u1 and bit sequence u2.
Step 2 calculates the length of bit sequence u1 according to the following formula:
Wherein, K1Indicate the length of bit sequence u1, M indicates of the nand flash memory cell on the even character line wiped
Number, N indicate that formulation enters the number of the nand flash memory cell on the even character line of data wiped, and N=M/2, C (M, N) are indicated
The combined number of N number of flash cell is selected from M flash cell,Expression takes maximum integer to operate, log2It indicates with 2 to be bottom
Log operations.
Step 3 calculates the length of bit sequence u2 according to the following formula:
K2=Nlog2L
Wherein, K2Indicate the length of bit sequence u2, N indicates that formulation enters the NAND on the even character line of data wiped
The number of flash cell, L indicate that the voltage that uses writes the number of plies on the nand flash memory cell for the even character line of activation wiped,
log2Indicate the log operations with 2 bottom of for.
When storage information needs to carry out unequal error protection, odd character line writes the lower bit information of priority, even
Character line writes the higher bit information of priority.Meanwhile the nand flash memory cell on even character line is compared on odd character line
Nand flash memory cell generally use the unit storage mode of higher order to improve storage density.
Step 4, nand flash memory controller read the data of bit sequence u1, obtain formulation on the even character line wiped and enter
The position of the nand flash memory cell of data.
Step 5, nand flash memory controller read the data of bit sequence u2, obtain the even word wiped that formulation enters data
The nand flash memory cell threshold voltage of line is accorded with, then compilation operation is completed by step pulse write method.
Step 3, the data stored in nand flash memory cell are read:
By nand flash memory controller, the voltage value on the nand flash memory cell of storing data is read.
Voltage value on the nand flash memory cell of the storing data of reading is carried out with threshold voltage when write-in data
Compare, obtain with read storing data nand flash memory cell on voltage value it is immediate write-in data when threshold voltage
Value.
Threshold voltage when the write-in data that nand flash memory controller is read is obtained and is stored in nand flash memory cell
Data.
When Fig. 2 intuitively describes compilation operation and finishes, unit that the nand flash memory cell in odd number character line is subject to
Between interfere.In fig. 2 it is possible to intuitively find out, the nand flash memory cell in odd character line is by from upper and lower two sides even number
It is interfered between 6 on the character line units for closing on nand flash memory cell.Index modulation is used further as even character line, so
The number interfered between the unit that odd character line is subject to is less than 6.
Effect of the invention can be further described by following emulation.
1. the condition of emulation experiment:
The present invention emulated on C++ platform obtain emulation data obtain simulation performance curve graph on Matlab platform.
The present invention is to the intersection write method on nand flash memory based on index modulation, the even-odd bit line nand flash memory side of writing
Method and full bit line nand flash memory write method compare emulation under different coupling strength factors.
2. emulation experiment content:
Emulation experiment 1, on nand flash memory in the intersection write method based on index modulation, by serious interference between unit
Odd character line on, the data of 1 bit are only written in each nand flash memory cell, the NAND on odd character line each at this time
Flash cell is all equivalent to a single layer nand flash memory cell.And interfered between unit on negligible even character line,
One group of every M=5 nand flash memory cell therefrom activates N=3 nand flash memory cell, to the nand flash memory cell of each activation
Using 16 layers of multi-level storage.The average data amount of storage of nand flash memory totality is 2 bits of every unit at this time.Odd even simultaneously
The data of 2 bits are written in every unit in bit line nand flash memory write method.The error performance of two kinds of write methods is compared, is tied
Fruit is as shown in figure 3, abscissa indicates that coupling strength factor, ordinate BER indicate bit error rate in Fig. 3.
When indicating to use the intersection write method on nand flash memory based on index modulation with the solid line that diamond shape indicates in Fig. 3,
The bit error rate performance simulation curve of nand flash memory cell in odd number character line.
It is indicated with the solid line that pentalpha indicates using the intersection write method based on index modulation on nand flash memory in Fig. 3
When, the bit error rate performance simulation curve of the nand flash memory cell in even number character line.
When indicating with the solid line that triangle indicates using even-odd bit line nand flash memory write method in Fig. 3, it is in even number
The bit error rate performance simulation curve of the nand flash memory cell of bit line.
When indicating with the solid line of circle mark using even-odd bit line nand flash memory write method in Fig. 3, it is in odd number ratio
The bit error rate performance simulation curve of the nand flash memory cell of special line；
As seen from Figure 3, it in the case where the intersection write method on using nand flash memory based on index modulation, is in
The reliability of the nand flash memory cell of odd number character line is gradually more than to use parity ratio with the continuous increase interfered between unit
The performance of odd bit line nand flash memory cell in special line nand flash memory write method.And it is in the nand flash memory of even number character line
Although every unit stores the data of 4 bits to unit, but can be ignored due to interfering between unit, so still can keep
Good error ratio characteristic, bit error rate performance are better than even-odd bit line nand flash memory write method always.
Emulation experiment 2, in order to more fully understand the error code of intersection write method of the nand flash memory based on index modulation
Can, the average bit error characteristic of nand flash memory cell is emulated below, and result and even-odd bit line nand flash memory are write
Method and full bit line nand flash memory write method are compared.As a result as shown in figure 4, abscissa indicates that coupling is strong in Fig. 4
Coefficient is spent, ordinate BER indicates bit error rate.
When being indicated with the solid line of circle mark using even-odd bit line nand flash memory write method in Fig. 4, nand flash memory list
The average error rate performance simulation curve of member.
It is indicated with the solid line that triangle indicates using the intersection write method based on index modulation on nand flash memory in Fig. 4
When, the average error rate performance simulation curve of nand flash memory cell.
When being indicated with the solid line that diamond shape indicates using full bit line nand flash memory write method in Fig. 4, nand flash memory cell
Average error rate performance simulation curve.
As seen from Figure 4, using the intersection write method on nand flash memory proposed by the present invention based on index modulation
The global reliability of nand flash memory cell is an advantage over using even-odd bit line nand flash memory write method.And as coupling is strong
Degree coefficient is gradually increased, and uses the nand flash memory cell average bit error of the intersection write method on nand flash memory based on index modulation
The case where rate characteristic has also gradually been more than using full bit line nand flash memory write method.
Claims (2)
1. the intersection write method on a kind of nand flash memory based on index modulation, specific steps include the following:
(1) erasing operation is carried out to nand flash memory cell:
The charge on nand flash memory cell, the nand flash memory cell wiped are removed by nand flash memory controller；
(2) nand flash memory cell wiped is written in the data being written into:
(2a) writes the nand flash memory cell on the odd character line wiped by step pulse write method line by line
Operation, obtains storing the data in nand flash memory cell；
(2b) after the completion of being write to the nand flash memory cell on the odd character line wiped, on the even character line wiped
Nand flash memory cell carries out compilation operation by index modulation write method line by line, obtains storing in nand flash memory cell
Data；
Specific step is as follows for the index modulation write method:
Step 1, the bit sequence u that formulation is entered to the nand flash memory cell on the even character line wiped are divided into bit sequence u1
With bit sequence u2；
Step 2 calculates the length of bit sequence u1 according to the following formula:
Wherein, K1Indicate the length of bit sequence u1, M indicates the number of the nand flash memory cell on the even character line wiped, N
Indicate that formulation enters the number of the nand flash memory cell on the even character line of data wiped, N=M/2, C (M, N) are indicated from M
The combined number of N number of flash cell is selected in flash cell,Expression takes maximum integer to operate, log2Indicate pair with 2 bottom of for
Number operation；
Step 3 calculates the length of bit sequence u2 according to the following formula:
K2=Nlog2L
Wherein, K2It indicates the length of bit sequence u2, is adopted on the nand flash memory cell for the even character line of L expression activation wiped
Voltage writes the number of plies；
Step 4, nand flash memory controller read the data of bit sequence u1, obtain formulation on the even character line wiped and enter data
Nand flash memory cell position；
Step 5, nand flash memory controller read the data of bit sequence u2, obtain the even character line wiped that formulation enters data
Nand flash memory cell threshold voltage, then by step pulse write method complete compilation operation；
(3) data stored in nand flash memory cell are read:
(3a) reads the voltage value on the nand flash memory cell of storing data by nand flash memory controller；
(3b) carries out the voltage value on the nand flash memory cell of the storing data of reading with threshold voltage when write-in data
Compare, obtain with read storing data nand flash memory cell on voltage value it is immediate write-in data when threshold voltage
Value；
Threshold voltage when the write-in data that (3c) nand flash memory controller is read is obtained and is stored in nand flash memory cell
Data.
2. the intersection write method on nand flash memory according to claim 1 based on index modulation, which is characterized in that step
Specific step is as follows for step pulse write method described in (2a):
Step 1, the reading data that the nand flash memory cell formulation on the odd character line wiped is entered to nand flash memory controller,
Obtain the threshold voltage of the nand flash memory cell；
Step 2, on odd character line plus a step voltage, to the nand flash memory cell on the odd character line wiped recycle into
The injection of row charge, and the voltage value of the nand flash memory cell is compared with threshold voltage, when the electricity of the nand flash memory cell
After pressure value reaches threshold voltage, terminate compilation operation.
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| US7251160B2 (en) * | 2005-03-16 | 2007-07-31 | Sandisk Corporation | Non-volatile memory and method with power-saving read and program-verify operations |
| US8767459B1 (en) * | 2010-07-31 | 2014-07-01 | Apple Inc. | Data storage in analog memory cells across word lines using a non-integer number of bits per cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154450A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | A method for programming a nand flash memory device |
| CN103366818A (en) * | 2007-06-19 | 2013-10-23 | 三星电子株式会社 | Programming method of flash memory device |
| CN102568595A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Semiconductor memory device and method of operating the same |
| CN103377686A (en) * | 2012-04-24 | 2013-10-30 | 北京兆易创新科技股份有限公司 | Nand Flash memory and method for implementing continuous reading operation of Nand Flash memory |
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