CN106452372B - Low-noise preamplifier circuit for bio signal amplification - Google Patents

Abstract

The present invention relates to a kind of low-noise preamplifier circuits for bio signal amplification.The amplifier circuit includes: that input impedance improves module (1), chopping modulation module (2), feedback network module (3) and binary channels mutual conductance boster (4)；It includes first voltage follower (A1), second voltage follower (A2), tertiary voltage follower (A3) and the 4th voltage follower (A4) that input impedance, which improves module (1),；Chopping modulation module (2) includes the first chopping switch (CH1), the second chopping switch (CH2), third chopping switch (CH3), the 4th chopping switch (CH4), the 5th chopping switch (CH5), the 6th chopping switch (CH6), the 7th chopping switch (CH7) and the 8th chopping switch (CH8)；Feedback network module includes the first and second feedback networks；Binary channels mutual conductance boster (4) includes first passage mutual conductance boster and second channel mutual conductance boster.The embodiment of the present invention is able to solve bio signal low-noise amplifier in low-power consumption in application, input impedance is lower, the higher problem of noise efficient coefficient.

Description

Low-noise preamplifier circuit for bio signal amplification

Technical field

The invention belongs to technical field of integrated circuits, and in particular to it is a kind of for bio signal amplification low noise before put Big device circuit.

Background technique

Nowadays portable medical device, wireless body area network (Wireless Body Area Network, abbreviation WBAN) etc. Technology is receive more and more attention.More and more researchs are dedicated to bioelectrical signals obtaining the system integration to a core On piece, to realize the low-power consumption and micromation of the system.

As the bioelectrical signals of representative have the characteristics that amplitude is small, frequency is low using brain electricity, electrocardiosignal, thus they are to making an uproar Sound especially low-frequency noise is especially sensitive.In low-power consumption bioelectrical signals acquisition system, preamplifier performance it is excellent with The no quality for directly determining the signal got.And in the design of preamplifier, noiseproof feature is most important index One of.In order to promote the noiseproof feature of amplifier of creatures' physical electric signals device, wave chopping technology is used in considerable research at present.It cuts The principle of wave technology is that the low frequency signal that will first input is modulated to high frequency, then allows the high-frequency signal by amplifier, then will letter Number modulate back low frequency.In this way, it is still thus low frequency signal that bioelectrical signals, which have been modulated twice, and low-frequency noise is only modulated It is primary, thus it is located at high frequency, and then low-frequency noise can be eliminated using low-pass filter.

Referring to Figure 1, Fig. 1 is the electrical block diagram of the amplifier using wave chopping technology of the prior art.First cuts Wave switch CH01, the second chopping switch CH02 are modulated input signal, capacitor C01, C02, C03 and C04, pseudo- resistance Rp01, Rp02 form feedforward and feedback network.Trsanscondutance amplifier is its core, and specific structure refers to Fig. 2, and Fig. 2 is existing The electrical block diagram of the trsanscondutance amplifier of technology.The first transistor M1 is offset, for providing bias current, wherein the Two-transistor M2 and the 4th transistor M4, third transistor M3 and the 5th transistor M5 respectively constitute Differential Input pipe, put at this time Mutual conductance the sum of of the value equal to second transistor M2 and the 4th transistor M4 of the mutual conductance of big device, twice of about single metal-oxide-semiconductor. Pseudo- resistance Rp03, puppet resistance Rp04 are the pseudo- resistance that PMOS is constituted, the high impedance with G Ω~T Ω rank, by adjusting the 6th The grid voltage of transistor M6 realizes common-mode feedback.

However in these traditional low noise chopping modulation amplifiers, urgently optimize there are two key index: first is that putting The input impedance of big device, second is that the noise efficient coefficient of amplifier.In traditional structure shown in Fig. 1, collected low frequency is raw Object signal has been modulated to high frequency by the first chopping switch CH01 and then has passed through feed-forward capacitance C01, capacitor C02, entire amplifier Input impedance it is lower.And the dry electrode for acquiring bioelectrical signals has very high input impedance, usually to reach tens M Ω extremely M Ω up to a hundred, the input impedance of amplifier is too low to will cause serious gain loss.Noise efficient coefficient (noise Efficiency factor, abbreviation NEF) it is an other important indicator, expression formula is as follows:

Wherein, V_rms,inFor the equivalent input noise voltage of amplifier, I is quiescent current, and BW is-three dB bandwidth.Noise efficient The tradeoff of quiescent current and noise under the certain bandwidth of the conceptual description of coefficient, its value is lower shows under unit work consumptiom Noiseproof feature is better, limiting value 1.Noise efficient coefficient can be used to the power consumption noiseproof feature between more different amplifiers, This is particularly important in low power dissipation design.However traditional low noise chopping modulation amplifier is limited by structure, is difficult to continue Reduce noise efficient coefficient.

Summary of the invention

The purpose of the present invention is to provide a kind of low-noise preamplifier circuits for bio signal amplification, solve existing There is the noise efficient coefficient of low-noise amplifier higher, the problems such as input impedance is lower, there is low-power consumption, can be integrated etc. on piece Feature is suitable for the application such as wireless body area network, portable medical device.

An embodiment provides a kind of low-noise preamplifier circuit for bio signal amplification, packets Include: input impedance improves module 1, chopping modulation module 2, feedback network module 3 and binary channels mutual conductance boster 4；It is described It includes first voltage follower A1, second voltage follower A2, tertiary voltage follower A3 and the 4th that input impedance, which improves module 1, Voltage follower A4；The chopping modulation module 2 is opened including the first chopping switch CH1, the second chopping switch CH2, third copped wave Close CH3, the 4th chopping switch CH4, the 5th chopping switch CH5, the 6th chopping switch CH6, the 7th chopping switch (CH7) and the 8th Chopping switch (CH8)；The feedback network module includes the first feedback network and the second feedback network；The binary channels mutual conductance increases Strong amplifier 4 includes first passage mutual conductance boster and second channel mutual conductance boster；Wherein,

The non-inverting input terminal AVIN1 of the positive input electrical connection first passage of the first voltage follower A1, bears The first input end of the first chopping switch CH1 is electrically connected to input terminal and output end；The second voltage follower The inverting input terminal AVIN2 of the positive input electrical connection first passage of A2, negative input and its output end are electrically connected To the second input terminal of the first chopping switch CH1；The positive input electrical connection second of the tertiary voltage follower A3 The noninverting input BVIN1 in channel, negative input and its output end are electrically connected to the of the second chopping switch CH2 One input terminal；The inverting input terminal BVIN2 of the positive input electrical connection second channel of the 4th voltage follower A4, bears The second input terminal of the second chopping switch CH2 is electrically connected to input terminal and its output end；

The first output end and second output terminal of the first chopping switch CH1 is respectively electrically connected to first feedback net The first input end X1 of network and the second input terminal X2；The first output end and second output terminal of the second chopping switch CH2 point It is not electrically connected to the first input end X3 and the second input terminal X4 of second feedback network；The third chopping switch CH3's First output end and second output terminal are respectively electrically connected to the noninverting input AVIN1 and inverting input terminal of the first passage AVIN2 and its first output end and second output terminal are respectively electrically connected to the first input end X1 and of first feedback network Two input terminal X2；It is logical that the first input end and the second input terminal of the 4th chopping switch CH4 is respectively electrically connected to described second The noninverting input BVIN1 and inverting input terminal BVIN2 and its first output end and second output terminal in road are respectively electrically connected to institute State the first input end X3 and the second input terminal X4 of the second feedback network；

The first feedback end and the second feedback end of first feedback network are respectively electrically connected to the 7th chopping switch (CH7) output end of first input end and the second input terminal and first feedback network be electrically connected to the first passage across Lead the input terminal (AVIN1+, AVIN2+, AVIN3+, AVIN1-, AVIN2-, AVIN3-) of boster；Second feedback The first feedback end and the second feedback end of network are respectively electrically connected to the first input end and of the 8th chopping switch (CH8) The output end of two input terminals and second feedback network is electrically connected to the input terminal of the second channel mutual conductance boster (BVIN1+,BVIN2+,BVIN3+,BVIN1-,BVIN2-,BVIN3-)；

The the first output terminals A VO+ and second output terminal AVO- of the first passage mutual conductance boster are electrically connected To the first input end and the second input terminal of the 5th chopping switch CH5；The of the second channel mutual conductance boster One output end BVO+ and second output terminal BVO- is respectively electrically connected to the first input end and second of the 6th chopping switch CH6 Input terminal；And

The first output end and second output terminal of the 5th chopping switch CH5 are respectively electrically connected to the same phase of first passage Output terminals A VOUT1 and reversed-phase output AVOUT2；The first output end and second output terminal of the 6th chopping switch CH6 point It is not electrically connected to the in-phase output end BVOUT1 and reversed-phase output BVOUT2 of second channel；The 7th chopping switch CH7's First output end and second output terminal are respectively electrically connected to the in-phase output end AVOUT1 and reversed-phase output of first passage AVOUT2；The first input end and the second input terminal of the 8th chopping switch CH8 are respectively electrically connected to the same phase of second channel Output end BVOUT1 and reversed-phase output BVOUT2.

In one embodiment of the invention, the binary channels mutual conductance boster 4 includes the first PMOS tube MP1, the Two PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS Pipe MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS Pipe MP12, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the first pseudo- resistance R1, the second pseudo- resistance R2, third puppet resistance R3, the 4th pseudo- resistance R4 and the first current source I1；Wherein,

The first PMOS tube MP1, the second PMOS tube MP2, the 4th PMOS tube MP4, the 4th NMOS tube MN4, The second NMOS tube MN2 and the first NMOS tube MN1 are sequentially connected in series between voltage source VDD and ground terminal GND；Described Three PMOS tube MP3, the 5th PMOS tube MP5, the 5th NMOS tube MN5 and the third NMOS tube MN3 are sequentially connected in series in described First PMOS tube MP1 and the second PMOS tube MP2 concatenate at the node A to be formed with the first NMOS tube MN1 and described the Two NMOS tube MN2 are concatenated between the node B to be formed；The grid of the first PMOS tube MP1 inputs first passage bias voltage V_BIASA, second non-inverting input terminal of the grid of the second PMOS tube MP2 as the first passage mutual conductance boster AVIN2+, second inverting input terminal of the grid of the third PMOS tube MP3 as the first passage mutual conductance boster AVIN2-；The grid of the 4th PMOS tube MP4 and the grid of the 5th PMOS tube MP5 input the first external bias voltage (V_B1)；The first puppet resistance R1 and the second puppet resistance R2 are serially connected with the 4th PMOS tube MP4 and the 4th NMOS Pipe MN4 is concatenated and is concatenated at the node F to be formed at the node E to be formed with the 5th PMOS tube MP5 and the 5th NMOS tube MN5 Between and node E and node F respectively as the first passage mutual conductance boster reversed-phase output and in-phase output end； The grid of the 4th NMOS tube MN4 and the grid of the 5th NMOS tube MN5 input the second external bias voltage (V_B2)；Institute State third non-inverting input terminal AVIN3+ of the grid as the first passage mutual conductance boster of the second NMOS tube MN2, institute State third inverting input terminal AVIN3- of the grid as the first passage mutual conductance boster of third NMOS tube MN3；Institute The grid for stating the first NMOS tube MN1 is electrically connected to the first puppet resistance R1 and concatenates the node to be formed with the second puppet resistance R2 At M；

The 8th PMOS tube MP8, the 9th PMOS tube MP9, the 11st PMOS tube MP11, the 11st NMOS tube MN11, the 9th NMOS tube MN9 and the 8th NMOS tube MN8 are sequentially connected in series between voltage source VDD and ground terminal GND； The tenth PMOS tube MP10, the 12nd PMOS tube MP12, the 12nd NMOS tube MN12 and the tenth NMOS tube MN10 Be sequentially connected in series in the 8th PMOS tube MP8 and the 9th PMOS tube MP9 concatenate at the node N to be formed with the 9th NMOS Pipe MN9 and the 8th NMOS tube MN8 is concatenated between the node H to be formed；Described in the grid of the 9th PMOS tube MP9 is used as Described in the grid of third the non-inverting input terminal BVIN3+, the tenth PMOS tube MP10 of second channel mutual conductance boster are used as The third inverting input terminal BVIN3- of second channel mutual conductance boster；The grid of the 11st PMOS tube MP11 and described The grid of 12nd PMOS tube MP12 inputs the external bias voltage (V of third_B3)；The third puppet resistance R3 and the 4th puppet Resistance R4 be serially connected with the 11st PMOS tube MP11 and the 11st NMOS tube MN11 concatenate at the node I to be formed with it is described 12nd PMOS tube MP12 and the 12nd NMOS tube MN12 is concatenated between the node J to be formed and node I and node J distinguishes Reversed-phase output and in-phase output end as the second channel mutual conductance boster；The 11st NMOS tube MN11's The grid of grid and the 12nd NMOS tube MN12 input the 4th external bias voltage (V_B4)；The 9th NMOS tube MN9 Second non-inverting input terminal BVIN2+, the tenth NMOS tube MN10 of the grid as the second channel mutual conductance boster Second inverting input terminal BVIN2- of the grid as the second channel mutual conductance boster；The 8th PMOS tube MP8 Grid be electrically connected to the third puppet resistance R3 and concatenated at the node R to be formed with the 4th puppet resistance R4, the described 8th The grid of NMOS tube MN8 inputs second channel bias voltage V_BIASB；

The drain electrode of 6th NMOS tube (MN6) is electrically connected to the third PMOS tube (MP3) and the 5th PMOS tube (MP5) at the node D that concatenation is formed, the source electrode of the 6th NMOS tube (MN6) is electrically connected to one end of first current source (I1), First non-inverting input terminal (AVIN1+) of its grid as the first passage mutual conductance boster；7th NMOS tube (MN7) drain electrode is electrically connected to second PMOS tube (MP2) and is concatenated at the node C formed with the 4th PMOS tube (MP4), The source electrode of 7th NMOS tube (MN7) is electrically connected to one end of first current source (I1), and grid is as the first passage The first inverting input terminal (AVIN1-) of mutual conductance boster；The drain electrode of 6th PMOS tube (MP6) is electrically connected to described At the node K that 11st NMOS tube (MN11) and the 9th NMOS tube (MN9) concatenation are formed, the source of the 6th PMOS tube (MP6) Pole is electrically connected to the other end of first current source (I1), grid as the second channel mutual conductance boster One noninverting input (BVIN1+)；The drain electrode of 7th PMOS tube (MP7) is electrically connected to the 12nd NMOS tube (MN12) At the node L formed with the tenth NMOS tube (MN10) concatenation, the source electrode of the 7th PMOS tube (MP7) is electrically connected to described first The other end of current source (I1), first inverting input terminal of the grid as the second channel mutual conductance boster (BVIN1-)。

In one embodiment of the invention, described voltage follower A1, A2, A3, A4 include the 13rd PMOS tube MP13, 14th PMOS tube MP14, the 15th PMOS tube MP15, the 16th PMOS tube MP16, the 13rd NMOS tube MN13 and the 14th NMOS tube MN14；Wherein, the 13rd PMOS tube MP13, the 14th PMOS tube MP14, the 15th PMOS tube MP15 and the 13rd NMOS tube MN13 are sequentially connected in series between voltage source VDD and ground terminal GND；16th PMOS tube MP16 and the 14th NMOS tube MN14 are sequentially connected in series in the 14th PMOS tube MP14 and the 15th PMOS tube MP15 is concatenated at the node P to be formed between ground terminal GND；The grid input offset voltage of the 13rd PMOS tube MP13 The grid of VBIAS, the 14th PMOS tube MP14 input enable signal EN, and the grid of the 15th PMOS tube MP15 is electrically connected It is connected to input terminal AVIN1, AVIN2, BVIN1, BVIN2 of the low-noise preamplifier, the 13rd NMOS tube MN13 Grid and the grid of the 14th NMOS tube MN14 be electrically connected to the 15th PMOS tube MP15 and the described 13rd NMOS tube MN13 is concatenated at the node O to be formed, and the grid of the 16th PMOS tube MP16 is electrically connected to the 16th PMOS Pipe MP16 is concatenated with the 14th NMOS tube MN14 at the node Q to be formed and as described voltage follower A1, A2, A3, A4 Output end vo ut.

In one embodiment of the invention, the first chopping switch CH1 or described second chopping switch CH2 includes the 15 NMOS tube MN15, the 16th NMOS tube MN16, the 17th NMOS tube MN17 and the 18th NMOS tube MN18；Wherein,

The 15th NMOS tube MN15 is electrically connected to second chopping switch of the first chopping switch CH1 or described CH2 First input end and the second input terminal between and its grid input the 6th clock control signal CLKB2；16th NMOS Pipe MN16 is electrically connected to the second input terminal and the second output of second chopping switch of the first chopping switch CH1 or described CH2 Between end and its grid inputs the 5th clock control signal CLK2；The 17th NMOS tube MN17 is electrically connected to described first and cuts Between the first output end and second output terminal of second chopping switch of wave switch CH1 or described CH2 and when its grid input the 6th Clock signal CLKB2；The 18th NMOS tube MN18 is electrically connected to second copped wave of the first chopping switch CH1 or described Between the first input end of switch CH2 and the first output end and its grid inputs the 5th clock control signal CLK2.

In one embodiment of the invention, the 4th chopping switch CH4 of third chopping switch CH3 or described includes the 19 NMOS tube MN19, the 20th NMOS tube MN20, the 21st NMOS tube MN21 and the 22nd NMOS tube MN22；Wherein,

The 19th NMOS tube MN19 is electrically connected to the 4th chopping switch CH4 of third chopping switch CH3 or described First input end and the second input terminal between and its grid input the 4th clock control signal CLKB1；20th NMOS Pipe MN20 is electrically connected to the second input terminal and the second output of the 4th chopping switch CH4 of third chopping switch CH3 or described Between end and its grid inputs third clock control signal CLK1；The 21st NMOS tube MN21 is electrically connected to the third Between the first output end and second output terminal of 4th chopping switch CH4 of chopping switch CH3 or described and its grid inputs the 4th Clock control signal CLKB1；The 22nd NMOS tube MN22 is electrically connected to the third chopping switch CH3 or described 4th Between the first input end of chopping switch CH4 and the first output end and its grid inputs third clock control signal CLK1.

In one embodiment of the invention, the 5th chopping switch CH5, the 6th chopping switch CH6, described Seven chopping switch CH7 or described, 8th chopping switch CH8 include the 23rd NMOS tube MN23, the 24th NMOS tube MN24, 25th NMOS tube MN25 and the 26th NMOS tube MN26；Wherein,

The 23rd NMOS tube MN23 is electrically connected to 6th chopping switch of the 5th chopping switch CH5 or described Between the first input end of CH6 and the second input terminal and its grid input second clock controls signal CLKB0；Described 24th NMOS tube MN24 is electrically connected to the second input terminal and second of the 6th chopping switch CH6 of the 5th chopping switch CH5 or described Between output end and its grid inputs the first clock control signal CLK0；The 25th NMOS tube MN25 is electrically connected to described Between the first output end and second output terminal of 5th chopping switch CH5 or described, 6th chopping switch CH6 and its grid inputs Second clock controls signal CLKB0；The 26th NMOS tube MN26 is electrically connected to the 5th chopping switch CH5 or described Between the first input end and the first output end of 6th chopping switch CH6 and its grid inputs the first clock control signal CLK0.

In one embodiment of the invention, first feedback network include the 5th pseudo- resistance R5, the 6th pseudo- resistance R6, 7th puppet resistance R7, the 8th pseudo- resistance R8, the 9th pseudo- resistance R9, the tenth pseudo- resistance R10, the 11st pseudo- resistance R11, the 12nd puppet Resistance R12, the 13rd pseudo- resistance R13, the 14th pseudo- resistance R14, the 15th pseudo- resistance R15, the 16th pseudo- resistance R16, the tenth Seven pseudo- resistance R17, the 18th pseudo- resistance R18, the 19th pseudo- resistance R19, the 20th pseudo- resistance R20, the 21st pseudo- resistance R21, the 22nd pseudo- resistance R22, the 23rd pseudo- resistance R23, the 24th pseudo- resistance R24, the 25th pseudo- resistance R25, 26th pseudo- resistance R26, the 27th pseudo- resistance R27, the 28th pseudo- resistance R28, the 29th pseudo- resistance R29, third Ten pseudo- resistance R30, the 31st pseudo- resistance R31, the 32nd pseudo- resistance R32, the 33rd pseudo- resistance R33, the 34th puppet Resistance R34, the 35th pseudo- resistance R35, the 36th pseudo- resistance R36, first capacitor C1, the second capacitor C2, third capacitor C3, 4th capacitor C4, the 5th capacitor C5, the 6th capacitor C6, the 7th capacitor C7, the 8th capacitor C8, the 9th capacitor C9, the tenth capacitor C10, the 11st capacitor C11 and the 12nd capacitor C12；Wherein,

Described 5th pseudo- resistance R5, the 6th pseudo- resistance R6, the 7th puppet resistance R7 and the 8th pseudo- resistance R8 It is sequentially connected in series between the in-phase output end AVOUT1 and ground terminal GND of the first passage and the first passage mutual conductance enhances The third inverting input terminal AVIN3- of amplifier is electrically connected to the 5th puppet resistance R5 and concatenates shape with the 6th puppet resistance R6 At node at；Described 9th pseudo- resistance R9, the tenth pseudo- resistance R10, the 11st puppet resistance R11 and the described 12nd Pseudo- resistance R12 is sequentially connected in series between the reversed-phase output AVOUT2 and ground terminal GND of the first passage and described first leads to The third non-inverting input terminal AVIN3+ of road mutual conductance boster is electrically connected to the 9th puppet resistance R9 and the tenth pseudo- electricity Resistance R10 is concatenated at the node to be formed；

Described 13rd pseudo- resistance R13, the 14th pseudo- resistance R14, the 15th pseudo- resistance R15, the described tenth It is six pseudo- resistance R16, the 17th pseudo- resistance R17, the 18th pseudo- resistance R18, the 19th pseudo- resistance R19, described 20th pseudo- resistance R20, the 21st pseudo- resistance R21, the 22nd pseudo- resistance R22, the 23rd pseudo- electricity Resistance R23 and the 24th puppet resistance R24 is sequentially connected in series in-phase output end AVOUT1 and voltage source in the first passage Between VDD and the second inverting input terminal AVIN2- of the first passage mutual conductance boster is electrically connected to the 14th puppet Resistance R14 concatenated with the 15th puppet resistance R15 at the node to be formed and the first passage mutual conductance boster One inverting input terminal AVIN1- is electrically connected to the 21st puppet resistance R21 and concatenates shape with the 22nd puppet resistance R22 At node at；The 25th pseudo- resistance R25, the 26th pseudo- resistance R26, the 27th pseudo- resistance R27, Described 28th pseudo- resistance R28, the 29th pseudo- resistance R29, the 30th pseudo- resistance R30, the described 31st Pseudo- resistance R31, the 32nd pseudo- resistance R32, the 33rd pseudo- resistance R33, the 34th pseudo- resistance R34, The 35th puppet resistance R35 and the 36th puppet resistance R36 are sequentially connected in series in the anti-phase output of the first passage Between the AVOUT2 and voltage source VDD of end and the second non-inverting input terminal AVIN2+ of the first passage mutual conductance boster is electrically connected The 26th puppet resistance R26 is connected to concatenate with the 27th puppet resistance R27 at the node to be formed and described first logical First non-inverting input terminal AVIN1+ of road mutual conductance boster is electrically connected to the 33rd puppet resistance R33 and the third 14 pseudo- resistance R34s concatenate at the node to be formed；

The first capacitor C1 and the 7th capacitor C7, the second capacitor C2 and the 8th capacitor C8, described the Three capacitor C3 and the 9th capacitor C9 are sequentially connected in series the first input end X1 and described first in first feedback network Between the in-phase output end AVOUT1 in channel and the first non-inverting input terminal AVIN1+ of the first passage mutual conductance boster Be electrically connected to the first capacitor C1 concatenated at the node to be formed with the 7th capacitor C7 and the first passage mutual conductance enhancing Second non-inverting input terminal AVIN2+ of amplifier is electrically connected to the second capacitor C2 and concatenates with the 8th capacitor C8 to be formed At node and the third non-inverting input terminal AVIN3+ of the first passage mutual conductance boster is electrically connected to the third capacitor C3 is concatenated at the node to be formed with the 9th capacitor C9, the 4th capacitor C4 and the tenth capacitor C10, the 5th electricity Hold C5 and the 11st capacitor C11, the 6th capacitor C6 and the 12nd capacitor C12 is sequentially connected in series in described first Between second input terminal X2 of feedback network and the reversed-phase output AVOUT2 of the first passage and the first passage mutual conductance First inverting input terminal AVIN1- of boster is electrically connected to the 4th capacitor C4 and concatenates shape with the tenth capacitor C10 At node at and the second inverting input terminal AVIN2- of the first passage mutual conductance boster be electrically connected to the described 5th Capacitor C5 is concatenated at the node to be formed with the 11st capacitor C11 and the third of the first passage mutual conductance boster is anti- Phase input terminal AVIN3- is electrically connected to the 6th capacitor C6 and concatenates at the node to be formed with the 12nd capacitor C12.

In one embodiment of the invention, second feedback network includes the 37th pseudo- resistance R37, the 38th Pseudo- resistance R38, the 39th pseudo- resistance R39, the 40th pseudo- resistance R40, the 41st pseudo- resistance R41, the 42nd pseudo- resistance R42, the 43rd pseudo- resistance R43, the 44th pseudo- resistance R44, the 45th pseudo- resistance R45, the 46th pseudo- resistance R46, 47th pseudo- resistance R47, the 48th pseudo- resistance R48, the 49th pseudo- resistance R49, the 50th pseudo- resistance R50, the 50th One pseudo- resistance R51, the 52nd pseudo- resistance R52, the 53rd pseudo- resistance R53, the 54th pseudo- resistance R54, the 55th puppet Resistance R55, the 56th pseudo- resistance R56, the 57th pseudo- resistance R57, the 58th pseudo- resistance R58, the 59th pseudo- resistance R59, the 60th pseudo- resistance R60, the 61st pseudo- resistance R61, the 62nd pseudo- resistance R62, the 13rd capacitor C13, the 14th Capacitor C14, the 15th capacitor C15, the 16th capacitor C16, the 17th capacitor C17, the 18th capacitor C18, the 19th capacitor C19, the 20th capacitor C20, the 21st capacitor C21, the 22nd capacitor C22, the electricity of the 23rd capacitor C23 and the 24th Hold C24；Wherein,

The 37th puppet resistance R37 be serially connected with second channel in-phase output end BVOUT1 and the second channel across Third the inverting input terminal BVIN3-, the 38th puppet resistance R38 for leading boster are serially connected with the second channel Between reversed-phase output BVOUT2 and the third non-inverting input terminal BVIN3+ of the second channel mutual conductance boster；

It is the 39th pseudo- resistance R39, the 40th pseudo- resistance R40, the 41st pseudo- resistance R41, described 42nd pseudo- resistance R42, the 43rd pseudo- resistance R43, the 44th pseudo- resistance R44, the 45th puppet Resistance R45, the 46th pseudo- resistance R46, the 47th pseudo- resistance R47, the 48th pseudo- resistance R48, institute It states the 49th puppet resistance R49 and the 50th puppet resistance R50 is sequentially connected in series in the in-phase output end of the second channel Between BVOUT1 and ground terminal GND and the second inverting input terminal BVIN2- of the second channel mutual conductance boster is electrically connected To the 40th puppet resistance R40 concatenated at the node to be formed with the 41st puppet resistance R41 and the second channel across The the first inverting input terminal BVIN1- for leading boster is electrically connected to the 48th puppet resistance R48 and the described 49th Pseudo- resistance R49 is concatenated at the node to be formed；The 51st pseudo- resistance R51, the 52nd pseudo- resistance R52, described the 53 pseudo- resistance R53, the 54th pseudo- resistance R54, the 55th pseudo- resistance R55, the 56th pseudo- electricity Hinder R56, the 57th pseudo- resistance R57, the 58th pseudo- resistance R58, the 59th pseudo- resistance R59, described 60th pseudo- resistance R60, the 61st puppet resistance R61 and the 62nd puppet resistance R62 are sequentially connected in series in described the Between the reversed-phase output AVOUT2 and ground terminal GND in two channels and the second same phase of the second channel mutual conductance boster Input terminal BVIN2+ is electrically connected to the 52nd puppet resistance R52 and concatenates the section to be formed with the 53rd puppet resistance R53 At point and the first non-inverting input terminal BVIN1+ of the second channel mutual conductance boster is electrically connected to the described 60th pseudo- electricity Resistance R60 is concatenated at the node to be formed with the 61st puppet resistance R61；

The 13rd capacitor C13 and the 19th capacitor C19, the 14th capacitor C14 and the 20th electricity Hold C20, the 15th capacitor C15 and the 21st capacitor C21 are sequentially connected in series the in second feedback network Between one input terminal X3 and the in-phase output end BVOUT1 of the second channel and the second channel mutual conductance boster First non-inverting input terminal BVIN1+ is electrically connected to the 13rd capacitor C13 and concatenates the section to be formed with the 19th capacitor C19 At point and the second non-inverting input terminal BVIN2+ of the second channel mutual conductance boster is electrically connected to the 14th capacitor C14 is concatenated at the node to be formed with the 20th capacitor C20 and the same phase of third of the second channel mutual conductance boster Input terminal BVIN3+ is electrically connected to the 15th capacitor C15 and concatenates at the node to be formed with the 21st capacitor C21, institute State the 16th capacitor C16 and the 22nd capacitor C22, the 17th capacitor C17 and the 23rd capacitor C23, The 18th capacitor C18 and the 24th capacitor C24 is sequentially connected in series the second input in second feedback network It holds between the X4 and reversed-phase output BVOUT2 of the second channel and the first of the second channel mutual conductance boster is anti- Phase input terminal BVIN1- is electrically connected to the 16th capacitor C16 and concatenates at the node to be formed with the 22nd capacitor C22 And the second inverting input terminal BVIN2- of the second channel mutual conductance boster be electrically connected to the 17th capacitor C17 with The 23rd capacitor C23 is concatenated at the node to be formed and the third anti-phase input of the second channel mutual conductance boster End BVIN3- is electrically connected to the 18th capacitor C18 and concatenates at the node to be formed with the 24th capacitor C24.

The embodiment of the present invention has following advantage by the improvement of foregoing circuit structure:

1, noise efficient coefficient is improved, i.e., effective noise of step-down amplifier under same bias current.

2, improve input impedance, avoid the especially dry electrode of bioelectrode output impedance it is excessively high caused by gain Loss.All circuits of the present invention can integrate in the chips, and power consumption is applied less than 1 μ W in wearable device, wireless body area network etc. In can be used as preamplifier to acquire bio signal.

Detailed description of the invention

Fig. 1 is the electrical block diagram of the amplifier using wave chopping technology of the prior art；

Fig. 2 is the electrical block diagram of the trsanscondutance amplifier of the prior art；

Fig. 3 is a kind of circuit knot of low-noise preamplifier for bio signal amplification provided in an embodiment of the present invention Structure schematic diagram；

Fig. 4 is a kind of electrical block diagram of binary channels mutual conductance boster provided in an embodiment of the present invention；

Fig. 5 is a kind of electrical block diagram of voltage follower provided in an embodiment of the present invention；

Fig. 6 a-6c is a kind of electrical block diagram of chopping switch provided in an embodiment of the present invention；

Fig. 7 is a kind of time diagram of the control signal of chopping switch provided in an embodiment of the present invention；

Fig. 8 is a kind of first feedback network internal circuit configuration schematic diagram provided in an embodiment of the present invention；

Fig. 9 is a kind of second feedback network internal circuit configuration schematic diagram provided in an embodiment of the present invention；

Figure 10 is a kind of noise spectrum characteristics curve synoptic diagram of low-noise preamplifier provided in an embodiment of the present invention；

Figure 11 is a kind of input impedance characteristic curve synoptic diagram of low-noise preamplifier provided in an embodiment of the present invention.

Specific embodiment

In order to keep the technical problem to be solved in the present invention, technical solution and advantage clearer, below in conjunction with attached drawing and Specific implementation example is described in detail.The present invention for existing bio signal low-noise amplifier in low-power consumption in application, Input impedance is lower, the higher problem of noise efficient coefficient, and providing a kind of develop skill using input impedance enhances skill with mutual conductance The Low Noise and Low Frequency Amplifier of art.

Embodiment one

Fig. 3 is referred to, Fig. 3 is a kind of preposition amplification of low noise for bio signal amplification provided in an embodiment of the present invention The electrical block diagram of device.The low-noise preamplifier includes:

Input impedance improves module 1, for improving the input impedance of the low-noise preamplifier, to eliminate electrode resistance Resist excessive caused gain loss；

Chopping modulation module 2 improves module 1 with input impedance and connect, including chopping modulation submodule 21,22, for believing Number modulation, the low-frequency noise based on flicker noise is modulated onto high frequency, to realize point of noise and signal on frequency spectrum From rear class can be eliminated noise by low-pass filter；

Feedback network module 3 is connect with chopping modulation module 2, is made of capacitor and pseudo- resistance, pseudo- resistance is used for bilateral Road preamplifier 4 provides dc point, and capacitor is for determining feedback factor；

Binary channels mutual conductance boster 4 is connect with feedback network module 3, chopping modulation submodule 22.

Specifically, Fig. 4 is referred to, Fig. 4 is a kind of electricity of binary channels mutual conductance boster provided in an embodiment of the present invention Line structure schematic diagram.The binary channels mutual conductance boster 4 includes channel trsanscondutance amplifier and channel trsanscondutance amplifier；Channel across Leading amplifier includes PMOS tube MP1, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5, NMOS tube MN7, NMOS Pipe MN6, NMOS tube MN5, NMOS tube MN4, NMOS tube MN3, NMOS tube MN2, NMOS tube MN1, puppet resistance R1 and pseudo- resistance R2. Wherein,

The grid and channel bias voltage V of PMOS tube MP1_BIASAConnection；The source electrode of PMOS tube MP1 is connect with voltage source VDD； The drain electrode of PMOS tube MP1 is connect with the source electrode of the source electrode of PMOS tube MP2 and PMOS tube MP3；

The grid of PMOS tube MP2 is connect with the positive output end AVIN2+ of the first feedback network；The source electrode of PMOS tube MP2 with The drain electrode of PMOS tube MP1 connects；The drain electrode of PMOS tube MP2 is connect with the drain electrode of the source electrode of PMOS tube MP4 and NMOS tube MN7；

The grid of PMOS tube MP3 is connect with the negative output terminal AVIN2- of the first feedback network；The source electrode of PMOS tube MP3 with The drain electrode of PMOS tube MP1 connects；The drain electrode of PMOS tube MP3 is connect with the drain electrode of the source electrode of PMOS tube MP5 and NMOS tube MN6；

The grid of PMOS tube MP4 is connect with the grid of PMOS tube MP5, the first external bias voltage V of input_B1；PMOS tube The source electrode of MP4 is connect with the drain electrode of PMOS tube MP2；One end and NMOS tube MN4 of the drain electrode of PMOS tube MP4 and pseudo- resistance R1 Drain electrode connection；

The grid of PMOS tube MP5 is connect with the grid pole of PMOS tube MP4；The leakage of the source electrode and PMOS tube MP3 of PMOS tube MP5 Pole connection；The drain electrode of PMOS tube MP5 is connect with the drain electrode of one end of pseudo- resistance R2 and NMOS tube MN5；

The grid of NMOS tube MN7 is connect with the positive output end AVIN1+ of the first feedback network；The source electrode of NMOS tube MN7 with The connection of one end of the source electrode of NMOS tube MN6 and the first current source I1；The drain electrode of NMOS tube MN7 and the drain electrode of PMOS tube MP3 connect It connects；

The grid of NMOS tube MN6 is connect with the negative output terminal AVIN1- of the first feedback network；The source electrode of NMOS tube MN6 with The source electrode of NMOS tube MN7 connects；The drain electrode of NMOS tube MN6 is connect with the drain electrode of PMOS tube MP3；

The grid of NMOS tube MN5 is connect with the grid of NMOS tube MN4；The drain electrode of the source electrode and NMOS tube MN3 of NMOS tube MN5 Connection；The drain electrode of NMOS tube MN5 is connect with the drain electrode of PMOS tube MP5；

The grid of NMOS tube MN4 is connect with the grid of NMOS tube MN5, the second external bias voltage (V of input_B2)；NMOS The source electrode of pipe MN4 is connect with the drain electrode of NMOS tube MN2；The drain electrode of NMOS tube MN2 is connect with the drain electrode of PMOS tube MP5；

The grid of NMOS tube MN3 is connect with input AVIN3+；The source electrode of NMOS tube MN3 is connect with the source electrode of NMOS tube MN2； The drain electrode of NMOS tube MN3 is connect with the source electrode of NMOS tube MN5；

The grid of NMOS tube MN2 is connect with the third positive output end AVIN3- of first feedback network；NMOS tube MN2's Source electrode is connect with the source electrode of NMOS tube MN3；The drain electrode of NMOS tube MN2 is connect with the source electrode of NMOS tube MN4；

The grid of NMOS tube MN1 is connect with the other end of the other end of pseudo- resistance R1 and pseudo- resistance R2；NMOS tube MN1's Source electrode is connected to ground；The drain electrode of NMOS tube MN1 is connect with the source electrode of the source electrode of NMOS tube MN3 and NMOS tube MN2；

One end of pseudo- resistance R1 is connect with the drain electrode of PMOS tube MP4；The other end of pseudo- resistance R1 is another with pseudo- resistance R2's End connection；

One end of pseudo- resistance R2 is connect with the drain electrode of PMOS tube MP5；The other end of pseudo- resistance R2 is another with pseudo- resistance R1's End connection；

Second channel trsanscondutance amplifier includes NMOS tube MN8, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11, NMOS Pipe MN12, PMOS tube MP6, PMOS tube MP7, PMOS tube MP12, PMOS tube MP11, PMOS tube MP10, PMOS tube MP9, PMOS tube MP8, puppet resistance R3 and pseudo- resistance R4.Wherein,

The grid and second channel bias voltage V of NMOS tube MN8_BIASBConnection；The source electrode and ground terminal GND of NMOS tube MN8 Connection；The drain electrode of NMOS tube MN8 is connect with the source electrode of the source electrode of NMOS tube MN9 and NMOS tube MN10；

The grid of NMOS tube MN9 is connect with the second positive output end BVIN2+ of the second feedback network；The source electrode of NMOS tube MN9 It is connect with the drain electrode of NMOS tube MN8；The drain electrode of NMOS tube MN9 and the drain electrode of the source electrode of NMOS tube MN11 and PMOS tube MP6 connect It connects；

The grid of NMOS tube MN10 is connect with the second negative output terminal BVIN2- of the second feedback network；The source of PMOS tube MP3 Pole is connect with the drain electrode of NMOS tube MN12；The leakage of the drain electrode of NMOS tube MN12 and the source electrode of NMOS tube MN12 and PMOS tube MP7 Pole connection；

The grid of NMOS tube MN11 is connect with the grid of NMOS tube MN12；The source electrode of NMOS tube MN11 and four NMOS tube MN9 Drain electrode connection；The drain electrode of NMOS tube MN11 is connect with the drain electrode of one end of pseudo- resistance R3 and PMOS tube MP11；.

The grid of NMOS tube MN12 is connect with the grid pole of NMOS tube MN11, the 4th external bias voltage V of input_B4； The source electrode of NMOS tube MN12 is connect with the drain electrode of NMOS tube MN10；One end of the drain electrode of NMOS tube MN12 and pseudo- resistance R4 and The drain electrode of PMOS tube MP12 connects；

The grid of PMOS tube MP6 is connect with the first positive output end BVIN1+ of the second feedback network；The source electrode of PMOS tube MP6 It is connect with the other end of the source electrode of PMOS tube MP7 and the first current source I1；The drain electrode of PMOS tube MP6 and the leakage of NMOS tube MN9 Pole connection；

The grid of PMOS tube MP7 is connect with the first negative output terminal BVIN1- of the second feedback network；The source electrode of PMOS tube MP7 It is connect with the other end of the source electrode of PMOS tube MP6 and the first current source I1；The drain electrode of PMOS tube MP7 and the leakage of PMOS tube MP10 Pole connection；

The grid of PMOS tube MP12 is connect with the grid of PMOS tube MP11；The source electrode of PMOS tube MP12 is with PMOS tube MP10's Drain electrode connection；The drain electrode of PMOS tube MP12 is connect with the drain electrode of NMOS tube MN12；

The grid of PMOS tube MP11 is connect with the grid of PMOS tube MP12, the input external bias voltage V of third_B3；PMOS The source electrode of pipe MP11 is connect with the drain electrode of PMOS tube MP9；The drain electrode of PMOS tube MP11 is connect with the drain electrode of NMOS tube MN11；

The grid of PMOS tube MP10 is connect with input BVIN3-；The source electrode of PMOS tube MP10 and the source electrode of PMOS tube MP9 connect It connects；The drain electrode of PMOS tube MP10 is connect with the source electrode of PMOS tube MP11；

The grid of PMOS tube MP9 is connect with the third negative output terminal BVIN3- of the second feedback network；The source electrode of PMOS tube MP9 It is connect with the source electrode of PMOS tube MP10；The drain electrode of PMOS tube MP9 is connect with the source electrode of PMOS tube MP12；

The grid of PMOS tube MP8 is connect with the other end of the other end of pseudo- resistance R3 and pseudo- resistance R4；PMOS tube MP8's Source electrode is connect with power vd D；The drain electrode of PMOS tube MP8 is connect with the source electrode of the source electrode of PMOS tube MP10 and PMOS tube MP9；

One end of pseudo- resistance R3 is connect with the drain electrode of NMOS tube MN11；The other end of pseudo- resistance R3 is another with pseudo- resistance R4's End connection；

One end of pseudo- resistance R4 is connect with the drain electrode of NMOS tube MN12；The other end of pseudo- resistance R3 is another with pseudo- resistance R4's End connection；

First current source I1 is double-ended current source.Wherein one end is connected with NMOS tube MN6 with NMOS tube MN7；The other end and PMOS tube MP6, PMOS tube MP7 connection.

Fig. 5 is referred to, Fig. 5 is a kind of electrical block diagram of voltage follower provided in an embodiment of the present invention.The electricity Press follower A1, A2, A3, A4, comprising: PMOS tube MP13, PMOS tube MP14, PMOS tube MP15, PMOS tube MP16, NMOS tube MN13 and NMOS tube MN14, wherein

The grid of PMOS tube MP13 is connect with bias voltage VBIAS；The source electrode of PMOS tube MP13 is connect with voltage source VDD； The drain electrode of PMOS tube MP13 is connect with the source electrode of PMOS tube MP14；

The grid of PMOS tube MP14 is connect with enable signal EN；The drain electrode of the source electrode and PMOS tube MP13 of PMOS tube MP14 connects It connects；The drain electrode of PMOS tube MP14 is connect with the source electrode of the source electrode of PMOS tube MP15 and PMOS tube MP16；

The grid of PMOS tube MP15 is connect with input Vin (i.e. AVIN1/AVIN2/BVIN1/BVIN2)；PMOS tube MP15's Source electrode is connect with the drain electrode of PMOS tube MP14；The drain electrode of PMOS tube MP15 and the drain electrode of NMOS tube MN13 and NMOS tube MN13's Grid connection；

The grid of PMOS tube MP16 is connect with the drain electrode of PMOS tube MP16 and output Vout；The source electrode of PMOS tube MP16 with The drain electrode of PMOS tube MP14 connects；The drain electrode of PMOS tube MP16 is connect with the grid of PMOS tube MP16；

The grid of NMOS tube MN13 is connect with the drain electrode of the grid of NMOS tube MN14 and NMOS tube MN13；NMOS tube MN13 Source electrode connect with ground terminal GND；The drain electrode of NMOS tube MN13 is connect with the grid of NMOS tube MN13；

The grid of NMOS tube MN14 is connect with the grid of NMOS tube MN13；The source electrode of NMOS tube MN13 is connected to ground；NMOS The drain electrode of pipe MN13 is connect with the drain electrode of NMOS tube MN13.

Fig. 6 a-6c is referred to, Fig. 6 a-6c is a kind of circuit structure signal of chopping switch provided in an embodiment of the present invention Figure.Channel C H1/CH2 includes: NMOS tube MN15, NMOS tube MN16, NMOS tube MN17 and NMOS tube MN18, wherein

The grid of NMOS tube MN15 is connect with CLKB2；The source electrode of NMOS tube MN15 is connect with the source electrode of NMOS tube MN18； The drain electrode of NMOS tube MN15 is connect with the source electrode of NMOS tube MN16；

The grid of NMOS tube MN16 is connect with CLK2；The source electrode of NMOS tube MN16 is connect with the drain electrode of NMOS tube MN15； The drain electrode of NMOS tube MN16 is connect with the drain electrode of NMOS tube MN17；

The grid of NMOS tube MN17 is connect with CLKB2；The source electrode of NMOS tube MN17 is connect with the drain electrode of NMOS tube MN18； The drain electrode of NMOS tube MN17 is connect with the drain electrode of NMOS tube MN16；

The grid of NMOS tube MN18 is connect with CLK2；The source electrode of NMOS tube MN18 is connect with the source electrode of NMOS tube MN15； The drain electrode of NMOS tube MN18 is connect with the source electrode of NMOS tube MN17.

Channel C H3/CH4 includes: NMOS tube MN19, NMOS tube MN20, NMOS tube MN22 and NMOS tube MN21, wherein

The grid of NMOS tube MN19 is connect with CLKB1；The source electrode of NMOS tube MN19 is connect with the source electrode of NMOS tube MN22； The drain electrode of NMOS tube MN19 is connect with the source electrode of NMOS tube MN20；

The grid of NMOS tube MN20 is connect with CLK1；The source electrode of NMOS tube MN20 is connect with the drain electrode of NMOS tube MN19； The drain electrode of NMOS tube MN20 is connect with the drain electrode of NMOS tube MN21；

The grid of NMOS tube MN21 is connect with CLKB1；The source electrode of NMOS tube MN21 is connect with the drain electrode of NMOS tube MN22； The drain electrode of NMOS tube MN21 is connect with the drain electrode of NMOS tube MN20；

The grid of NMOS tube MN22 is connect with CLK1；The source electrode of NMOS tube MN22 is connect with the source electrode of NMOS tube MN19； The drain electrode of NMOS tube MN22 is connect with the source electrode of NMOS tube MN21.

Channel C H3/CH4 includes: NMOS tube MN23, NMOS tube MN24, NMOS tube MN25 and NMOS tube MN26, wherein

The grid of NMOS tube MN23 is connect with CLKB0；The source electrode of NMOS tube MN23 is connect with the source electrode of NMOS tube MN26； The drain electrode of NMOS tube MN23 is connect with the source electrode of NMOS tube MN24；

The grid of NMOS tube MN24 is connect with CLK0；The source electrode of NMOS tube MN24 is connect with the drain electrode of NMOS tube MN23； The drain electrode of NMOS tube MN24 is connect with the drain electrode of NMOS tube MN25；

The grid of NMOS tube MN25 is connect with CLKB0；The source electrode of NMOS tube MN25 is connect with the drain electrode of body pipe MN26；NMOS The drain electrode of pipe MN25 is connect with the drain electrode of NMOS tube MN24；

The grid of NMOS tube MN26 is connect with CLK0；The source electrode of NMOS tube MN26 is connect with the source electrode of NMOS tube MN23； The drain electrode of NMOS tube MN26 is connect with the source electrode of NMOS tube MN25.

Fig. 7 is referred to, Fig. 7 is a kind of time diagram of the control signal of chopping switch provided in an embodiment of the present invention. It is applied in example above-mentioned, CLK0 and CLKB0 are 50% duty ratio square waves of opposite in phase, are cut for the first chopping switch CH1 and second Wave switch CH2 provides clock control signal；In order to improve the input impedance of amplifier, the square wave of 50% duty ratio is resolved into CLK1,CLKB1,CLK2,CLKB2.Wherein, the 45% duty ratio square wave that CLK1 and CLKB1 are, be third chopping switch CH3 and 4th chopping switch CH4 provides clock control signal；The 5% duty ratio square wave that CLK2 and CLKB2 are is the 5th chopping switch CH5 and the 6th chopping switch CH6 provides clock control signal.When clock control signal is set to high level, by voltage follower Input charge is provided, rather than directly obtains charge from input terminal (bioelectrode), to improve the input impedance of amplifier.

Fig. 8 is referred to, Fig. 8 is a kind of first feedback network internal circuit configuration schematic diagram provided in an embodiment of the present invention. In the present embodiment, feedback capacity is capacitor above-mentioned, and such as the first feedback capacity C1 is the above-mentioned first capacitor C1 referred to.

One end of the first feedback capacity C1 is connect with the first input end X1 of the first feedback network；First feedback The other end of capacitor C1 is connect with the first non-inverting input terminal AVIN1+ of first passage mutual conductance boster.

One end of the second feedback capacity C2 is connect with the first input end X1 of the first feedback network；Second feedback The other end of capacitor C2 is connect with the second non-inverting input terminal AVIN2+ of first passage mutual conductance boster.

One end of the third feedback capacity C3 is connect with the first input end X1 of the first feedback network；The third feedback The other end of capacitor C3 is connect with the third non-inverting input terminal AVIN3+ of first passage mutual conductance boster.

One end of the 4th feedback capacity C4 is connect with the second input terminal X2 of the first feedback network；4th feedback The other end of capacitor C4 is connect with the first inverting input terminal AVIN1- of first passage mutual conductance boster.

One end of the 5th feedback capacity C5 is connect with the second input terminal X2 of the first feedback network；5th feedback The other end of capacitor C5 is connect with the second inverting input terminal AVIN2- of first passage mutual conductance boster.

One end of the 6th feedback capacity C6 is connect with the second input terminal X2 of the first feedback network；6th feedback The other end of capacitor C6 is connect with the third inverting input terminal AVIN3- of first passage mutual conductance boster.

One end of the 7th feedback capacity C7 is used for the first of the low-noise preamplifier of bio signal amplification with this The first output terminals A VOUT1 connection in channel；The other end and first passage mutual conductance boster of the 7th feedback capacity C7 The first non-inverting input terminal AVIN1+ connection.

One end of the 8th feedback capacity C8 is used for the first of the low-noise preamplifier of bio signal amplification with this The first output terminals A VOUT1 connection in channel；The other end and first passage mutual conductance boster of the 8th feedback capacity C8 The second non-inverting input terminal AVIN2+ connection.

One end of the 9th feedback capacity C9 is used for the first of the low-noise preamplifier of bio signal amplification with this The first output terminals A VOUT1 connection in channel；The other end and first passage mutual conductance boster of the 9th feedback capacity C9 The AVIN3+ connection of third non-inverting input terminal.

One end of the tenth feedback capacity C10 is used for the first of the low-noise preamplifier of bio signal amplification with this The second output terminal AVOUT2 connection in channel；The other end of the tenth feedback capacity C10 and first passage mutual conductance enhancing are amplified First inverting input terminal AVIN1- connection of device.

One end of the 11st feedback capacity C11 is used for the of the low-noise preamplifier of bio signal amplification with this The second output terminal AVOUT2 connection in one channel；The other end of the 11st feedback capacity C11 and first passage mutual conductance enhance Second inverting input terminal AVIN2- connection of amplifier.

One end of the 12nd feedback capacity C12 is used for the of the low-noise preamplifier of bio signal amplification with this The first output terminals A VOUT2 connection in one channel；The other end of the 12nd feedback capacity C12 and first passage mutual conductance enhance The third inverting input terminal AVIN3- connection of amplifier.

First that one end of described 5th pseudo- resistance R5 is used for the low-noise preamplifier of bio signal amplification with this is led to The first output terminals A VOUT1 connection in road；The of the other end of the 5th pseudo- resistance R5 and first passage mutual conductance boster Three inverting input terminal AVIN3- connections.

One end of described 6th pseudo- resistance R6 and the third inverting input terminal AVIN3- of first passage mutual conductance boster Connection；The other end of described 6th pseudo- resistance R6 is connect with one end of the 7th pseudo- resistance R7.

One end of described 7th pseudo- resistance R7 is connect with the other end of the 6th pseudo- resistance R6；The phase puppet resistance R7's is another One end is connect with one end of the 8th pseudo- resistance R8.

One end of described 8th pseudo- resistance R8 is connect with the other end of the 7th pseudo- resistance R7；Described 7th pseudo- resistance R7's is another One end is connect with GND.

First that one end of described 9th pseudo- resistance R9 is used for the low-noise preamplifier of bio signal amplification with this is led to The second output terminal AVOUT2 connection in road；The of the other end of the 9th pseudo- resistance R9 and first passage mutual conductance boster Three non-inverting input terminal AVIN3+ connections.

One end of described tenth pseudo- resistance R10 and the third non-inverting input terminal AVIN3+ of first passage mutual conductance boster Connection；The other end of described tenth pseudo- resistance R10 is connect with one end of the 11st pseudo- resistance R11.

One end of described 11st pseudo- resistance R11 is connect with the other end of the tenth pseudo- resistance R10；Described 11st pseudo- resistance The other end of R11 is connect with one end of the 12nd pseudo- resistance R12.

One end of described 12nd pseudo- resistance R12 is connect with the other end of the 11st pseudo- resistance R11；Described 12nd pseudo- electricity The other end of resistance R12 is connect with ground terminal GND.

One end of described 13rd pseudo- resistance R13 is used for the first of the low-noise preamplifier of bio signal amplification with this The first output terminals A VOUT1 connection in channel；One end of the other end of described 13rd pseudo- resistance R13 and the 14th pseudo- resistance R14 Connection.

One end of described 14th pseudo- resistance R14 is connect with the other end of the 13rd pseudo- resistance R13；Described 14th pseudo- electricity The other end of resistance R14 is connect with the second inverting input terminal AVIN2- of first passage mutual conductance boster.

One end of described 15th pseudo- resistance R15 and the second inverting input terminal of first passage mutual conductance boster AVIN2- connection；The other end of described 15th pseudo- resistance R15 is connect with one end of the 16th pseudo- resistance R16.

One end of described 16th pseudo- resistance R16 is connect with the other end of the 15th pseudo- resistance R15；Described 16th pseudo- electricity The other end for hindering R16 is connect with one end of the 17th pseudo- resistance R17.

One end of described 17th pseudo- resistance R17 is connect with the other end of the 16th pseudo- resistance R16；Described 17th pseudo- electricity The other end for hindering R17 is connect with one end of the 18th pseudo- resistance R18.

One end of described 18th pseudo- resistance R18 is connect with the other end of the 17th pseudo- resistance R17；Described 18th pseudo- electricity The other end for hindering R18 is connect with one end of the 19th pseudo- resistance R19.

One end of described 19th pseudo- resistance R19 is connect with the other end of the 18th pseudo- resistance R18；Described 19th pseudo- electricity The other end for hindering R19 is connect with one end of the 20th pseudo- resistance R20.

One end of described 20th pseudo- resistance R20 is connect with the other end of the 19th pseudo- resistance R19；Described 20th pseudo- electricity The other end for hindering R20 is connect with one end of the 21st pseudo- resistance R21.

One end of described 21st pseudo- resistance R21 is connect with the other end of the 20th pseudo- resistance R20；Described 21st The other end of pseudo- resistance R21 is connect with the first inverting input terminal AVIN1- of first passage mutual conductance boster.

One end of described 22nd pseudo- resistance R22 and the second inverting input terminal of first passage mutual conductance boster AVIN1- connection；The other end of described 22nd pseudo- resistance R22 is connect with one end of the 23rd pseudo- resistance R23.

One end of described 23rd pseudo- resistance R23 is connect with the other end of the 22nd pseudo- resistance R22；Described 20th The other end of three pseudo- resistance R23 is connect with one end of the 24th pseudo- resistance R24.

One end of described 24th pseudo- resistance R24 is connect with the other end of the 23rd pseudo- resistance R23；Described 20th The other end of four pseudo- resistance R24 is connect with power vd D.

One end of the 25th pseudo- resistance R25 and this be used for the of the low-noise preamplifier that bio signal amplifies The second output terminal AVOUT2 connection in one channel；The other end of described 25th pseudo- resistance R25 and the 26th pseudo- resistance R26 One end connection.

One end of described 26th pseudo- resistance R26 is connect with the other end of the 25th pseudo- resistance R25；Described 20th The other end of six pseudo- resistance R26 is connect with the second non-inverting input terminal AVIN2+ of first passage mutual conductance boster.

One end of described 27th pseudo- resistance R27 and the second non-inverting input terminal of first passage mutual conductance boster AVIN2+ connection；The other end of described 27th pseudo- resistance R27 is connect with one end of the 28th pseudo- resistance R28.

One end of described 28th pseudo- resistance R28 is connect with the other end of the 27th pseudo- resistance R27；Described 20th The other end of eight pseudo- resistance R28 is connect with one end of the 27th pseudo- resistance R27.

One end of described 29th pseudo- resistance R29 is connect with the other end of the 28th pseudo- resistance R28；Described 20th The other end of nine pseudo- resistance R29 is connect with one end of the 30th pseudo- resistance R30.

One end of described 30th pseudo- resistance R30 is connect with the other end of the 29th pseudo- resistance R29；Described 30th is pseudo- The other end of resistance R30 is connect with one end of the 31st pseudo- resistance R31.

One end of described 31st pseudo- resistance R31 is connect with the other end of the 30th pseudo- resistance R30；Described 31st The other end of pseudo- resistance R31 is connect with one end of the 32nd pseudo- resistance R32.

One end of described 32nd pseudo- resistance R32 is connect with the other end of the 31st pseudo- resistance R31；Described 30th The other end of two pseudo- resistance R32 is connect with one end of the 33rd pseudo- resistance R33.

One end of described 33rd pseudo- resistance R33 is connect with the other end of the 32nd pseudo- resistance R32；Described 30th The other end of three pseudo- resistance R33 is connect with the first non-inverting input terminal AVIN1+ of first passage mutual conductance boster.

One end of described 34th pseudo- resistance R34 and the second non-inverting input terminal of first passage mutual conductance boster AVIN1+ connection；The other end of described 34th pseudo- resistance R34 is connect with one end of the 35th pseudo- resistance R35.

One end of described 35th pseudo- resistance R35 is connect with the other end of the 34th pseudo- resistance R34；Described 30th The other end of five pseudo- resistance R35 is connect with one end of the 36th pseudo- resistance R36.

One end of described 36th pseudo- resistance R36 is connect with the other end of the 35th pseudo- resistance R35；Described 30th The other end of six pseudo- resistance R36 is connect with power vd D.

Referring to Fig. 9, Fig. 9 is a kind of first feedback network internal circuit configuration schematic diagram provided in an embodiment of the present invention.? It is above-mentioned to apply in example,

One end of the 13rd feedback capacity C13 is connect with the first input end X3 of the second feedback network；Described tenth The other end of three feedback capacity C13 is connect with the first non-inverting input terminal BVIN1+ of second channel mutual conductance boster.

One end of the 14th feedback capacity C14 is connect with the first input end X3 of the second feedback network；Described tenth The other end of four feedback capacity C14 is connect with the second non-inverting input terminal BVIN2+ of second channel mutual conductance boster.

One end of the 15th feedback capacity C15 is connect with the first input end X1 of the second feedback network；Described tenth The other end of five feedback capacity C15 is connect with the third non-inverting input terminal BVIN3+ of second channel mutual conductance boster.

One end of the 16th feedback capacity C16 is connect with the second input terminal X4 of the second feedback network；Described tenth The other end of six feedback capacity C16 is connect with the first inverting input terminal BVIN1- of second channel mutual conductance boster.

One end of the 17th feedback capacity C17 is connect with the second input terminal X4 of the second feedback network；Described tenth The other end of seven feedback capacity C17 is connect with the second inverting input terminal BVIN2- of second channel mutual conductance boster.

One end that the eighteen incompatibilities feed holds C18 is connect with the second input terminal X4 of the second feedback network；Described tenth The other end of eight feedback capacity C18 is connect with the third inverting input terminal BVIN3- of second channel mutual conductance boster.

One end of the 19th feedback capacity C19 is used for the of the low-noise preamplifier of bio signal amplification with this The first output end BVOUT1 connection in two channels；The other end of the 19th feedback capacity C19 and second channel mutual conductance enhance The first input end BVIN1+ connection of amplifier.

One end of the 20th feedback capacity C20 is used for the of the low-noise preamplifier of bio signal amplification with this The first output end BVOUT1 connection in two channels；The other end of the 20th feedback capacity C20 and second channel mutual conductance enhance Second non-inverting input terminal BVIN2+ connection of amplifier.

One end of the 21st feedback capacity C21 is used for the low-noise preamplifier of bio signal amplification with this First output end BVOUT1 connection of second channel；The other end of the 21st feedback capacity C21 and second channel mutual conductance The third non-inverting input terminal BVIN3+ connection of boster.

One end of the 22nd feedback capacity C22 is used for the low-noise preamplifier of bio signal amplification with this The second output terminal BVOUT2 connection of second channel；The other end of the 22nd feedback capacity C22 and second channel mutual conductance First inverting input terminal BVIN1- connection of boster.

One end of the 23rd feedback capacity C23 is used for the low-noise preamplifier of bio signal amplification with this The second output terminal BVOUT2 connection of second channel；The other end of the 23rd feedback capacity C23 and second channel mutual conductance Second inverting input terminal BVIN2- connection of boster.

One end of the 24th feedback capacity C24 is used for the low-noise preamplifier of bio signal amplification with this First output end BVOUT2 connection of second channel；The other end of the 24th feedback capacity C24 and second channel mutual conductance The third inverting input terminal BVIN3- connection of boster.

One end of the 37th pseudo- resistance R37 and this be used for the of the low-noise preamplifier that bio signal amplifies The first output end BVOUT1 connection in two channels；The other end of described 37th pseudo- resistance R37 and second channel mutual conductance enhance The third inverting input terminal BVIN3- connection of amplifier.

One end of the 38th pseudo- resistance R38 and this be used for the of the low-noise preamplifier that bio signal amplifies The second output terminal BVOUT2 connection in two channels；The other end of described 38th pseudo- resistance R38 and second channel mutual conductance enhance The third non-inverting input terminal BVIN3+ connection of amplifier.

One end of the 39th pseudo- resistance R39 and this be used for the of the low-noise preamplifier that bio signal amplifies The first output end BVOUT1 connection in two channels；The other end of the 39th pseudo- resistance R39 is with the 40th puppet resistance R40's One end connection.

One end of described 40th pseudo- resistance R40 is connect with the other end of the 40th pseudo- resistance R40；Described 40th pseudo- electricity The other end of resistance R40 is connect with the second inverting input terminal BVIN2- of second channel mutual conductance boster.

One end of described 41st pseudo- resistance R41 and the second inverting input terminal of second channel mutual conductance boster BVIN2- connection；The other end of described 41st pseudo- resistance R41 is connect with one end of the 42nd pseudo- resistance R42.

One end of described 42nd pseudo- resistance R42 is connect with the other end of the 41st pseudo- resistance R41；Described 40th The other end of two pseudo- resistance R42 is connect with one end of the 43rd pseudo- resistance R43.

One end of described 43rd pseudo- resistance R43 is connect with the other end of the 42nd pseudo- resistance R43；Described 40th The other end of three pseudo- resistance R43 is connect with one end of the 44th pseudo- resistance R44.

One end of described 44th pseudo- resistance R44 is connect with the other end of the 43rd pseudo- resistance R43；Described 40th The other end of four pseudo- resistance R44 is connect with one end of the 45th pseudo- resistance R45.

One end of described 45th pseudo- resistance R45 is connect with the other end of the 44th pseudo- resistance R44；Described 40th The other end of five pseudo- resistance R45 is connect with one end of the 46th pseudo- resistance R46.

One end of described 46th pseudo- resistance R46 is connect with the other end of the 45th pseudo- resistance R45；Described 40th The other end of six pseudo- resistance R46 is connect with one end of the 47th pseudo- resistance R47.

One end of described 47th pseudo- resistance R47 is connect with the other end of the 46th pseudo- resistance R46；Described 40th The other end of seven pseudo- resistance R47 is connect with one end of the 48th pseudo- resistance R48.

One end of described 48th pseudo- resistance R48 is connect with the other end of the 47th pseudo- resistance R47；Described 40th The eight pseudo- resistance R48 other ends are connect with the first inverting input terminal BVIN1- of second channel mutual conductance boster.

One end of described 49th pseudo- resistance R49 and the first inverting input terminal of second channel mutual conductance boster BVIN1- connection；The other end of described 49th pseudo- resistance R49 is connect with one end of the 50th pseudo- resistance R50.

One end of described 50th pseudo- resistance R50 is connect with the other end of the 49th pseudo- resistance R49；Described 50th is pseudo- The other end of resistance R50 is connect with ground terminal GND.

One end of the 51st pseudo- resistance R51 and this be used for the of the low-noise preamplifier that bio signal amplifies The second output terminal BVOUT2 connection in two channels；The other end of described 51st pseudo- resistance R51 and the 52nd pseudo- resistance R52 One end connection.

One end of described 52nd pseudo- resistance R52 is connect with the other end of the 51st pseudo- resistance R51；Described 50th The other end of two pseudo- resistance R52 is connect with the second non-inverting input terminal BVIN2+ of second channel mutual conductance boster.

One end of described 53rd pseudo- resistance R41 and the second non-inverting input terminal of second channel mutual conductance boster BVIN2+ connection；The other end of described 53rd pseudo- resistance R53 is connect with one end of the 54th pseudo- resistance R54.

One end of described 54th pseudo- resistance R54 is connect with the other end of the 53rd pseudo- resistance R53；Described 50th The other end of four pseudo- resistance R54 is connect with one end of the 54th pseudo- resistance R54.

One end of described 55th pseudo- resistance R55 is connect with the other end of the 54th pseudo- resistance R54；Described 50th The other end of five pseudo- resistance R55 is connect with one end of the 56th pseudo- resistance R56.

One end of described 56th pseudo- resistance R56 is connect with the other end of the 55th pseudo- resistance R55；Described 50th The other end of six pseudo- resistance R56 is connect with one end of the 57th pseudo- resistance R57.

One end of described 57th pseudo- resistance R57 is connect with the other end of the 56th pseudo- resistance R56；Described 50th The other end of seven pseudo- resistance R57 is connect with one end of the 58th pseudo- resistance R58.

One end of described 58th pseudo- resistance R58 is connect with the other end of the 57th pseudo- resistance R57；Described 50th The other end of eight pseudo- resistance R58 is connect with one end of the 59th pseudo- resistance R59.

One end of described 59th pseudo- resistance R59 is connect with the other end of the 58th pseudo- resistance R58；Described 50th The other end of nine pseudo- resistance R59 is connect with one end of the 60th pseudo- resistance R60.

One end of described 60th pseudo- resistance R60 is connect with the other end of the 59th pseudo- resistance R59；Described 60th is pseudo- The resistance R60 other end is connect with the first non-inverting input terminal BVIN1+ of second channel mutual conductance boster.

One end of described 61st pseudo- resistance R61 and the first non-inverting input terminal of second channel mutual conductance boster BVIN1- connection；The other end of described 61st pseudo- resistance R61 is connect with one end of the 62nd pseudo- resistance R62.

One end of described 62nd pseudo- resistance R62 is connect with the other end of the 61st pseudo- resistance R61；Described 60th The other end of two pseudo- resistance R62 is connect with ground terminal GND.

It is above-mentioned to apply in example, the equivalent inpnt thermal noise of metal-oxide-semiconductor are as follows:

Therefore, increase g_mIt is the effective way for reducing noise.And in actual low-power consumption application, it is necessary to amplifier Power consumption makes stringent limitation.In the case where given quiescent current, the electric current mutual conductance efficiency of MOS transistor can be indicated are as follows:

For single MOS transistor, in order to obtain higher electric current mutual conductance efficiency, need to bias MOS transistor In sub-threshold region.However the promotion done so is limited.

Above-mentioned to apply in example, there are three Differential Input pipes pair for each channel tool of binary channels mutual conductance boster.With For first passage, MN2 and MN3, MP2 and MP3, MN6 and MN7 respectively constitute three Differential Input pipes pair, and mutual conductance is respectively g_m1、 g_m2、g_m3。

Total mutual conductance of first passage:

G_mA=g_m1+g_m2+g_m3；

That is total mutual conductance of first passage is the sum of the mutual conductance of three metal-oxide-semiconductors.And each of traditional structure shown in Fig. 2 is defeated Enter end and be all connected to NMOS and PMOS, is similar to phase inverter.In this way the mutual conductance of amplifier be equal to NMOS and PMOS it With, i.e., only with 2 times of single metal-oxide-semiconductor mutual conductance.If the electric current that MP1 flows through is I, mutual conductance g_m, electricity that current source I1 flows through Stream is 2I, then the total current of entire amplifier is 4I, and the electric current in an average channel is 2I.So 2I is similarly with bias current Fig. 2 shown in structure compare, the transconductance value in each of the invention channel is the sum of the mutual conductance of MN2, MP2, MN6, i.e. G_mA=g_m1+ g_m2+g_m3=3g_m, and total transconductance value of structure shown in Fig. 2 is 2g_m, to effectively raise transconductance value, thereby reduce bottom It makes an uproar.In conjunction with wave chopping technology, the low-frequency noise of amplifier has also obtained effective inhibition.The embodiment of the present invention uses 0.18 μm of standard CMOS technology is realized.Supply voltage 1.2V, each channel consume 200nA electric current.

0, Figure 10 is a kind of noise spectrum characteristics of low-noise preamplifier provided in an embodiment of the present invention referring to Figure 1 Curve synoptic diagram.

1, Figure 11 is a kind of input impedance characteristic of low-noise preamplifier provided in an embodiment of the present invention referring to Figure 1 Curve synoptic diagram.

The embodiment of the present invention is under 0.1-200Hz bandwidth, noise efficient coefficient 1.71, with interior 1.25 μ of equivalent point noise Vrms, low frequency input impedance can achieve 200M Ω.And for custom low noise chopper amplifier structure, noise efficient coefficient is big In 2, input impedance does not exceed 10M Ω, thus, the present invention can efficiently solve the noise efficient of existing low-noise amplifier The problems such as coefficient is higher, and the input impedance of amplifier is lower.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention Protection scope.

Claims (8)

1. a kind of low-noise preamplifier circuit for bio signal amplification characterized by comprising input impedance improves Module (1), chopping modulation module (2), feedback network module (3) and binary channels mutual conductance boster (4)；The input impedance Improving module (1) includes first voltage follower (A1), second voltage follower (A2), tertiary voltage follower (A3) and the 4th Voltage follower (A4)；The chopping modulation module (2) includes the first chopping switch (CH1), the second chopping switch (CH2), the Three chopping switch (CH3), the 4th chopping switch (CH4), the 5th chopping switch (CH5), the 6th chopping switch (CH6), the 7th cut Wave switchs (CH7) and the 8th chopping switch (CH8)；The feedback network module includes the first feedback network and the second feedback net Network；The binary channels mutual conductance boster (4) includes that first passage mutual conductance boster and second channel mutual conductance enhancing are put Big device；Wherein,

The non-inverting input terminal (AVIN1) of the positive input electrical connection first passage of the first voltage follower (A1), bears The first input end of first chopping switch (CH1) is electrically connected to input terminal and output end；The second voltage follows The inverting input terminal (AVIN2) of the positive input electrical connection first passage of device (A2), negative input and its output end are equal It is electrically connected to the second input terminal of first chopping switch (CH1)；The positive input of the tertiary voltage follower (A3) It is electrically connected the noninverting input (BVIN1) of second channel, negative input and its output end are electrically connected to described second and cut Wave switchs the first input end of (CH2)；The positive input of 4th voltage follower (A4) is electrically connected the anti-of second channel It is second defeated to be electrically connected to second chopping switch (CH2) for phase input terminal (BVIN2), negative input and its output end Enter end；

The first output end and second output terminal of first chopping switch (CH1) are respectively electrically connected to first feedback network First input end (X1) and the second input terminal (X2)；First output end of second chopping switch (CH2) and the second output End is respectively electrically connected to the first input end (X3) and the second input terminal (X4) of second feedback network；The third copped wave is opened Close (CH3) the first output end and second output terminal be respectively electrically connected to the first passage noninverting input (AVIN1) and Inverting input terminal (AVIN2) and its first output end and second output terminal are respectively electrically connected to the first of first feedback network Input terminal (X1) and the second input terminal (X2)；The first input end of 4th chopping switch (CH4) and the second input terminal difference It is electrically connected to the noninverting input (BVIN1) and inverting input terminal (BVIN2) and its first output end and of the second channel Two output ends are respectively electrically connected to the first input end (X3) and the second input terminal (X4) of second feedback network；

The first feedback end and the second feedback end of first feedback network are respectively electrically connected to the 7th chopping switch (CH7) First input end and the output end of the second input terminal and first feedback network be electrically connected to the first passage mutual conductance and increase The input terminal (AVIN1+, AVIN2+, AVIN3+, AVIN1-, AVIN2-, AVIN3-) of strong amplifier；Second feedback network The first feedback end and the second feedback end be respectively electrically connected to the first input end of the 8th chopping switch (CH8) and second defeated The output end for entering end and second feedback network is electrically connected to the input terminal of the second channel mutual conductance boster (BVIN1+,BVIN2+,BVIN3+,BVIN1-,BVIN2-,BVIN3-)；

The first output end (AVO+) and second output terminal (AVO-) of the first passage mutual conductance boster are electrically connected To the first input end and the second input terminal of the 5th chopping switch (CH5)；The second channel mutual conductance boster First output end (BVO+) and second output terminal (BVO-) are respectively electrically connected to the first input of the 6th chopping switch (CH6) End and the second input terminal；And

The first output end and second output terminal of 5th chopping switch (CH5) are respectively electrically connected to the same mutually defeated of first passage Outlet (AVOUT1) and reversed-phase output (AVOUT2)；First output end of the 6th chopping switch (CH6) and the second output End is respectively electrically connected to the in-phase output end (BVOUT1) and reversed-phase output (BVOUT2) of second channel；7th copped wave is opened The first output end and second output terminal that close (CH7) are respectively electrically connected to the in-phase output end (AVOUT1) and reverse phase of first passage Output end (AVOUT2)；The first output end and second output terminal of 8th chopping switch (CH8) are respectively electrically connected to second The in-phase output end (BVOUT1) and reversed-phase output (BVOUT2) in channel.

2. circuit according to claim 1, which is characterized in that the binary channels mutual conductance boster (4) includes first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), 6th PMOS tube (MP6), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), the tenth PMOS tube (MP10), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12), the first NMOS tube (MN1), the second NMOS tube (MN2), Third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th NMOS tube (MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), 12 NMOS tubes (MN12), the first pseudo- resistance (R1), the second pseudo- resistance (R2), third puppet resistance (R3), the 4th pseudo- resistance (R4) And first current source (I1)；Wherein,

First PMOS tube (MP1), second PMOS tube (MP2), the 4th PMOS tube (MP4), the 4th NMOS tube (MN4), second NMOS tube (MN2) and first NMOS tube (MN1) are sequentially connected in series in voltage source (VDD) and ground terminal (GND) between；The third PMOS tube (MP3), the 5th PMOS tube (MP5), the 5th NMOS tube (MN5) and the third NMOS tube (MN3) is sequentially connected in series the node A formed in first PMOS tube (MP1) and second PMOS tube (MP2) concatenation Place is concatenated with first NMOS tube (MN1) and second NMOS tube (MN2) between the node B formed；Described first The grid of PMOS tube (MP1) inputs first passage bias voltage (V_BIASA), described in the grid of second PMOS tube (MP2) is used as The second non-inverting input terminal (AVIN2+) of first passage mutual conductance boster, the grid conduct of the third PMOS tube (MP3) The second inverting input terminal (AVIN2-) of the first passage mutual conductance boster；The grid of 4th PMOS tube (MP4) And the grid of the 5th PMOS tube (MP5) inputs the first external bias voltage (V_B1)；Described first pseudo- resistance (R1) and institute State the second node E that pseudo- resistance (R2) is serially connected with the 4th PMOS tube (MP4) and the 4th NMOS tube (MN4) concatenation is formed Place concatenate with the 5th PMOS tube (MP5) and the 5th NMOS tube (MN5) formation node F between and node E with save Reversed-phase output and in-phase output end of the point F respectively as the first passage mutual conductance boster；4th NMOS tube (MN4) grid of grid and the 5th NMOS tube (MN5) inputs the second external bias voltage (V_B2)；2nd NMOS Manage third non-inverting input terminal (AVIN3+) of the grid of (MN2) as the first passage mutual conductance boster, the third Third inverting input terminal (AVIN3-) of the grid of NMOS tube (MN3) as the first passage mutual conductance boster；It is described The grid of first NMOS tube (MN1) is electrically connected to the described first pseudo- resistance (R1) and concatenates formation with the described second pseudo- resistance (R2) At node M；

8th PMOS tube (MP8), the 9th PMOS tube (MP9), the 11st PMOS tube (MP11), the 11st NMOS Pipe (MN11), the 9th NMOS tube (MN9) and the 8th NMOS tube (MN8) are sequentially connected in series in voltage source (VDD) and ground connection It holds between (GND)；Tenth PMOS tube (MP10), the 12nd PMOS tube (MP12), the 12nd NMOS tube (MN12) and Tenth NMOS tube (MN10) is sequentially connected in series in the 8th PMOS tube (MP8) and the 9th PMOS tube (MP9) concatenation shape At node N at concatenate with the 9th NMOS tube (MN9) and the 8th NMOS tube (MN8) between the node H formed；Institute State third non-inverting input terminal (BVIN3 of the grid as the second channel mutual conductance boster of the 9th PMOS tube (MP9) +), third inverting input terminal of the grid of the tenth PMOS tube (MP10) as the second channel mutual conductance boster (BVIN3-)；The grid of 11st PMOS tube (MP11) and the grid of the 12nd PMOS tube (MP12) input third External bias voltage (V_B3)；The third puppet resistance (R3) and the 4th pseudo- resistance (R4) are serially connected with the 11st PMOS tube (MP11) and at the node I that is formed of the 11st NMOS tube (MN11) concatenation with the 12nd PMOS tube (MP12) and described Between the node J that 12nd NMOS tube (MN12) concatenation is formed and node I and node J are respectively as the second channel mutual conductance The reversed-phase output and in-phase output end of boster；The grid and the described 12nd of 11st NMOS tube (MN11) The grid of NMOS tube (MN12) inputs the 4th external bias voltage (V_B4)；The grid of 9th NMOS tube (MN9) is as institute The second non-inverting input terminal (BVIN2+) of second channel mutual conductance boster is stated, the grid of the tenth NMOS tube (MN10) is made For the second inverting input terminal (BVIN2-) of the second channel mutual conductance boster；The grid of 8th PMOS tube (MP8) Pole is electrically connected to the third puppet resistance (R3) and concatenates at the node R formed with the described 4th pseudo- resistance (R4), and the described 8th The grid of NMOS tube (MN8) inputs second channel bias voltage (V_BIASB)；

The drain electrode of 6th NMOS tube (MN6) is electrically connected to the third PMOS tube (MP3) and the 5th PMOS tube (MP5) It concatenates at the node D formed, the source electrode of the 6th NMOS tube (MN6) is electrically connected to one end of first current source (I1), grid First non-inverting input terminal (AVIN1+) of the pole as the first passage mutual conductance boster；7th NMOS tube (MN7) Drain electrode be electrically connected to second PMOS tube (MP2) concatenated with the 4th PMOS tube (MP4) formed node C at, the 7th The source electrode of NMOS tube (MN7) is electrically connected to one end of first current source (I1), and grid is as the first passage mutual conductance The first inverting input terminal (AVIN1-) of boster；The drain electrode of 6th PMOS tube (MP6) is electrically connected to the described tenth At the node K that one NMOS tube (MN11) and the 9th NMOS tube (MN9) concatenation are formed, the source electrode electricity of the 6th PMOS tube (MP6) It is connected to the other end of first current source (I1), grid is first same as the second channel mutual conductance boster To input terminal (BVIN1+)；The drain electrode of 7th PMOS tube (MP7) is electrically connected to the 12nd NMOS tube (MN12) and institute It states at the node L that the tenth NMOS tube (MN10) concatenation is formed, the source electrode of the 7th PMOS tube (MP7) is electrically connected to first electric current The other end in source (I1), first inverting input terminal (BVIN1-) of the grid as the second channel mutual conductance boster.

3. circuit according to claim 1, which is characterized in that the voltage follower (A1, A2, A3, A4) includes the tenth Three PMOS tube (MP13), the 14th PMOS tube (MP14), the 15th PMOS tube (MP15), the 16th PMOS tube (MP16), the tenth Three NMOS tubes (MN13) and the 14th NMOS tube (MN14)；Wherein,

13rd PMOS tube (MP13), the 14th PMOS tube (MP14), the 15th PMOS tube (MP15) and institute The 13rd NMOS tube (MN13) is stated to be sequentially connected in series between voltage source (VDD) and ground terminal (GND)；16th PMOS tube (MP16) and the 14th NMOS tube (MN14) is sequentially connected in series in the 14th PMOS tube (MP14) and the described 15th At the node P that PMOS tube (MP15) concatenation is formed between ground terminal (GND)；The grid of 13rd PMOS tube (MP13) is defeated Enter bias voltage (VBIAS), the grid of the 14th PMOS tube (MP14) inputs enable signal (EN), the 15th PMOS The grid of pipe (MP15) is electrically connected to the input terminal (AVIN1, AVIN2, BVIN1, BVIN2) of the low-noise preamplifier, The grid of 13rd NMOS tube (MN13) and the grid of the 14th NMOS tube (MN14) are electrically connected to the described tenth Five PMOS tube (MP15) are concatenated with the 13rd NMOS tube (MN13) at the node O formed, the 16th PMOS tube (MP16) grid is electrically connected to the 16th PMOS tube (MP16) and concatenates formation with the 14th NMOS tube (MN14) At node Q and as the output end of the voltage follower (A1, A2, A3, A4) (Vout).

4. circuit according to claim 1, which is characterized in that first chopping switch (CH1) or second copped wave Switching (CH2) includes the 15th NMOS tube (MN15), the 16th NMOS tube (MN16), the 17th NMOS tube (MN17) and the 18th NMOS tube (MN18)；Wherein,

15th NMOS tube (MN15) is electrically connected to first chopping switch (CH1) or second chopping switch (CH2) between first input end and the second input terminal and its grid inputs the 6th clock control signal (CLKB2)；Described tenth Six NMOS tubes (MN16) are electrically connected to the second input of first chopping switch (CH1) or second chopping switch (CH2) Between end and second output terminal and its grid inputs the 5th clock control signal (CLK2)；17th NMOS tube (MN17) electricity Be connected to first chopping switch (CH1) or second chopping switch (CH2) the first output end and second output terminal it Between and its grid input the 6th clock control signal (CLKB2)；18th NMOS tube (MN18) is electrically connected to described first Between chopping switch (CH1) or the first input end and the first output end of second chopping switch (CH2) and its grid inputs 5th clock control signal (CLK2).

5. circuit according to claim 1, which is characterized in that the third chopping switch (CH3) or the 4th copped wave Switching (CH4) includes the 19th NMOS tube (MN19), the 20th NMOS tube (MN20), the 21st NMOS tube (MN21) and second 12 NMOS tubes (MN22)；Wherein,

19th NMOS tube (MN19) is electrically connected to the third chopping switch (CH3) or the 4th chopping switch (CH4) between first input end and the second input terminal and its grid inputs the 4th clock control signal (CLKB1)；Described second Ten NMOS tubes (MN20) are electrically connected to the second input of the third chopping switch (CH3) or the 4th chopping switch (CH4) Between end and second output terminal and its grid inputs third clock control signal (CLK1)；21st NMOS tube (MN21) It is electrically connected to the first output end and second output terminal of the third chopping switch (CH3) or the 4th chopping switch (CH4) Between and its grid input the 4th clock control signal (CLKB1)；22nd NMOS tube (MN22) is electrically connected to described Between third chopping switch (CH3) or the first input end and the first output end of the 4th chopping switch (CH4) and its grid It inputs third clock control signal (CLK1).

6. circuit according to claim 1, which is characterized in that the 5th chopping switch (CH5), the 6th copped wave are opened Close (CH6), the 7th chopping switch (CH7) or the 8th chopping switch (CH8) include the 23rd NMOS tube (MN23), 24th NMOS tube (MN24), the 25th NMOS tube (MN25) and the 26th NMOS tube (MN26)；Wherein,

23rd NMOS tube (MN23) is electrically connected to the 5th chopping switch (CH5) or the 6th chopping switch (CH6) between first input end and the second input terminal and its grid input second clock controls signal (CLKB0)；Described second 14 NMOS tubes (MN24) are electrically connected to the 5th chopping switch (CH5) or the second of the 6th chopping switch (CH6) defeated Enter between end and second output terminal and its grid inputs the first clock control signal (CLK0)；25th NMOS tube (MN25) it is electrically connected to the first output end and second of the 5th chopping switch (CH5) or the 6th chopping switch (CH6) Between output end and its grid input second clock controls signal (CLKB0)；26th NMOS tube (MN26) electrical connection Between the 5th chopping switch (CH5) or the first input end and the first output end of the 6th chopping switch (CH6) and Its grid inputs the first clock control signal (CLK0).

7. circuit according to claim 1, which is characterized in that first feedback network include the 5th pseudo- resistance (R5), 6th pseudo- resistance (R6), the 7th pseudo- resistance (R7), the 8th pseudo- resistance (R8), the 9th pseudo- resistance (R9), the tenth pseudo- resistance (R10), 11st pseudo- resistance (R11), the 12nd pseudo- resistance (R12), the 13rd pseudo- resistance (R13), the 14th pseudo- resistance (R14), the tenth Five pseudo- resistance (R15), the 16th pseudo- resistance (R16), the 17th pseudo- resistance (R17), the 18th pseudo- resistance (R18), the 19th puppet Resistance (R19), the 20th pseudo- resistance (R20), the 21st pseudo- resistance (R21), the 22nd pseudo- resistance (R22), the 23rd Pseudo- resistance (R23), the 24th pseudo- resistance (R24), the 25th pseudo- resistance (R25), the 26th pseudo- resistance (R26), second 17 pseudo- resistance (R27), the 28th pseudo- resistance (R28), the 29th pseudo- resistance (R29), the 30th pseudo- resistance (R30), the 31 pseudo- resistance (R31), the 32nd pseudo- resistance (R32), the 33rd pseudo- resistance (R33), the 34th pseudo- resistance (R34), the 35th pseudo- resistance (R35), the 36th pseudo- resistance (R36), first capacitor (C1), the second capacitor (C2), third Capacitor (C3), the 4th capacitor (C4), the 5th capacitor (C5), the 6th capacitor (C6), the 7th capacitor (C7), the 8th capacitor (C8), Nine capacitors (C9), the tenth capacitor (C10), the 11st capacitor (C11) and the 12nd capacitor (C12)；Wherein,

Described 5th pseudo- resistance (R5), the 6th pseudo- resistance (R6), the 7th pseudo- resistance (R7) and the 8th pseudo- resistance (R8) it is sequentially connected in series between the in-phase output end (AVOUT1) and ground terminal (GND) of the first passage and the first passage The third inverting input terminal (AVIN3-) of mutual conductance boster is electrically connected to the described 5th pseudo- resistance (R5) and the 6th puppet At the node that resistance (R6) concatenation is formed；Described 9th pseudo- resistance (R9), the tenth pseudo- resistance (R10), the 11st puppet Resistance (R11) and the 12nd pseudo- resistance (R12) be sequentially connected in series reversed-phase output (AVOUT2) in the first passage with Between ground terminal (GND) and the third non-inverting input terminal (AVIN3+) of the first passage mutual conductance boster is electrically connected to institute The 9th pseudo- resistance (R9) is stated to concatenate at the node formed with the described tenth pseudo- resistance (R10)；

The 13rd pseudo- resistance (R13), the 14th pseudo- resistance (R14), the 15th pseudo- resistance (R15), described the 16 pseudo- resistance (R16), the 17th pseudo- resistance (R17), the 18th pseudo- resistance (R18), the 19th pseudo- resistance (R19), the described 20th pseudo- resistance (R20), the 21st pseudo- resistance (R21), the 22nd pseudo- resistance (R22), Described 23rd pseudo- resistance (R23) and the 24th pseudo- resistance (R24) are sequentially connected in series the same phase in the first passage Between output end (AVOUT1) and voltage source (VDD) and the second inverting input terminal of the first passage mutual conductance boster (AVIN2-) the described 14th pseudo- resistance (R14) is electrically connected to concatenate at the node formed with the described 15th pseudo- resistance (R15) And the first inverting input terminal (AVIN1-) of the first passage mutual conductance boster is electrically connected to the described 21st pseudo- electricity Resistance (R21) concatenates at the node formed with the described 22nd pseudo- resistance (R22)；It is the 25th pseudo- resistance (R25), described 26th pseudo- resistance (R26), the 27th pseudo- resistance (R27), the 28th pseudo- resistance (R28), described second 19 pseudo- resistance (R29), the 30th pseudo- resistance (R30), the 31st pseudo- resistance (R31), the 32nd puppet Resistance (R32), the 33rd pseudo- resistance (R33), the 34th pseudo- resistance (R34), the 35th pseudo- resistance (R35) and the 36th pseudo- resistance (R36) is sequentially connected in series reversed-phase output (AVOUT2) and electricity in the first passage Between potential source (VDD) and the second non-inverting input terminal (AVIN2+) of the first passage mutual conductance boster be electrically connected to it is described 26th pseudo- resistance (R26) concatenated at the node of formation with the described 27th pseudo- resistance (R27) and the first passage across The first non-inverting input terminal (AVIN1+) for leading boster is electrically connected to the described 33rd pseudo- resistance (R33) and the third 14 pseudo- resistance (R34) concatenate at the node formed；

The first capacitor (C1) and the 7th capacitor (C7), second capacitor (C2) and the 8th capacitor (C8), institute It states third capacitor (C3) and the 9th capacitor (C9) is sequentially connected in series first input end (X1) in first feedback network Between the in-phase output end (AVOUT1) of the first passage and the first same phase of the first passage mutual conductance boster Input terminal (AVIN1+) be electrically connected to the first capacitor (C1) concatenated with the 7th capacitor (C7) formed node at and institute The second non-inverting input terminal (AVIN2+) for stating first passage mutual conductance boster is electrically connected to second capacitor (C2) and institute State the 8th capacitor (C8) concatenation formed node at and the first passage mutual conductance boster third non-inverting input terminal (AVIN3+) it is electrically connected to the third capacitor (C3) to concatenate with the 9th capacitor (C9) at the node formed, the 4th electricity Hold (C4) and the tenth capacitor (C10), the 5th capacitor (C5) and the 11st capacitor (C11), the 6th capacitor (C6) the second input terminal (X2) in first feedback network and described the are sequentially connected in series with the 12nd capacitor (C12) Between the reversed-phase output (AVOUT2) in one channel and the first inverting input terminal of the first passage mutual conductance boster (AVIN1-) be electrically connected to the 4th capacitor (C4) concatenated with the tenth capacitor (C10) formed node at and described first The second inverting input terminal (AVIN2-) of channel mutual conductance boster is electrically connected to the 5th capacitor (C5) and the described tenth One capacitor (C11) concatenates at the node formed and the third inverting input terminal of the first passage mutual conductance boster (AVIN3-) the 6th capacitor (C6) is electrically connected to concatenate with the 12nd capacitor (C12) at the node formed.

8. circuit according to claim 1, which is characterized in that second feedback network includes the 37th pseudo- resistance (R37), the 38th pseudo- resistance (R38), the 39th pseudo- resistance (R39), the 40th pseudo- resistance (R40), the 41st pseudo- electricity Hinder (R41), the 42nd pseudo- resistance (R42), the 43rd pseudo- resistance (R43), the 44th pseudo- resistance (R44), the 45th Pseudo- resistance (R45), the 46th pseudo- resistance (R46), the 47th pseudo- resistance (R47), the 48th pseudo- resistance (R48), the 4th 19 pseudo- resistance (R49), the 50th pseudo- resistance (R50), the 51st pseudo- resistance (R51), the 52nd pseudo- resistance (R52), the 53 pseudo- resistance (R53), the 54th pseudo- resistance (R54), the 55th pseudo- resistance (R55), the 56th pseudo- resistance (R56), the 57th pseudo- resistance (R57), the 58th pseudo- resistance (R58), the 59th pseudo- resistance (R59), the 60th pseudo- electricity Hinder (R60), the 61st pseudo- resistance (R61), the 62nd pseudo- resistance (R62), the 13rd capacitor (C13), the 14th capacitor (C14), the 15th capacitor (C15), the 16th capacitor (C16), the 17th capacitor (C17), the 18th capacitor (C18), the 19th Capacitor (C19), the 20th capacitor (C20), the 21st capacitor (C21), the 22nd capacitor (C22), the 23rd capacitor (C23) and the 24th capacitor (C24)；Wherein,

The 37th pseudo- resistance (R37) be serially connected with second channel in-phase output end (BVOUT1) and the second channel across The third inverting input terminal (BVIN3-) of boster is led, it is logical that the described 38th pseudo- resistance (R38) is serially connected with described second The third non-inverting input terminal (BVIN3+) of the reversed-phase output (BVOUT2) in road and the second channel mutual conductance boster it Between；

Described 39th pseudo- resistance (R39), the 40th pseudo- resistance (R40), the 41st pseudo- resistance (R41), institute State the 42nd pseudo- resistance (R42), the 43rd pseudo- resistance (R43), the 44th pseudo- resistance (R44), described the 45 pseudo- resistance (R45), the 46th pseudo- resistance (R46), the 47th pseudo- resistance (R47), the described 40th Eight pseudo- resistance (R48), the 49th pseudo- resistance (R49) and the 50th pseudo- resistance (R50) are sequentially connected in series in described the Between the in-phase output end (BVOUT1) and ground terminal (GND) in two channels and the second channel mutual conductance boster second Inverting input terminal (BVIN2-) is electrically connected to the described 40th pseudo- resistance (R40) and concatenates with the described 41st pseudo- resistance (R41) At the node of formation and the first inverting input terminal (BVIN1-) of the second channel mutual conductance boster be electrically connected to it is described 48th pseudo- resistance (R48) concatenates at the node formed with the described 49th pseudo- resistance (R49)；Described 51st pseudo- electricity Hinder (R51), the 52nd pseudo- resistance (R52), the 53rd pseudo- resistance (R53), the 54th pseudo- resistance (R54), the described 55th pseudo- resistance (R55), the 56th pseudo- resistance (R56), the 57th pseudo- resistance (R57), the described 58th pseudo- resistance (R58), the 59th pseudo- resistance (R59), the 60th pseudo- resistance (R60), Described 61st pseudo- resistance (R61) and the 62nd pseudo- resistance (R62) are sequentially connected in series in the reverse phase of the second channel Between output end (AVOUT2) and ground terminal (GND) and the second non-inverting input terminal of the second channel mutual conductance boster (BVIN2+) it is electrically connected to the described 52nd pseudo- resistance (R52) and concatenates the section formed with the described 53rd pseudo- resistance (R53) At point and the first non-inverting input terminal (BVIN1+) of the second channel mutual conductance boster is electrically connected to the 60th puppet Resistance (R60) concatenates at the node formed with the described 61st pseudo- resistance (R61)；

13rd capacitor (C13) and the 19th capacitor (C19), the 14th capacitor (C14) and the described 20th Capacitor (C20), the 15th capacitor (C15) and the 21st capacitor (C21) are sequentially connected in series in second feedback Between the first input end (X3) of network and the in-phase output end (BVOUT1) of the second channel and the second channel mutual conductance The first non-inverting input terminal (BVIN1+) of boster is electrically connected to the 13rd capacitor (C13) and the 19th capacitor (C19) it concatenates at the node formed and the second non-inverting input terminal (BVIN2+) of the second channel mutual conductance boster is electrically connected Be connected to the 14th capacitor (C14) concatenated with the 20th capacitor (C20) formed node at and the second channel across The third non-inverting input terminal (BVIN3+) for leading boster is electrically connected to the 15th capacitor (C15) and the described 21st At the node that capacitor (C21) concatenation is formed, the 16th capacitor (C16) and the 22nd capacitor (C22), the described tenth Seven capacitors (C17) and the 23rd capacitor (C23), the 18th capacitor (C18) and the 24th capacitor (C24) It is sequentially connected in series in the reversed-phase output of the second input terminal (X4) and the second channel of second feedback network (BVOUT2) between and the first inverting input terminal (BVIN1-) of the second channel mutual conductance boster be electrically connected to it is described 16th capacitor (C16) is concatenated at the node formed with the 22nd capacitor (C22) and second channel mutual conductance enhancing The second inverting input terminal (BVIN2-) of amplifier is electrically connected to the 17th capacitor (C17) and the 23rd capacitor (C23) it concatenates at the node formed and the third inverting input terminal (BVIN3-) of the second channel mutual conductance boster is electrically connected The 18th capacitor (C18) is connected to concatenate with the 24th capacitor (C24) at the node formed.