WO2009077759A1

WO2009077759A1 - Differential mode sensing arrangement

Info

Publication number: WO2009077759A1
Application number: PCT/GB2008/004175
Authority: WO
Inventors: Mohamad Rahal; Andreas Demosthenous
Original assignee: Ucl Business Plc
Priority date: 2007-12-19
Filing date: 2008-12-17
Publication date: 2009-06-25
Also published as: GB0724733D0

Abstract

A new architecture front-end for electronic sensing is introduced. The architecture utilizes a fully differential synchronous detector to modulate the received signal. A first chopping circuit is used to modulate the offset of a fully differential amplifier. A second chopping circuit is used to demodulate the outputs from the amplifier to remove its offset. The new architecture does not require the offset to be measured before a measurement is taken as in the prior art through the use of microcontroller based system. The amplifier employed is fully differential and does not require any feedback components thus increasing the ability to reject interference and common mode signals. The architecture is also immune to the impedance imbalances at the front end by employing cross- coupled synchronous detector arrangement. The architecture can be employed in various applications where the detection of low-level signals with specific frequency contents is required.

Description

DIFFERENTIAL MODE SENSING ARRANGEMENT

Field of the Invention:

This invention relates generally to the field of electronic sensing, and more specifically, it pertains to a measurement circuit, a differential-mode measurement circuit, and to a method of measuring an ac signal. Embodiments enable detection or measurement of signals in a way that is free of offsets and rejects common mode interference.

Background of the invention: In sensing applications there is a need for measuring the average of a periodic or non-periodic signal. The origin of the signal can be from a biomedical source such as a nerve fibre, from a receiving coil in industrial applications or other suitable sources. An amplifier is needed to amplify the signal. Ideally the amplifier should only amplify the signal of interest and not to add any noise or offset. However, in practice this is not possible and both noise and offset issues cause problems and special techniques are used to minimise these non-idealities in the sensing system.

One method is the use of synchronous detection, which involves the sampling of the input signal with a signal of the same frequency. This method is phase sensitive and gives a maximum output when the phase difference between the input and the modulating signal is zero and a minimum when the phase is 90 degrees. As a result, the synchronous detection action acts as a band-pass filter to the input signal. Other methods used to minimize the effect of amplifier offset include auto-zeroing and chopping.

GB-A- 2374424, US-B- 7205775 and 6838873 disclose some prior art inductive position sensors

Typically, an inductive position sensor uses mutual inductance between an antenna and a target to determine the target position along a measurement axis. An antenna containing transmitter and receiver coils on a printed circuit board (PCB) is supplied with an AC signal from an electronic module to drive a transmitter coil. Analysis of the signals from the receiver coils by the electronic module determines the exact position of the target. However, there are inherent errors and offsets in the electronic sensing system, and to cope with these a calibration measurement is taken before every proper measurement is taken. The results from the calibration measurement are then used to correct the results of the proper measurement, for example in the digital domain. The need for more than one measuring step to achieve a single useful result may prevent application of the technique to fast sensing applications such as when detecting from multiple targets.

In addition, known synchronous detection architectures may not reject unwanted coupling between the transmitter and receiver coils which occurs, for example, if both share the same PCB. Furthermore, known amplifier architecture may not optimally reject common-mode signals that appear on the two ends of the receiver coil. All of these factors limit the speed of the sensor and its resolution.

In one aspect there is provided a differential-mode measurement circuit having a synchronous detector coupled to a full differential open loop amplifier via a first chopper, and a second chopper coupled to feed differential signals to a low pass filter.

In another aspect there is provided a method of measuring an ac signal comprising synchronously detecting the ac signal to provide a detected differential signal; chopping the detected differential signal at a frequency higher than the frequency of the ac signal; applying the chopped signals to an open loop differential-to-differential amplifier; chopping output signals of the differential-to-differential amplifier; and applying the chopped output signals of the differential-to-differential amplifier to a low pass filter.

In a further aspect there is provided a measurement circuit having a synchronous detector, an amplifier circuit and a low pass filter; the synchronous detector having a pair of differential input nodes and a pair of differential output nodes and being connected to receive an ac input signal, the amplifier circuit being connected to receive signals from the detector and to output signals to the low pass filter; characterised by: the amplifier circuit being an open loop differential-to-differential amplifier, having two input terminals and two output terminals; a first chopper, having differential input nodes and output nodes, and a second chopper having differential input nodes and output nodes; output nodes of the synchronous detector being connected to the differential input nodes of the first chopper, the differential output nodes of the first chopper being connected respectively to the two input terminals of the open loop differential-to-differential amplifier, the two output terminals of the open loop differential-to-differential amplifier being connected to the differential input nodes of the second chopper; the differential output nodes of the second chopper being connected respectively to the low-pass filter.

Embodiments provide a sensing system, which is offset free and hence does not require offset measurement before a measurement is taken. Embodiments aim at a novel differential synchronous detector architecture that significantly reduces the effect of coupling between the transmitter and receiver coils. An embodiment has an amplifier architecture that is fully differential and compatible with the novel differential detector described above. The amplifier architecture may significantly reduce the effect of common-mode signals that appear on the receiver coils. An underlying interest is to provide a particularly versatile architecture, which can be changed to suit multiple applications. One embodiment of the invention will allow the use of position inductive sensor in high-speed applications such as in multiple targets.

The invention will be more clearly understood after reading the description of an exemplary embodiment of the invention, and referring to the accompanying drawings, in which: Fig. 1 shows a schematic diagram of a detector;

Fig. 2 shows the basic block diagram of an electronic readout system for the detector of Fig 1;

Fig. 3 shows a first synchronous detector;

Fig. 4 shows a second synchronous detector; Fig. 5 shows a basic block diagram of an embodiment;

Fig. 6 shows a basic schematic diagram of the embodiment of Fig.5;

Fig. 7 shows illustrative signals of the embodiment of Fig.6; and

Fig 8 shows an exemplary switch for use in the invention. In the various figures, like reference signs indicate like parts.

Referring to Fig. 1 a detector (1) for linear or angular position has a printed circuit board (110), a movable target (120) whose position is to be sensed, an electronic module (130) , a power supply (140) and an output line (150) for communication signals. The PCB (110) defines transmitter and receiver coils of an antenna. The target (120) is shown movably disposed over the PCB (110). The electronic module (130) is connected to supply signals to and receive signals from the PCB (110) and is powered from the power supply (140). The electronics module (130) sends communication signals (150) to the outside world.

In one known arrangement, the vertical distance between target (120) and antenna (110) PCB is about 2 mm. Referring to Fig.2, the target (120) is shown as having a parallel resonant circuit (201); the PCB (110) carries three coils (202, 203, 204) of which the first two coils (202,203) are two receiver coils and the third coil (204) is a transmitter coil.

The electronic module (130) consists of first, second and third filters (205-7), a time-multiplexer (208), a mixer (209), 90 degree phase shifter (210), an oscillator (211), an amplifier/filter (212), an ADC(213) and a digital signal processor (214) acting as a microcontroller.

The signal processor (214) is connected to control the oscillator (211), whose square wave output is connected to an input of the third buffer (207), which in turn has outputs to the third coil (204). The first and second coils (202,203) feed inputs of their respective filters (205, 206). The outputs of the first and second filters (205,206) provide inputs to the multiplexer (208), and the time- division multiplexed output of the multiplexer (208) is fed as an input to the mixer (209). The oscillator (211) has a second output fed to the input of the phase shifter (210); the phase-shifted output of the phase shifter (210) feeds to the second input of the mixer (209). The output of the mixer (209) is fed as input to the amplifier/filter (212), and the output of this is fed to the ADC (213). The ADC output is fed as an input to the microcontroller (214).

In normal operation, at least two receiver coils (202, 203) are used to determine the target (201) position. Energy is transferred between the transmitter coil (204) and the target (201) through their mutual inductance as is well-known. Energy from the target (201) is transferred in turn to the receiver coils (202, 203). By selecting an appropriate layout of the receiver coils (202, 203) on the PCB (110), the signals picked up by the coils (202,203) are in- phase with each other in the time domain but out-of-phase spatially. The transmitter coil (204) is driven by a buffer (207) via an oscillator. In this arrangement the oscillator is a square- wave oscillator (211) having an output of controllable variable frequency.

The received signals picked up by the coils (202, 203) are synchronously demodulated through the mixer (209) by a signal whose frequency is equal to the resonant frequency of the target (201). The oscillator (211) provides a signal to the mixer, which by virtue of the phase shifter (210) is in phase quadrature with the signal provided to the buffer driver (207).

The mixer output consists of the multiplexed demodulated signals, and these are amplified and filtered by the amplifier/filter sub-system (212) to obtain a DC value. The analogue to digital converter (213) is used to digitize this DC value for further processing by the microcontroller (214).

There are different synchronous detection schemes used in the prior art. Referring to Fig. 3, one end of a receiver coil (301) is at a reference voltage V_REF (306). Signals from the coil are synchronously demodulated in differential mode by switches (304 and 305) using two switching signals (302, 303). These are at the oscillator frequency, i.e. the same frequency at which the target resonates, and are respectively in phase and anti-phase with the oscillator output. (This is discussed later herein with reference to Fig.8) The outputs of the synchronous demodulator are connected to a first-order low-pass filter (307), implemented as a differential amplifier with negative feedback. A programmable amplification stage (308) is added to increase the signal level for proper A/D operation. Referring to Fig. 4, a receiver coil (401) is connected to ends of a resistive divider (402), having a centre tap connected to a reference potential Vref. (403). A local oscillator (404) signal with the same frequency as the resonant frequency and in-phase with the received signal picked up by the coil (401) is used to synchronously demodulate the signals at the ends of the resistive divider with a switch (405). As in the configuration of Fig. 3, the output of the synchronous demodulator is connected to a first-order low-pass filter (406), and a programmable amplification stage (407).

The circuits of Fig. 3 and 4 suffer from inherent input offsets requiring a later micro-controller or signal processor to measure offset before every measurement is taken.

In addition, a key need is be able to reject any out-of-phase components, in particular the transmitter signal pickup. Transmitter signal pickup occurs due to receiver and transmitter coils sharing the same PCB and the difference in magnitude of the transmitted signal compared to the received signal. The amplitude of the transmitting signal is on the order of a few volts, whereas the received signal due to target excitation is perhaps the order of a few millivolts. Consequently, any phase difference between the received signal and the demodulating signal(s) used in the synchronous detectors will cause transmitter signal breakthrough, which will appear as a phase-sensitive offset. Additionally as this dynamic offset has the same frequency as the signal measured from the receiver coil, measuring this offset before a measurement is taken will not cancel it. In the prior art, this issue is coped with by the previously-described technique, in which a calibration measurement is effected to determine the offset, and then the offset value is subtracted from the final measurement to achieve the desired value.

Furthermore, in high-speed applications where multiple targets are employed, and a single sensor circuit provided, measuring the both the static and dynamic offset will not be an option. In addition, for both configurations disclosed in Fig. 3 and 4 the filter/amplifier employed suffers from a poor rejection to common-mode signal. This has been found to be due to the feedback nature of the architecture at the inputs of the filter/amplifier, and to the unequal impedances on the cables connecting the receiver coils to the input of the filter/amplifier (307, 308; 406, 407). Referring to Fig.5, a resistive divider (502) has its tap connected to a reference Vref, and its respective ends each connected to an analogue signal source (501) and inputs of a synchronous detector (503). Outputs of the detector (503) connect to inputs of a first chopping circuit (504). Outputs of the first chopping circuit (504) connect to differential inputs of an open loop instrumentation amplifier (505). Differential outputs of the open loop instrumentation amplifier (505) form inputs to a second chopping circuit (506), whose differential outputs are connected to a low pass filter (507)

The analogue signal (501) having a frequency fj_n is converted to differential by the resistive divider (502). The synchronous detector (503), supplied with a detection signal at a frequency f_ci_ksyn, together with chopping mechanisms (504 and 506), serve to remove the offset of the instrumentation amplifier (505). The chopping mechanisms (504,506) are supplied with chopping signals at a frequency f_ci_kch- The average output is obtained through the use of a low-pass filter (507).

Fig. 6 shows an embodiment in a powered up state. (It will be understood that although switches are shown diagrammatically as mechanical contacts, they will instead be semiconductor switches in most implementations. An exemplary switch using FETs is shown in Fig 8.)

Referring to Fig. 6, the analogue signal source (501) of Fig. 5 is formed by a coil (601), having first and second ends (601a, 601b). The resistive divider

(502) of Fig. 5 is two resistors (603), shown as having slightly differing values (R and R+dR), to represent the resistor tolerances, but having their common point connected to the fixed reference V _ref at (602). The synchronous detector (503) of Fig. 6 is shown as first and second switches (604, 605) controlled by phase-opposite signals. The switches are each operated functionally as double-pole single-throw, with the "wipers" respectively providing first and second synchronous detector outputs (624, 625). In the state shown the first switch (604) connect the signal at the first end (601a) of the coil to the first synchronous detector output node (624), and the second switch (605) connects the signal at the second end of the coil (601b) to the second synchronous detector output (625). The switches are controlled by two equal and opposite signals (606) and (607), which have the same frequency and are in phase with the received signal picked up by the coil (601).

In the opposite state of the signals, the first switch (604) connect the signal at the second end (601b) of the coil to the first synchronous detector output node (624), and the second switch (605) connects the signal at the first end of the coil (601a) to the second synchronous detector output (625). The first synchronous detector output (624) provides a first input to the first chopper (504), and the second synchronous detector output (625) provides a second input to the first chopper (504). The first chopper (504) has two switches (608) and (609), between the synchronous detector and the instrumentation amplifier (612), which has no feedback components and is fully differential. Each switch may be of the type shown in Fig.8. The chopper is driven by two equal and opposite signals (610) and (611), which have a frequency usually higher than the frequency of the two signals (606) and (607) driving the synchronous detector.

A second chopper, shown as made up of switches (613) and (614), is connected to the outputs of the amplifier (612). Each switch may be of the type shown in Fig.8. The second chopper is driven by two equal and opposite signals (615) and (616) which have the same frequency as the signals (610) and (611) driving the first chopper. A fully differential low-pass filter (507) is used to obtain a DC value, which is offset free.

The operation of the invention can be understood by considering the following embodiment using the waveforms shown in Fig. 7. Assume that the reference voltage is 2.5V and there is mismatch in the value of the resistors of the divider ( 603) so the voltages at the end of the resistive divider are opposite but not equal (701). The synchronous detector, which is made up of switches (604) and (605), is driven with signals (606) and (607), which have the same frequency as the received signal. The outputs of the synchronous demodulator (702) are in the form of respective rectified signals. The difference between these two signals is fixed irrespective of the mismatch of the resistors of the divider. The modulated outputs (703) of the first chopper are connected to the inputs of amplifier (612). An objective of the first chopper scheme is to modulate the outputs of the synchronous detector (702) and the offset of the amplifier (612) into a higher frequency. In one embodiment the chopping frequency is a value selected to be between 3 and 100 times the oscillator frequency; in another the range is between 5 and 10 times the oscillator frequency. The outputs of the differential amplifier (704) include the offset of the amplifier (704a), which has been modulated to a frequency equal to the frequency of the signals (610) and (611) driving the first chopper. The outputs (705) of the second chopper are similar to the outputs (702) of the synchronous detector but the effect of the imbalance has been removed by the differential nature of the synchronous detector and the amplifier. The low-pass filter acts on the difference (706) between the signals (705). As the offset (706a) is modulated into a much higher frequency, it can be easily removed by the low-pass filter action. The output (707) of the low-pass filter as result of the chopping mechanism is free from offset (707a).

The bandwidth of the low-pass filter is selected according to the application and the frequencies of interest. In one embodiment 10kHz-50kHz is the range of interest. In some embodiments, the low pass filter is as simple as a capacitor whose outputs are connected to a differential-input analogue to digital converter.

Referring to Fig. 8, a partial schematic of the synchronous detector of Fig 6 is shown, to illustrate an example of switches usable in the present invention and implemented as complementary MOSFETs. A first switch (801) consists of a pFET (811), and an nFET (812), with their source-drain conduction paths connected mutually in parallel. A second switch (802) consists of a pFET (813), and an nFET (814), with their source-drain conduction paths connected mutually in parallel. First switch (801) is connected between the first end (601a) of the coil (601) and the first synchronous demodulator output node (624). Second switch (802) is connected between the second end (601b) of the coil (601) and the first synchronous demodulator output node (624). The control gates of the pFET (811) of the first switch (801) and of the nFET (814) of the second switch (802) are supplied with a switching signal LO; the control gates of the nFET (812) of the first switch (801) and of the pFET (813) of the second switch (802) are supplied with a switching signal LO .

As will be clear to those in the art LO and LO are never TRUE simultaneously. When LO is true, the nFET (824) of the second switch (802) is conductive by virtue of gate drive and the pFET (811) of the first switch is off; at this time LO is false, so the pFET (813) of the second switch is conductive and the NFET(812) of the first switch (811) is off. Hence second end (601b) of the coil (601) is connected to first synchronous demodulator output node (624), and first end (601a) of the coil (601) is isolated from first synchronous demodulator output node (624).

An embodiment of the invention similar to that of Fig 6 has a plurality of sensor coils, each with its own potential divider. Each coil is switchably connected to a single synchronous detector, having choppers, an amplifier and a filter as shown in Fig 6. This is possible because the architecture does not require offset to be measured separately as it is removed by the chopping mechanism and as result the architecture can handle multiple inputs. Also the architecture is immune from impedance imbalance at the front-end due to the differential operation of the synchronous detector.

In other embodiments, other bias arrangements are provided for the coil. One of these uses a centre-tapped coil, with the tap connected to a reference potential.

An embodiment of the invention with the architecture shown in Fig. 5 and 6 can be used in position sensing applications. The architecture is advantageous compared to the prior art used in position sensing applications with the removal of the amplifier offset and substantial reduction in the impedance imbalance at the front-end. Embodiments do not require the use of a microcontroller to measure the offset prior to every measurement; this results in faster operation, reduced circuit complexity and reduced cost.

A further property of embodiments of this invention is the use of an amplifier (612), which has no feedback components as in the prior art. The main advantage of this is that these feedback components reduce the ability of the amplifier to reject common-mode signals in particular at high frequencies.

In addition, the system employed in this invention is fully differential, which has superior performance compared to single-ended systems as employed in the prior art. The main advantage of differential systems compared to single-ended ones is the ability to reject a noise, which is present at the two differential signal paths. The invention is not restricted to the described features of the embodiments.

Claims

1. A differential-mode measurement circuit having a synchronous detector coupled to a full differential open-loop amplifier via a first chopper, and a second chopper coupled to feed differential signals to a low-pass filter.

2. A differential-mode measurement circuit according to claim 1, having a measurement coil for providing an input signal to be measured, the coil being connected to a bias circuit.

3. A differential-mode measurement circuit according to claim 2, wherein the bias circuit comprises a resistive potential divider having a tap connected to a reference node.

4. A differential-mode measurement circuit according to claim 1 , having a switching device for connecting an arbitrary one of plural measurement coils to the synchronous detector, wherein each coil has a respective bias circuit, the arrangement being such that different dc offsets of different coils are removed by the choppers.

5. A method of measuring an ac signal comprising synchronously detecting the ac signal to provide a detected differential signal; chopping the detected differential signal at a frequency higher than the frequency of the ac signal; applying the chopped signals to an open loop differential-to-differential amplifier; chopping output signals of the differential- to-differential amplifier; and applying the chopped output signals of the differential-to-differential amplifier to a low pass filter.

6. A method according to claim 5, wherein the ac signal is derived from a measurement coil, further comprising biasing the coil so that signals from its ends are substantially differential with respect to a reference potential, whereby common mode is removed by the synchronous detecting step.

7. A measurement circuit having a synchronous detector, an amplifier circuit and a low pass filter; the synchronous detector having a pair of differential input nodes and a pair of differential output nodes and being connected to receive an ac input signal, the amplifier circuit being connected to receive signals from the detector and to output signals to the low pass filter; characterised by: the amplifier circuit being an open loop differential-to-differential amplifier, having two input terminals and two output terminals; a first chopper, having differential input nodes and output nodes, and a second chopper having differential input nodes and output nodes; output nodes of the synchronous detector being connected to the differential input nodes of the first chopper, the differential output nodes of the first chopper being connected respectively to the two input terminals of the open loop differential-to-differential amplifier, the two output terminals of the open loop differential-to-differential amplifier being connected to the differential input nodes of the second chopper; the differential output nodes of the second chopper being connected respectively to the low-pass filter.

8. A measurement circuit according to claim 7 having an input bias circuit including a centre-tapped resistive divider, the tap being connected to a reference voltage, whereby the synchronous detector removes voltage imbalance due to resistor imbalance.